drivers/usb/host/dwc2.c

   1 /*
   2  * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   3  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <usb.h>
  12 #include <malloc.h>
  13 #include <memalign.h>
  14 #include <phys2bus.h>
  15 #include <usbroothubdes.h>
  16 #include <asm/io.h>
  17
  18 #include "dwc2.h"
  19
  20 /* Use only HC channel 0. */
  21 #define DWC2_HC_CHANNEL                 0
  22
  23 #define DWC2_STATUS_BUF_SIZE            64
  24 #define DWC2_DATA_BUF_SIZE              (64 * 1024)
  25
  26 #define MAX_DEVICE                      16
  27 #define MAX_ENDPOINT                    16
  28
  29 struct dwc2_priv {
  30 #ifdef CONFIG_DM_USB
  31         uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  32         uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  33 #else
  34         uint8_t *aligned_buffer;
  35         uint8_t *status_buffer;
  36 #endif
  37         int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  38         struct dwc2_core_regs *regs;
  39         int root_hub_devnum;
  40 };
  41
  42 #ifndef CONFIG_DM_USB
  43 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
  44 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
  45                 ARCH_DMA_MINALIGN);
  46 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
  47                 ARCH_DMA_MINALIGN);
  48
  49 static struct dwc2_priv local;
  50 #endif
  51
  52 /*
  53  * DWC2 IP interface
  54  */
  55 static int wait_for_bit(void *reg, const uint32_t mask, bool set)
  56 {
  57         unsigned int timeout = 1000000;
  58         uint32_t val;
  59
  60         while (--timeout) {
  61                 val = readl(reg);
  62                 if (!set)
  63                         val = ~val;
  64
  65                 if ((val & mask) == mask)
  66                         return 0;
  67
  68                 udelay(1);
  69         }
  70
  71         debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
  72               __func__, reg, mask, set);
  73
  74         return -ETIMEDOUT;
  75 }
  76
  77 /*
  78  * Initializes the FSLSPClkSel field of the HCFG register
  79  * depending on the PHY type.
  80  */
  81 static void init_fslspclksel(struct dwc2_core_regs *regs)
  82 {
  83         uint32_t phyclk;
  84
  85 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  86         phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  87 #else
  88         /* High speed PHY running at full speed or high speed */
  89         phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
  90 #endif
  91
  92 #ifdef CONFIG_DWC2_ULPI_FS_LS
  93         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  94         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  95                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  96         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  97                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  98
  99         if (hval == 2 && fval == 1)
 100                 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
 101 #endif
 102
 103         clrsetbits_le32(&regs->host_regs.hcfg,
 104                         DWC2_HCFG_FSLSPCLKSEL_MASK,
 105                         phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
 106 }
 107
 108 /*
 109  * Flush a Tx FIFO.
 110  *
 111  * @param regs Programming view of DWC_otg controller.
 112  * @param num Tx FIFO to flush.
 113  */
 114 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
 115 {
 116         int ret;
 117
 118         writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
 119                &regs->grstctl);
 120         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
 121         if (ret)
 122                 printf("%s: Timeout!\n", __func__);
 123
 124         /* Wait for 3 PHY Clocks */
 125         udelay(1);
 126 }
 127
 128 /*
 129  * Flush Rx FIFO.
 130  *
 131  * @param regs Programming view of DWC_otg controller.
 132  */
 133 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
 134 {
 135         int ret;
 136
 137         writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
 138         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
 139         if (ret)
 140                 printf("%s: Timeout!\n", __func__);
 141
 142         /* Wait for 3 PHY Clocks */
 143         udelay(1);
 144 }
 145
 146 /*
 147  * Do core a soft reset of the core.  Be careful with this because it
 148  * resets all the internal state machines of the core.
 149  */
 150 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
 151 {
 152         int ret;
 153
 154         /* Wait for AHB master IDLE state. */
 155         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
 156         if (ret)
 157                 printf("%s: Timeout!\n", __func__);
 158
 159         /* Core Soft Reset */
 160         writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
 161         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
 162         if (ret)
 163                 printf("%s: Timeout!\n", __func__);
 164
 165         /*
 166          * Wait for core to come out of reset.
 167          * NOTE: This long sleep is _very_ important, otherwise the core will
 168          *       not stay in host mode after a connector ID change!
 169          */
 170         mdelay(100);
 171 }
 172
 173 /*
 174  * This function initializes the DWC_otg controller registers for
 175  * host mode.
 176  *
 177  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
 178  * request queues. Host channels are reset to ensure that they are ready for
 179  * performing transfers.
 180  *
 181  * @param regs Programming view of DWC_otg controller
 182  *
 183  */
 184 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
 185 {
 186         uint32_t nptxfifosize = 0;
 187         uint32_t ptxfifosize = 0;
 188         uint32_t hprt0 = 0;
 189         int i, ret, num_channels;
 190
 191         /* Restart the Phy Clock */
 192         writel(0, &regs->pcgcctl);
 193
 194         /* Initialize Host Configuration Register */
 195         init_fslspclksel(regs);
 196 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
 197         setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
 198 #endif
 199
 200         /* Configure data FIFO sizes */
 201 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
 202         if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
 203                 /* Rx FIFO */
 204                 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
 205
 206                 /* Non-periodic Tx FIFO */
 207                 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
 208                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 209                 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
 210                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 211                 writel(nptxfifosize, &regs->gnptxfsiz);
 212
 213                 /* Periodic Tx FIFO */
 214                 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
 215                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 216                 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
 217                                 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
 218                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 219                 writel(ptxfifosize, &regs->hptxfsiz);
 220         }
 221 #endif
 222
 223         /* Clear Host Set HNP Enable in the OTG Control Register */
 224         clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
 225
 226         /* Make sure the FIFOs are flushed. */
 227         dwc_otg_flush_tx_fifo(regs, 0x10);      /* All Tx FIFOs */
 228         dwc_otg_flush_rx_fifo(regs);
 229
 230         /* Flush out any leftover queued requests. */
 231         num_channels = readl(&regs->ghwcfg2);
 232         num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
 233         num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
 234         num_channels += 1;
 235
 236         for (i = 0; i < num_channels; i++)
 237                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 238                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
 239                                 DWC2_HCCHAR_CHDIS);
 240
 241         /* Halt all channels to put them into a known state. */
 242         for (i = 0; i < num_channels; i++) {
 243                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 244                                 DWC2_HCCHAR_EPDIR,
 245                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
 246                 ret = wait_for_bit(&regs->hc_regs[i].hcchar,
 247                                    DWC2_HCCHAR_CHEN, 0);
 248                 if (ret)
 249                         printf("%s: Timeout!\n", __func__);
 250         }
 251
 252         /* Turn on the vbus power. */
 253         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
 254                 hprt0 = readl(&regs->hprt0);
 255                 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
 256                 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
 257                 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
 258                         hprt0 |= DWC2_HPRT0_PRTPWR;
 259                         writel(hprt0, &regs->hprt0);
 260                 }
 261         }
 262 }
 263
 264 /*
 265  * This function initializes the DWC_otg controller registers and
 266  * prepares the core for device mode or host mode operation.
 267  *
 268  * @param regs Programming view of the DWC_otg controller
 269  */
 270 static void dwc_otg_core_init(struct dwc2_core_regs *regs)
 271 {
 272         uint32_t ahbcfg = 0;
 273         uint32_t usbcfg = 0;
 274         uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
 275
 276         /* Common Initialization */
 277         usbcfg = readl(&regs->gusbcfg);
 278
 279         /* Program the ULPI External VBUS bit if needed */
 280 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
 281         usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 282 #else
 283         usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 284 #endif
 285
 286         /* Set external TS Dline pulsing */
 287 #ifdef CONFIG_DWC2_TS_DLINE
 288         usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 289 #else
 290         usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 291 #endif
 292         writel(usbcfg, &regs->gusbcfg);
 293
 294         /* Reset the Controller */
 295         dwc_otg_core_reset(regs);
 296
 297         /*
 298          * This programming sequence needs to happen in FS mode before
 299          * any other programming occurs
 300          */
 301 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
 302         (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
 303         /* If FS mode with FS PHY */
 304         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
 305
 306         /* Reset after a PHY select */
 307         dwc_otg_core_reset(regs);
 308
 309         /*
 310          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
 311          * Also do this on HNP Dev/Host mode switches (done in dev_init
 312          * and host_init).
 313          */
 314         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
 315                 init_fslspclksel(regs);
 316
 317 #ifdef CONFIG_DWC2_I2C_ENABLE
 318         /* Program GUSBCFG.OtgUtmifsSel to I2C */
 319         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
 320
 321         /* Program GI2CCTL.I2CEn */
 322         clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
 323                         DWC2_GI2CCTL_I2CDEVADDR_MASK,
 324                         1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
 325         setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
 326 #endif
 327
 328 #else
 329         /* High speed PHY. */
 330
 331         /*
 332          * HS PHY parameters. These parameters are preserved during
 333          * soft reset so only program the first time. Do a soft reset
 334          * immediately after setting phyif.
 335          */
 336         usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
 337         usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
 338
 339         if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) {      /* ULPI interface */
 340 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
 341                 usbcfg |= DWC2_GUSBCFG_DDRSEL;
 342 #else
 343                 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
 344 #endif
 345         } else {        /* UTMI+ interface */
 346 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
 347                 usbcfg |= DWC2_GUSBCFG_PHYIF;
 348 #endif
 349         }
 350
 351         writel(usbcfg, &regs->gusbcfg);
 352
 353         /* Reset after setting the PHY parameters */
 354         dwc_otg_core_reset(regs);
 355 #endif
 356
 357         usbcfg = readl(&regs->gusbcfg);
 358         usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
 359 #ifdef CONFIG_DWC2_ULPI_FS_LS
 360         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
 361         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
 362                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
 363         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
 364                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
 365         if (hval == 2 && fval == 1) {
 366                 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
 367                 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
 368         }
 369 #endif
 370         writel(usbcfg, &regs->gusbcfg);
 371
 372         /* Program the GAHBCFG Register. */
 373         switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
 374         case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
 375                 break;
 376         case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
 377                 while (brst_sz > 1) {
 378                         ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
 379                         ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
 380                         brst_sz >>= 1;
 381                 }
 382
 383 #ifdef CONFIG_DWC2_DMA_ENABLE
 384                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 385 #endif
 386                 break;
 387
 388         case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
 389                 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
 390 #ifdef CONFIG_DWC2_DMA_ENABLE
 391                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 392 #endif
 393                 break;
 394         }
 395
 396         writel(ahbcfg, &regs->gahbcfg);
 397
 398         /* Program the GUSBCFG register for HNP/SRP. */
 399         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
 400
 401 #ifdef CONFIG_DWC2_IC_USB_CAP
 402         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
 403 #endif
 404 }
 405
 406 /*
 407  * Prepares a host channel for transferring packets to/from a specific
 408  * endpoint. The HCCHARn register is set up with the characteristics specified
 409  * in _hc. Host channel interrupts that may need to be serviced while this
 410  * transfer is in progress are enabled.
 411  *
 412  * @param regs Programming view of DWC_otg controller
 413  * @param hc Information needed to initialize the host channel
 414  */
 415 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
 416                 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
 417                 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
 418 {
 419         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
 420         uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
 421                           (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
 422                           (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
 423                           (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
 424                           (max_packet << DWC2_HCCHAR_MPS_OFFSET);
 425
 426         if (dev->speed == USB_SPEED_LOW)
 427                 hcchar |= DWC2_HCCHAR_LSPDDEV;
 428
 429         /*
 430          * Program the HCCHARn register with the endpoint characteristics
 431          * for the current transfer.
 432          */
 433         writel(hcchar, &hc_regs->hcchar);
 434
 435         /* Program the HCSPLIT register, default to no SPLIT */
 436         writel(0, &hc_regs->hcsplt);
 437 }
 438
 439 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
 440                                   uint8_t hub_devnum, uint8_t hub_port)
 441 {
 442         uint32_t hcsplt = 0;
 443
 444         hcsplt = DWC2_HCSPLT_SPLTENA;
 445         hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
 446         hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
 447
 448         /* Program the HCSPLIT register for SPLITs */
 449         writel(hcsplt, &hc_regs->hcsplt);
 450 }
 451
 452 /*
 453  * DWC2 to USB API interface
 454  */
 455 /* Direction: In ; Request: Status */
 456 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
 457                                            struct usb_device *dev, void *buffer,
 458                                            int txlen, struct devrequest *cmd)
 459 {
 460         uint32_t hprt0 = 0;
 461         uint32_t port_status = 0;
 462         uint32_t port_change = 0;
 463         int len = 0;
 464         int stat = 0;
 465
 466         switch (cmd->requesttype & ~USB_DIR_IN) {
 467         case 0:
 468                 *(uint16_t *)buffer = cpu_to_le16(1);
 469                 len = 2;
 470                 break;
 471         case USB_RECIP_INTERFACE:
 472         case USB_RECIP_ENDPOINT:
 473                 *(uint16_t *)buffer = cpu_to_le16(0);
 474                 len = 2;
 475                 break;
 476         case USB_TYPE_CLASS:
 477                 *(uint32_t *)buffer = cpu_to_le32(0);
 478                 len = 4;
 479                 break;
 480         case USB_RECIP_OTHER | USB_TYPE_CLASS:
 481                 hprt0 = readl(&regs->hprt0);
 482                 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
 483                         port_status |= USB_PORT_STAT_CONNECTION;
 484                 if (hprt0 & DWC2_HPRT0_PRTENA)
 485                         port_status |= USB_PORT_STAT_ENABLE;
 486                 if (hprt0 & DWC2_HPRT0_PRTSUSP)
 487                         port_status |= USB_PORT_STAT_SUSPEND;
 488                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
 489                         port_status |= USB_PORT_STAT_OVERCURRENT;
 490                 if (hprt0 & DWC2_HPRT0_PRTRST)
 491                         port_status |= USB_PORT_STAT_RESET;
 492                 if (hprt0 & DWC2_HPRT0_PRTPWR)
 493                         port_status |= USB_PORT_STAT_POWER;
 494
 495                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
 496                         port_status |= USB_PORT_STAT_LOW_SPEED;
 497                 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 498                          DWC2_HPRT0_PRTSPD_HIGH)
 499                         port_status |= USB_PORT_STAT_HIGH_SPEED;
 500
 501                 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
 502                         port_change |= USB_PORT_STAT_C_ENABLE;
 503                 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
 504                         port_change |= USB_PORT_STAT_C_CONNECTION;
 505                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
 506                         port_change |= USB_PORT_STAT_C_OVERCURRENT;
 507
 508                 *(uint32_t *)buffer = cpu_to_le32(port_status |
 509                                         (port_change << 16));
 510                 len = 4;
 511                 break;
 512         default:
 513                 puts("unsupported root hub command\n");
 514                 stat = USB_ST_STALLED;
 515         }
 516
 517         dev->act_len = min(len, txlen);
 518         dev->status = stat;
 519
 520         return stat;
 521 }
 522
 523 /* Direction: In ; Request: Descriptor */
 524 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
 525                                                void *buffer, int txlen,
 526                                                struct devrequest *cmd)
 527 {
 528         unsigned char data[32];
 529         uint32_t dsc;
 530         int len = 0;
 531         int stat = 0;
 532         uint16_t wValue = cpu_to_le16(cmd->value);
 533         uint16_t wLength = cpu_to_le16(cmd->length);
 534
 535         switch (cmd->requesttype & ~USB_DIR_IN) {
 536         case 0:
 537                 switch (wValue & 0xff00) {
 538                 case 0x0100:    /* device descriptor */
 539                         len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
 540                         memcpy(buffer, root_hub_dev_des, len);
 541                         break;
 542                 case 0x0200:    /* configuration descriptor */
 543                         len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
 544                         memcpy(buffer, root_hub_config_des, len);
 545                         break;
 546                 case 0x0300:    /* string descriptors */
 547                         switch (wValue & 0xff) {
 548                         case 0x00:
 549                                 len = min3(txlen, (int)sizeof(root_hub_str_index0),
 550                                            (int)wLength);
 551                                 memcpy(buffer, root_hub_str_index0, len);
 552                                 break;
 553                         case 0x01:
 554                                 len = min3(txlen, (int)sizeof(root_hub_str_index1),
 555                                            (int)wLength);
 556                                 memcpy(buffer, root_hub_str_index1, len);
 557                                 break;
 558                         }
 559                         break;
 560                 default:
 561                         stat = USB_ST_STALLED;
 562                 }
 563                 break;
 564
 565         case USB_TYPE_CLASS:
 566                 /* Root port config, set 1 port and nothing else. */
 567                 dsc = 0x00000001;
 568
 569                 data[0] = 9;            /* min length; */
 570                 data[1] = 0x29;
 571                 data[2] = dsc & RH_A_NDP;
 572                 data[3] = 0;
 573                 if (dsc & RH_A_PSM)
 574                         data[3] |= 0x1;
 575                 if (dsc & RH_A_NOCP)
 576                         data[3] |= 0x10;
 577                 else if (dsc & RH_A_OCPM)
 578                         data[3] |= 0x8;
 579
 580                 /* corresponds to data[4-7] */
 581                 data[5] = (dsc & RH_A_POTPGT) >> 24;
 582                 data[7] = dsc & RH_B_DR;
 583                 if (data[2] < 7) {
 584                         data[8] = 0xff;
 585                 } else {
 586                         data[0] += 2;
 587                         data[8] = (dsc & RH_B_DR) >> 8;
 588                         data[9] = 0xff;
 589                         data[10] = data[9];
 590                 }
 591
 592                 len = min3(txlen, (int)data[0], (int)wLength);
 593                 memcpy(buffer, data, len);
 594                 break;
 595         default:
 596                 puts("unsupported root hub command\n");
 597                 stat = USB_ST_STALLED;
 598         }
 599
 600         dev->act_len = min(len, txlen);
 601         dev->status = stat;
 602
 603         return stat;
 604 }
 605
 606 /* Direction: In ; Request: Configuration */
 607 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
 608                                                   void *buffer, int txlen,
 609                                                   struct devrequest *cmd)
 610 {
 611         int len = 0;
 612         int stat = 0;
 613
 614         switch (cmd->requesttype & ~USB_DIR_IN) {
 615         case 0:
 616                 *(uint8_t *)buffer = 0x01;
 617                 len = 1;
 618                 break;
 619         default:
 620                 puts("unsupported root hub command\n");
 621                 stat = USB_ST_STALLED;
 622         }
 623
 624         dev->act_len = min(len, txlen);
 625         dev->status = stat;
 626
 627         return stat;
 628 }
 629
 630 /* Direction: In */
 631 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
 632                                     struct usb_device *dev, void *buffer,
 633                                     int txlen, struct devrequest *cmd)
 634 {
 635         switch (cmd->request) {
 636         case USB_REQ_GET_STATUS:
 637                 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
 638                                                        txlen, cmd);
 639         case USB_REQ_GET_DESCRIPTOR:
 640                 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
 641                                                            txlen, cmd);
 642         case USB_REQ_GET_CONFIGURATION:
 643                 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
 644                                                               txlen, cmd);
 645         default:
 646                 puts("unsupported root hub command\n");
 647                 return USB_ST_STALLED;
 648         }
 649 }
 650
 651 /* Direction: Out */
 652 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
 653                                      struct usb_device *dev,
 654                                      void *buffer, int txlen,
 655                                      struct devrequest *cmd)
 656 {
 657         struct dwc2_core_regs *regs = priv->regs;
 658         int len = 0;
 659         int stat = 0;
 660         uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
 661         uint16_t wValue = cpu_to_le16(cmd->value);
 662
 663         switch (bmrtype_breq & ~USB_DIR_IN) {
 664         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
 665         case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
 666                 break;
 667
 668         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 669                 switch (wValue) {
 670                 case USB_PORT_FEAT_C_CONNECTION:
 671                         setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
 672                         break;
 673                 }
 674                 break;
 675
 676         case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 677                 switch (wValue) {
 678                 case USB_PORT_FEAT_SUSPEND:
 679                         break;
 680
 681                 case USB_PORT_FEAT_RESET:
 682                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 683                                         DWC2_HPRT0_PRTCONNDET |
 684                                         DWC2_HPRT0_PRTENCHNG |
 685                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 686                                         DWC2_HPRT0_PRTRST);
 687                         mdelay(50);
 688                         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
 689                         break;
 690
 691                 case USB_PORT_FEAT_POWER:
 692                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 693                                         DWC2_HPRT0_PRTCONNDET |
 694                                         DWC2_HPRT0_PRTENCHNG |
 695                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 696                                         DWC2_HPRT0_PRTRST);
 697                         break;
 698
 699                 case USB_PORT_FEAT_ENABLE:
 700                         break;
 701                 }
 702                 break;
 703         case (USB_REQ_SET_ADDRESS << 8):
 704                 priv->root_hub_devnum = wValue;
 705                 break;
 706         case (USB_REQ_SET_CONFIGURATION << 8):
 707                 break;
 708         default:
 709                 puts("unsupported root hub command\n");
 710                 stat = USB_ST_STALLED;
 711         }
 712
 713         len = min(len, txlen);
 714
 715         dev->act_len = len;
 716         dev->status = stat;
 717
 718         return stat;
 719 }
 720
 721 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
 722                                  unsigned long pipe, void *buffer, int txlen,
 723                                  struct devrequest *cmd)
 724 {
 725         int stat = 0;
 726
 727         if (usb_pipeint(pipe)) {
 728                 puts("Root-Hub submit IRQ: NOT implemented\n");
 729                 return 0;
 730         }
 731
 732         if (cmd->requesttype & USB_DIR_IN)
 733                 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
 734         else
 735                 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
 736
 737         mdelay(1);
 738
 739         return stat;
 740 }
 741
 742 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, int *toggle)
 743 {
 744         int ret;
 745         uint32_t hcint, hctsiz;
 746
 747         ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true);
 748         if (ret)
 749                 return ret;
 750
 751         hcint = readl(&hc_regs->hcint);
 752         hctsiz = readl(&hc_regs->hctsiz);
 753         *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
 754                 DWC2_HCTSIZ_XFERSIZE_OFFSET;
 755         *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
 756
 757         debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
 758               *toggle);
 759
 760         if (hcint & DWC2_HCINT_XFERCOMP)
 761                 return 0;
 762
 763         if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
 764                 return -EAGAIN;
 765
 766         debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
 767         return -EINVAL;
 768 }
 769
 770 static int dwc2_eptype[] = {
 771         DWC2_HCCHAR_EPTYPE_ISOC,
 772         DWC2_HCCHAR_EPTYPE_INTR,
 773         DWC2_HCCHAR_EPTYPE_CONTROL,
 774         DWC2_HCCHAR_EPTYPE_BULK,
 775 };
 776
 777 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
 778                           int *pid, int in, void *buffer, int num_packets,
 779                           int xfer_len, int *actual_len)
 780 {
 781         int ret = 0;
 782         uint32_t sub;
 783
 784         debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
 785               *pid, xfer_len, num_packets);
 786
 787         writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
 788                (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
 789                (*pid << DWC2_HCTSIZ_PID_OFFSET),
 790                &hc_regs->hctsiz);
 791
 792         if (!in && xfer_len) {
 793                 memcpy(aligned_buffer, buffer, xfer_len);
 794
 795                 flush_dcache_range((unsigned long)aligned_buffer,
 796                                    (unsigned long)aligned_buffer +
 797                                    roundup(xfer_len, ARCH_DMA_MINALIGN));
 798         }
 799
 800         writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
 801
 802         /* Clear old interrupt conditions for this host channel. */
 803         writel(0x3fff, &hc_regs->hcint);
 804
 805         /* Set host channel enable after all other setup is complete. */
 806         clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
 807                         DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
 808                         (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
 809                         DWC2_HCCHAR_CHEN);
 810
 811         ret = wait_for_chhltd(hc_regs, &sub, pid);
 812         if (ret < 0)
 813                 return ret;
 814
 815         if (in) {
 816                 xfer_len -= sub;
 817
 818                 invalidate_dcache_range((unsigned long)aligned_buffer,
 819                                         (unsigned long)aligned_buffer +
 820                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 821
 822                 memcpy(buffer, aligned_buffer, xfer_len);
 823         }
 824         *actual_len = xfer_len;
 825
 826         return ret;
 827 }
 828
 829 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 830               unsigned long pipe, int *pid, int in, void *buffer, int len)
 831 {
 832         struct dwc2_core_regs *regs = priv->regs;
 833         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 834         int devnum = usb_pipedevice(pipe);
 835         int ep = usb_pipeendpoint(pipe);
 836         int max = usb_maxpacket(dev, pipe);
 837         int eptype = dwc2_eptype[usb_pipetype(pipe)];
 838         int done = 0;
 839         int ret = 0;
 840         int do_split = 0;
 841         int complete_split = 0;
 842         uint32_t xfer_len;
 843         uint32_t num_packets;
 844         int stop_transfer = 0;
 845         uint32_t max_xfer_len;
 846
 847         debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
 848               in, len);
 849
 850         max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
 851         if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
 852                 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
 853         if (max_xfer_len > DWC2_DATA_BUF_SIZE)
 854                 max_xfer_len = DWC2_DATA_BUF_SIZE;
 855
 856         /* Make sure that max_xfer_len is a multiple of max packet size. */
 857         num_packets = max_xfer_len / max;
 858         max_xfer_len = num_packets * max;
 859
 860         /* Initialize channel */
 861         dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
 862                         eptype, max);
 863
 864         /* Check if the target is a FS/LS device behind a HS hub */
 865         if (dev->speed != USB_SPEED_HIGH) {
 866                 uint8_t hub_addr;
 867                 uint8_t hub_port;
 868                 uint32_t hprt0 = readl(&regs->hprt0);
 869                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 870                      DWC2_HPRT0_PRTSPD_HIGH) {
 871                         usb_find_usb2_hub_address_port(dev, &hub_addr,
 872                                                        &hub_port);
 873                         dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
 874
 875                         do_split = 1;
 876                         num_packets = 1;
 877                         max_xfer_len = max;
 878                 }
 879         }
 880
 881         do {
 882                 int actual_len = 0;
 883                 uint32_t hcint;
 884                 xfer_len = len - done;
 885
 886                 if (xfer_len > max_xfer_len)
 887                         xfer_len = max_xfer_len;
 888                 else if (xfer_len > max)
 889                         num_packets = (xfer_len + max - 1) / max;
 890                 else
 891                         num_packets = 1;
 892
 893                 if (complete_split)
 894                         setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 895                 else if (do_split)
 896                         clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 897
 898                 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
 899                                      in, (char *)buffer + done, num_packets,
 900                                      xfer_len, &actual_len);
 901
 902                 hcint = readl(&hc_regs->hcint);
 903                 if (complete_split) {
 904                         stop_transfer = 0;
 905                         if (hcint & DWC2_HCINT_NYET)
 906                                 ret = 0;
 907                         else
 908                                 complete_split = 0;
 909                 } else if (do_split) {
 910                         if (hcint & DWC2_HCINT_ACK) {
 911                                 ret = 0;
 912                                 complete_split = 1;
 913                         }
 914                 }
 915
 916                 if (ret)
 917                         break;
 918
 919                 if (actual_len < xfer_len)
 920                         stop_transfer = 1;
 921
 922                 done += actual_len;
 923
 924         /* Transactions are done when when either all data is transferred or
 925          * there is a short transfer. In case of a SPLIT make sure the CSPLIT
 926          * is executed.
 927          */
 928         } while (((done < len) && !stop_transfer) || complete_split);
 929
 930         writel(0, &hc_regs->hcintmsk);
 931         writel(0xFFFFFFFF, &hc_regs->hcint);
 932
 933         dev->status = 0;
 934         dev->act_len = done;
 935
 936         return ret;
 937 }
 938
 939 /* U-Boot USB transmission interface */
 940 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 941                      unsigned long pipe, void *buffer, int len)
 942 {
 943         int devnum = usb_pipedevice(pipe);
 944         int ep = usb_pipeendpoint(pipe);
 945
 946         if (devnum == priv->root_hub_devnum) {
 947                 dev->status = 0;
 948                 return -EINVAL;
 949         }
 950
 951         return chunk_msg(priv, dev, pipe, &priv->bulk_data_toggle[devnum][ep],
 952                          usb_pipein(pipe), buffer, len);
 953 }
 954
 955 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
 956                                unsigned long pipe, void *buffer, int len,
 957                                struct devrequest *setup)
 958 {
 959         int devnum = usb_pipedevice(pipe);
 960         int pid, ret, act_len;
 961         /* For CONTROL endpoint pid should start with DATA1 */
 962         int status_direction;
 963
 964         if (devnum == priv->root_hub_devnum) {
 965                 dev->status = 0;
 966                 dev->speed = USB_SPEED_HIGH;
 967                 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
 968                                              setup);
 969         }
 970
 971         /* SETUP stage */
 972         pid = DWC2_HC_PID_SETUP;
 973         do {
 974                 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
 975         } while (ret == -EAGAIN);
 976         if (ret)
 977                 return ret;
 978
 979         /* DATA stage */
 980         act_len = 0;
 981         if (buffer) {
 982                 pid = DWC2_HC_PID_DATA1;
 983                 do {
 984                         ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
 985                                         buffer, len);
 986                         act_len += dev->act_len;
 987                         buffer += dev->act_len;
 988                         len -= dev->act_len;
 989                 } while (ret == -EAGAIN);
 990                 if (ret)
 991                         return ret;
 992                 status_direction = usb_pipeout(pipe);
 993         } else {
 994                 /* No-data CONTROL always ends with an IN transaction */
 995                 status_direction = 1;
 996         }
 997
 998         /* STATUS stage */
 999         pid = DWC2_HC_PID_DATA1;
1000         do {
1001                 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1002                                 priv->status_buffer, 0);
1003         } while (ret == -EAGAIN);
1004         if (ret)
1005                 return ret;
1006
1007         dev->act_len = act_len;
1008
1009         return 0;
1010 }
1011
1012 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1013                     unsigned long pipe, void *buffer, int len, int interval)
1014 {
1015         unsigned long timeout;
1016         int ret;
1017
1018         /* FIXME: what is interval? */
1019
1020         timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1021         for (;;) {
1022                 if (get_timer(0) > timeout) {
1023                         printf("Timeout poll on interrupt endpoint\n");
1024                         return -ETIMEDOUT;
1025                 }
1026                 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1027                 if (ret != -EAGAIN)
1028                         return ret;
1029         }
1030 }
1031
1032 static int dwc2_init_common(struct dwc2_priv *priv)
1033 {
1034         struct dwc2_core_regs *regs = priv->regs;
1035         uint32_t snpsid;
1036         int i, j;
1037
1038         snpsid = readl(&regs->gsnpsid);
1039         printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
1040
1041         if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1042             (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1043                 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
1044                 return -ENODEV;
1045         }
1046
1047         dwc_otg_core_init(regs);
1048         dwc_otg_core_host_init(regs);
1049
1050         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1051                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1052                         DWC2_HPRT0_PRTOVRCURRCHNG,
1053                         DWC2_HPRT0_PRTRST);
1054         mdelay(50);
1055         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1056                      DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1057                      DWC2_HPRT0_PRTRST);
1058
1059         for (i = 0; i < MAX_DEVICE; i++) {
1060                 for (j = 0; j < MAX_ENDPOINT; j++)
1061                         priv->bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1062         }
1063
1064         return 0;
1065 }
1066
1067 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1068 {
1069         /* Put everything in reset. */
1070         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1071                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1072                         DWC2_HPRT0_PRTOVRCURRCHNG,
1073                         DWC2_HPRT0_PRTRST);
1074 }
1075
1076 #ifndef CONFIG_DM_USB
1077 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1078                        int len, struct devrequest *setup)
1079 {
1080         return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1081 }
1082
1083 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1084                     int len)
1085 {
1086         return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1087 }
1088
1089 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1090                    int len, int interval)
1091 {
1092         return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1093 }
1094
1095 /* U-Boot USB control interface */
1096 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1097 {
1098         struct dwc2_priv *priv = &local;
1099
1100         memset(priv, '\0', sizeof(*priv));
1101         priv->root_hub_devnum = 0;
1102         priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1103         priv->aligned_buffer = aligned_buffer_addr;
1104         priv->status_buffer = status_buffer_addr;
1105
1106         /* board-dependant init */
1107         if (board_usb_init(index, USB_INIT_HOST))
1108                 return -1;
1109
1110         return dwc2_init_common(priv);
1111 }
1112
1113 int usb_lowlevel_stop(int index)
1114 {
1115         dwc2_uninit_common(local.regs);
1116
1117         return 0;
1118 }
1119 #endif
1120
1121 #ifdef CONFIG_DM_USB
1122 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1123                                    unsigned long pipe, void *buffer, int length,
1124                                    struct devrequest *setup)
1125 {
1126         struct dwc2_priv *priv = dev_get_priv(dev);
1127
1128         debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1129               dev->name, udev, udev->dev->name, udev->portnr);
1130
1131         return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1132 }
1133
1134 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1135                                 unsigned long pipe, void *buffer, int length)
1136 {
1137         struct dwc2_priv *priv = dev_get_priv(dev);
1138
1139         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1140
1141         return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1142 }
1143
1144 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1145                                unsigned long pipe, void *buffer, int length,
1146                                int interval)
1147 {
1148         struct dwc2_priv *priv = dev_get_priv(dev);
1149
1150         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1151
1152         return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1153 }
1154
1155 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1156 {
1157         struct dwc2_priv *priv = dev_get_priv(dev);
1158         fdt_addr_t addr;
1159
1160         addr = dev_get_addr(dev);
1161         if (addr == FDT_ADDR_T_NONE)
1162                 return -EINVAL;
1163         priv->regs = (struct dwc2_core_regs *)addr;
1164
1165         return 0;
1166 }
1167
1168 static int dwc2_usb_probe(struct udevice *dev)
1169 {
1170         struct dwc2_priv *priv = dev_get_priv(dev);
1171
1172         return dwc2_init_common(priv);
1173 }
1174
1175 static int dwc2_usb_remove(struct udevice *dev)
1176 {
1177         struct dwc2_priv *priv = dev_get_priv(dev);
1178
1179         dwc2_uninit_common(priv->regs);
1180
1181         return 0;
1182 }
1183
1184 struct dm_usb_ops dwc2_usb_ops = {
1185         .control = dwc2_submit_control_msg,
1186         .bulk = dwc2_submit_bulk_msg,
1187         .interrupt = dwc2_submit_int_msg,
1188 };
1189
1190 static const struct udevice_id dwc2_usb_ids[] = {
1191         { .compatible = "brcm,bcm2835-usb" },
1192         { .compatible = "snps,dwc2" },
1193         { }
1194 };
1195
1196 U_BOOT_DRIVER(usb_dwc2) = {
1197         .name   = "dwc2_usb",
1198         .id     = UCLASS_USB,
1199         .of_match = dwc2_usb_ids,
1200         .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1201         .probe  = dwc2_usb_probe,
1202         .remove = dwc2_usb_remove,
1203         .ops    = &dwc2_usb_ops,
1204         .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1205         .flags  = DM_FLAG_ALLOC_PRIV_DMA,
1206 };
1207 #endif