1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
4 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
12 #include <generic-phy.h>
18 #include <usbroothubdes.h>
20 #include <asm/cache.h>
22 #include <dm/device_compat.h>
23 #include <power/regulator.h>
28 /* Use only HC channel 0. */
29 #define DWC2_HC_CHANNEL 0
31 #define DWC2_STATUS_BUF_SIZE 64
32 #define DWC2_DATA_BUF_SIZE (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
35 #define MAX_ENDPOINT 16
38 #if CONFIG_IS_ENABLED(DM_USB)
39 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
40 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
41 #ifdef CONFIG_DM_REGULATOR
42 struct udevice *vbus_supply;
47 uint8_t *aligned_buffer;
48 uint8_t *status_buffer;
50 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
51 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
52 struct dwc2_core_regs *regs;
56 * The hnp/srp capability must be disabled if the platform
57 * does't support hnp/srp. Otherwise the force mode can't work.
62 struct reset_ctl_bulk resets;
65 #if !CONFIG_IS_ENABLED(DM_USB)
66 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
67 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
69 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
72 static struct dwc2_priv local;
80 * Initializes the FSLSPClkSel field of the HCFG register
81 * depending on the PHY type.
83 static void init_fslspclksel(struct dwc2_core_regs *regs)
87 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
88 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
90 /* High speed PHY running at full speed or high speed */
91 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
94 #ifdef CONFIG_DWC2_ULPI_FS_LS
95 uint32_t hwcfg2 = readl(®s->ghwcfg2);
96 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
97 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
98 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
99 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
101 if (hval == 2 && fval == 1)
102 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
105 clrsetbits_le32(®s->host_regs.hcfg,
106 DWC2_HCFG_FSLSPCLKSEL_MASK,
107 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
113 * @param regs Programming view of DWC_otg controller.
114 * @param num Tx FIFO to flush.
116 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
120 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
122 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_TXFFLSH,
125 dev_info(dev, "%s: Timeout!\n", __func__);
127 /* Wait for 3 PHY Clocks */
134 * @param regs Programming view of DWC_otg controller.
136 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
140 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
141 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_RXFFLSH,
144 dev_info(dev, "%s: Timeout!\n", __func__);
146 /* Wait for 3 PHY Clocks */
151 * Do core a soft reset of the core. Be careful with this because it
152 * resets all the internal state machines of the core.
154 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
158 /* Wait for AHB master IDLE state. */
159 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_AHBIDLE,
162 dev_info(dev, "%s: Timeout!\n", __func__);
164 /* Core Soft Reset */
165 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
166 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_CSFTRST,
169 dev_info(dev, "%s: Timeout!\n", __func__);
172 * Wait for core to come out of reset.
173 * NOTE: This long sleep is _very_ important, otherwise the core will
174 * not stay in host mode after a connector ID change!
179 #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR)
180 static int dwc_vbus_supply_init(struct udevice *dev)
182 struct dwc2_priv *priv = dev_get_priv(dev);
185 ret = device_get_supply_regulator(dev, "vbus-supply",
188 debug("%s: No vbus supply\n", dev->name);
192 ret = regulator_set_enable(priv->vbus_supply, true);
194 dev_err(dev, "Error enabling vbus supply\n");
201 static int dwc_vbus_supply_exit(struct udevice *dev)
203 struct dwc2_priv *priv = dev_get_priv(dev);
206 if (priv->vbus_supply) {
207 ret = regulator_set_enable(priv->vbus_supply, false);
209 dev_err(dev, "Error disabling vbus supply\n");
217 static int dwc_vbus_supply_init(struct udevice *dev)
222 #if CONFIG_IS_ENABLED(DM_USB)
223 static int dwc_vbus_supply_exit(struct udevice *dev)
231 * This function initializes the DWC_otg controller registers for
234 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
235 * request queues. Host channels are reset to ensure that they are ready for
236 * performing transfers.
238 * @param dev USB Device (NULL if driver model is not being used)
239 * @param regs Programming view of DWC_otg controller
242 static void dwc_otg_core_host_init(struct udevice *dev,
243 struct dwc2_core_regs *regs)
245 uint32_t nptxfifosize = 0;
246 uint32_t ptxfifosize = 0;
248 int i, ret, num_channels;
250 /* Restart the Phy Clock */
251 writel(0, ®s->pcgcctl);
253 /* Initialize Host Configuration Register */
254 init_fslspclksel(regs);
255 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
256 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
259 /* Configure data FIFO sizes */
260 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
261 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
263 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
265 /* Non-periodic Tx FIFO */
266 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
267 DWC2_FIFOSIZE_DEPTH_OFFSET;
268 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
269 DWC2_FIFOSIZE_STARTADDR_OFFSET;
270 writel(nptxfifosize, ®s->gnptxfsiz);
272 /* Periodic Tx FIFO */
273 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
274 DWC2_FIFOSIZE_DEPTH_OFFSET;
275 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
276 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
277 DWC2_FIFOSIZE_STARTADDR_OFFSET;
278 writel(ptxfifosize, ®s->hptxfsiz);
282 /* Clear Host Set HNP Enable in the OTG Control Register */
283 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
285 /* Make sure the FIFOs are flushed. */
286 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
287 dwc_otg_flush_rx_fifo(regs);
289 /* Flush out any leftover queued requests. */
290 num_channels = readl(®s->ghwcfg2);
291 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
292 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
295 for (i = 0; i < num_channels; i++)
296 clrsetbits_le32(®s->hc_regs[i].hcchar,
297 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
300 /* Halt all channels to put them into a known state. */
301 for (i = 0; i < num_channels; i++) {
302 clrsetbits_le32(®s->hc_regs[i].hcchar,
304 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
305 ret = wait_for_bit_le32(®s->hc_regs[i].hcchar,
306 DWC2_HCCHAR_CHEN, false, 1000, false);
308 dev_info("%s: Timeout!\n", __func__);
311 /* Turn on the vbus power. */
312 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
313 hprt0 = readl(®s->hprt0);
314 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
315 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
316 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
317 hprt0 |= DWC2_HPRT0_PRTPWR;
318 writel(hprt0, ®s->hprt0);
323 dwc_vbus_supply_init(dev);
327 * This function initializes the DWC_otg controller registers and
328 * prepares the core for device mode or host mode operation.
330 * @param regs Programming view of the DWC_otg controller
332 static void dwc_otg_core_init(struct dwc2_priv *priv)
334 struct dwc2_core_regs *regs = priv->regs;
337 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
339 /* Common Initialization */
340 usbcfg = readl(®s->gusbcfg);
342 /* Program the ULPI External VBUS bit if needed */
343 if (priv->ext_vbus) {
344 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
345 if (!priv->oc_disable) {
346 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
347 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
350 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
353 /* Set external TS Dline pulsing */
354 #ifdef CONFIG_DWC2_TS_DLINE
355 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
357 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
359 writel(usbcfg, ®s->gusbcfg);
361 /* Reset the Controller */
362 dwc_otg_core_reset(regs);
365 * This programming sequence needs to happen in FS mode before
366 * any other programming occurs
368 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
369 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
370 /* If FS mode with FS PHY */
371 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
373 /* Reset after a PHY select */
374 dwc_otg_core_reset(regs);
377 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
378 * Also do this on HNP Dev/Host mode switches (done in dev_init
381 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
382 init_fslspclksel(regs);
384 #ifdef CONFIG_DWC2_I2C_ENABLE
385 /* Program GUSBCFG.OtgUtmifsSel to I2C */
386 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
388 /* Program GI2CCTL.I2CEn */
389 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
390 DWC2_GI2CCTL_I2CDEVADDR_MASK,
391 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
392 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
396 /* High speed PHY. */
399 * HS PHY parameters. These parameters are preserved during
400 * soft reset so only program the first time. Do a soft reset
401 * immediately after setting phyif.
403 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
404 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
406 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
407 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
408 usbcfg |= DWC2_GUSBCFG_DDRSEL;
410 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
412 } else { /* UTMI+ interface */
413 #if (CONFIG_DWC2_UTMI_WIDTH == 16)
414 usbcfg |= DWC2_GUSBCFG_PHYIF;
418 writel(usbcfg, ®s->gusbcfg);
420 /* Reset after setting the PHY parameters */
421 dwc_otg_core_reset(regs);
424 usbcfg = readl(®s->gusbcfg);
425 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
426 #ifdef CONFIG_DWC2_ULPI_FS_LS
427 uint32_t hwcfg2 = readl(®s->ghwcfg2);
428 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
429 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
430 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
431 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
432 if (hval == 2 && fval == 1) {
433 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
434 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
437 if (priv->hnp_srp_disable)
438 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
440 writel(usbcfg, ®s->gusbcfg);
442 /* Program the GAHBCFG Register. */
443 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
444 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
446 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
447 while (brst_sz > 1) {
448 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
449 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
453 #ifdef CONFIG_DWC2_DMA_ENABLE
454 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
458 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
459 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
460 #ifdef CONFIG_DWC2_DMA_ENABLE
461 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
466 writel(ahbcfg, ®s->gahbcfg);
468 /* Program the capabilities in GUSBCFG Register */
471 if (!priv->hnp_srp_disable)
472 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
473 #ifdef CONFIG_DWC2_IC_USB_CAP
474 usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
477 setbits_le32(®s->gusbcfg, usbcfg);
481 * Prepares a host channel for transferring packets to/from a specific
482 * endpoint. The HCCHARn register is set up with the characteristics specified
483 * in _hc. Host channel interrupts that may need to be serviced while this
484 * transfer is in progress are enabled.
486 * @param regs Programming view of DWC_otg controller
487 * @param hc Information needed to initialize the host channel
489 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
490 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
491 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
493 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
494 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
495 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
496 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
497 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
498 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
500 if (dev->speed == USB_SPEED_LOW)
501 hcchar |= DWC2_HCCHAR_LSPDDEV;
504 * Program the HCCHARn register with the endpoint characteristics
505 * for the current transfer.
507 writel(hcchar, &hc_regs->hcchar);
509 /* Program the HCSPLIT register, default to no SPLIT */
510 writel(0, &hc_regs->hcsplt);
513 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
514 uint8_t hub_devnum, uint8_t hub_port)
518 hcsplt = DWC2_HCSPLT_SPLTENA;
519 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
520 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
522 /* Program the HCSPLIT register for SPLITs */
523 writel(hcsplt, &hc_regs->hcsplt);
527 * DWC2 to USB API interface
529 /* Direction: In ; Request: Status */
530 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
531 struct usb_device *dev, void *buffer,
532 int txlen, struct devrequest *cmd)
535 uint32_t port_status = 0;
536 uint32_t port_change = 0;
540 switch (cmd->requesttype & ~USB_DIR_IN) {
542 *(uint16_t *)buffer = cpu_to_le16(1);
545 case USB_RECIP_INTERFACE:
546 case USB_RECIP_ENDPOINT:
547 *(uint16_t *)buffer = cpu_to_le16(0);
551 *(uint32_t *)buffer = cpu_to_le32(0);
554 case USB_RECIP_OTHER | USB_TYPE_CLASS:
555 hprt0 = readl(®s->hprt0);
556 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
557 port_status |= USB_PORT_STAT_CONNECTION;
558 if (hprt0 & DWC2_HPRT0_PRTENA)
559 port_status |= USB_PORT_STAT_ENABLE;
560 if (hprt0 & DWC2_HPRT0_PRTSUSP)
561 port_status |= USB_PORT_STAT_SUSPEND;
562 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
563 port_status |= USB_PORT_STAT_OVERCURRENT;
564 if (hprt0 & DWC2_HPRT0_PRTRST)
565 port_status |= USB_PORT_STAT_RESET;
566 if (hprt0 & DWC2_HPRT0_PRTPWR)
567 port_status |= USB_PORT_STAT_POWER;
569 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
570 port_status |= USB_PORT_STAT_LOW_SPEED;
571 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
572 DWC2_HPRT0_PRTSPD_HIGH)
573 port_status |= USB_PORT_STAT_HIGH_SPEED;
575 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
576 port_change |= USB_PORT_STAT_C_ENABLE;
577 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
578 port_change |= USB_PORT_STAT_C_CONNECTION;
579 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
580 port_change |= USB_PORT_STAT_C_OVERCURRENT;
582 *(uint32_t *)buffer = cpu_to_le32(port_status |
583 (port_change << 16));
587 puts("unsupported root hub command\n");
588 stat = USB_ST_STALLED;
591 dev->act_len = min(len, txlen);
597 /* Direction: In ; Request: Descriptor */
598 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
599 void *buffer, int txlen,
600 struct devrequest *cmd)
602 unsigned char data[32];
606 uint16_t wValue = cpu_to_le16(cmd->value);
607 uint16_t wLength = cpu_to_le16(cmd->length);
609 switch (cmd->requesttype & ~USB_DIR_IN) {
611 switch (wValue & 0xff00) {
612 case 0x0100: /* device descriptor */
613 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
614 memcpy(buffer, root_hub_dev_des, len);
616 case 0x0200: /* configuration descriptor */
617 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
618 memcpy(buffer, root_hub_config_des, len);
620 case 0x0300: /* string descriptors */
621 switch (wValue & 0xff) {
623 len = min3(txlen, (int)sizeof(root_hub_str_index0),
625 memcpy(buffer, root_hub_str_index0, len);
628 len = min3(txlen, (int)sizeof(root_hub_str_index1),
630 memcpy(buffer, root_hub_str_index1, len);
635 stat = USB_ST_STALLED;
640 /* Root port config, set 1 port and nothing else. */
643 data[0] = 9; /* min length; */
645 data[2] = dsc & RH_A_NDP;
651 else if (dsc & RH_A_OCPM)
654 /* corresponds to data[4-7] */
655 data[5] = (dsc & RH_A_POTPGT) >> 24;
656 data[7] = dsc & RH_B_DR;
661 data[8] = (dsc & RH_B_DR) >> 8;
666 len = min3(txlen, (int)data[0], (int)wLength);
667 memcpy(buffer, data, len);
670 puts("unsupported root hub command\n");
671 stat = USB_ST_STALLED;
674 dev->act_len = min(len, txlen);
680 /* Direction: In ; Request: Configuration */
681 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
682 void *buffer, int txlen,
683 struct devrequest *cmd)
688 switch (cmd->requesttype & ~USB_DIR_IN) {
690 *(uint8_t *)buffer = 0x01;
694 puts("unsupported root hub command\n");
695 stat = USB_ST_STALLED;
698 dev->act_len = min(len, txlen);
705 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
706 struct usb_device *dev, void *buffer,
707 int txlen, struct devrequest *cmd)
709 switch (cmd->request) {
710 case USB_REQ_GET_STATUS:
711 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
713 case USB_REQ_GET_DESCRIPTOR:
714 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
716 case USB_REQ_GET_CONFIGURATION:
717 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
720 puts("unsupported root hub command\n");
721 return USB_ST_STALLED;
726 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
727 struct usb_device *dev,
728 void *buffer, int txlen,
729 struct devrequest *cmd)
731 struct dwc2_core_regs *regs = priv->regs;
734 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
735 uint16_t wValue = cpu_to_le16(cmd->value);
737 switch (bmrtype_breq & ~USB_DIR_IN) {
738 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
739 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
742 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
744 case USB_PORT_FEAT_C_CONNECTION:
745 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET);
750 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
752 case USB_PORT_FEAT_SUSPEND:
755 case USB_PORT_FEAT_RESET:
756 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
757 DWC2_HPRT0_PRTCONNDET |
758 DWC2_HPRT0_PRTENCHNG |
759 DWC2_HPRT0_PRTOVRCURRCHNG,
762 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST);
765 case USB_PORT_FEAT_POWER:
766 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
767 DWC2_HPRT0_PRTCONNDET |
768 DWC2_HPRT0_PRTENCHNG |
769 DWC2_HPRT0_PRTOVRCURRCHNG,
773 case USB_PORT_FEAT_ENABLE:
777 case (USB_REQ_SET_ADDRESS << 8):
778 priv->root_hub_devnum = wValue;
780 case (USB_REQ_SET_CONFIGURATION << 8):
783 puts("unsupported root hub command\n");
784 stat = USB_ST_STALLED;
787 len = min(len, txlen);
795 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
796 unsigned long pipe, void *buffer, int txlen,
797 struct devrequest *cmd)
801 if (usb_pipeint(pipe)) {
802 puts("Root-Hub submit IRQ: NOT implemented\n");
806 if (cmd->requesttype & USB_DIR_IN)
807 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
809 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
816 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
819 uint32_t hcint, hctsiz;
821 ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
826 hcint = readl(&hc_regs->hcint);
827 hctsiz = readl(&hc_regs->hctsiz);
828 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
829 DWC2_HCTSIZ_XFERSIZE_OFFSET;
830 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
832 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
835 if (hcint & DWC2_HCINT_XFERCOMP)
838 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
841 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
845 static int dwc2_eptype[] = {
846 DWC2_HCCHAR_EPTYPE_ISOC,
847 DWC2_HCCHAR_EPTYPE_INTR,
848 DWC2_HCCHAR_EPTYPE_CONTROL,
849 DWC2_HCCHAR_EPTYPE_BULK,
852 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
853 u8 *pid, int in, void *buffer, int num_packets,
854 int xfer_len, int *actual_len, int odd_frame)
859 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
860 *pid, xfer_len, num_packets);
862 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
863 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
864 (*pid << DWC2_HCTSIZ_PID_OFFSET),
869 invalidate_dcache_range(
870 (uintptr_t)aligned_buffer,
871 (uintptr_t)aligned_buffer +
872 roundup(xfer_len, ARCH_DMA_MINALIGN));
874 memcpy(aligned_buffer, buffer, xfer_len);
876 (uintptr_t)aligned_buffer,
877 (uintptr_t)aligned_buffer +
878 roundup(xfer_len, ARCH_DMA_MINALIGN));
882 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
884 /* Clear old interrupt conditions for this host channel. */
885 writel(0x3fff, &hc_regs->hcint);
887 /* Set host channel enable after all other setup is complete. */
888 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
889 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
891 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
892 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
895 ret = wait_for_chhltd(hc_regs, &sub, pid);
902 invalidate_dcache_range((unsigned long)aligned_buffer,
903 (unsigned long)aligned_buffer +
904 roundup(xfer_len, ARCH_DMA_MINALIGN));
906 memcpy(buffer, aligned_buffer, xfer_len);
908 *actual_len = xfer_len;
913 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
914 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
916 struct dwc2_core_regs *regs = priv->regs;
917 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
918 struct dwc2_host_regs *host_regs = ®s->host_regs;
919 int devnum = usb_pipedevice(pipe);
920 int ep = usb_pipeendpoint(pipe);
921 int max = usb_maxpacket(dev, pipe);
922 int eptype = dwc2_eptype[usb_pipetype(pipe)];
926 int complete_split = 0;
928 uint32_t num_packets;
929 int stop_transfer = 0;
930 uint32_t max_xfer_len;
931 int ssplit_frame_num = 0;
933 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
936 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
937 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
938 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
939 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
940 max_xfer_len = DWC2_DATA_BUF_SIZE;
942 /* Make sure that max_xfer_len is a multiple of max packet size. */
943 num_packets = max_xfer_len / max;
944 max_xfer_len = num_packets * max;
946 /* Initialize channel */
947 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
950 /* Check if the target is a FS/LS device behind a HS hub */
951 if (dev->speed != USB_SPEED_HIGH) {
954 uint32_t hprt0 = readl(®s->hprt0);
955 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
956 DWC2_HPRT0_PRTSPD_HIGH) {
957 usb_find_usb2_hub_address_port(dev, &hub_addr,
959 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
971 xfer_len = len - done;
973 if (xfer_len > max_xfer_len)
974 xfer_len = max_xfer_len;
975 else if (xfer_len > max)
976 num_packets = (xfer_len + max - 1) / max;
981 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
983 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
985 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
986 int uframe_num = readl(&host_regs->hfnum);
987 if (!(uframe_num & 0x1))
991 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
992 in, (char *)buffer + done, num_packets,
993 xfer_len, &actual_len, odd_frame);
995 hcint = readl(&hc_regs->hcint);
996 if (complete_split) {
998 if (hcint & DWC2_HCINT_NYET) {
1000 int frame_num = DWC2_HFNUM_MAX_FRNUM &
1001 readl(&host_regs->hfnum);
1002 if (((frame_num - ssplit_frame_num) &
1003 DWC2_HFNUM_MAX_FRNUM) > 4)
1007 } else if (do_split) {
1008 if (hcint & DWC2_HCINT_ACK) {
1009 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
1010 readl(&host_regs->hfnum);
1019 if (actual_len < xfer_len)
1024 /* Transactions are done when when either all data is transferred or
1025 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
1028 } while (((done < len) && !stop_transfer) || complete_split);
1030 writel(0, &hc_regs->hcintmsk);
1031 writel(0xFFFFFFFF, &hc_regs->hcint);
1034 dev->act_len = done;
1039 /* U-Boot USB transmission interface */
1040 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
1041 unsigned long pipe, void *buffer, int len)
1043 int devnum = usb_pipedevice(pipe);
1044 int ep = usb_pipeendpoint(pipe);
1047 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
1052 if (usb_pipein(pipe))
1053 pid = &priv->in_data_toggle[devnum][ep];
1055 pid = &priv->out_data_toggle[devnum][ep];
1057 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1060 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1061 unsigned long pipe, void *buffer, int len,
1062 struct devrequest *setup)
1064 int devnum = usb_pipedevice(pipe);
1067 /* For CONTROL endpoint pid should start with DATA1 */
1068 int status_direction;
1070 if (devnum == priv->root_hub_devnum) {
1072 dev->speed = USB_SPEED_HIGH;
1073 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1078 pid = DWC2_HC_PID_SETUP;
1080 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1081 } while (ret == -EAGAIN);
1088 pid = DWC2_HC_PID_DATA1;
1090 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1092 act_len += dev->act_len;
1093 buffer += dev->act_len;
1094 len -= dev->act_len;
1095 } while (ret == -EAGAIN);
1098 status_direction = usb_pipeout(pipe);
1100 /* No-data CONTROL always ends with an IN transaction */
1101 status_direction = 1;
1105 pid = DWC2_HC_PID_DATA1;
1107 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1108 priv->status_buffer, 0);
1109 } while (ret == -EAGAIN);
1113 dev->act_len = act_len;
1118 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1119 unsigned long pipe, void *buffer, int len, int interval,
1122 unsigned long timeout;
1125 /* FIXME: what is interval? */
1127 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1129 if (get_timer(0) > timeout) {
1130 dev_err(dev, "Timeout poll on interrupt endpoint\n");
1133 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1134 if ((ret != -EAGAIN) || nonblock)
1139 static int dwc2_reset(struct udevice *dev)
1142 struct dwc2_priv *priv = dev_get_priv(dev);
1144 ret = reset_get_bulk(dev, &priv->resets);
1146 dev_warn(dev, "Can't get reset: %d\n", ret);
1147 /* Return 0 if error due to !CONFIG_DM_RESET and reset
1148 * DT property is not present.
1150 if (ret == -ENOENT || ret == -ENOTSUPP)
1156 /* force reset to clear all IP register */
1157 reset_assert_bulk(&priv->resets);
1158 ret = reset_deassert_bulk(&priv->resets);
1160 reset_release_bulk(&priv->resets);
1161 dev_err(dev, "Failed to reset: %d\n", ret);
1168 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1170 struct dwc2_core_regs *regs = priv->regs;
1175 ret = dwc2_reset(dev);
1179 snpsid = readl(®s->gsnpsid);
1180 dev_info(dev, "Core Release: %x.%03x\n",
1181 snpsid >> 12 & 0xf, snpsid & 0xfff);
1183 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1184 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1185 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
1190 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1196 dwc_otg_core_init(priv);
1197 dwc_otg_core_host_init(dev, regs);
1199 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1200 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1201 DWC2_HPRT0_PRTOVRCURRCHNG,
1204 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1205 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1208 for (i = 0; i < MAX_DEVICE; i++) {
1209 for (j = 0; j < MAX_ENDPOINT; j++) {
1210 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1211 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1216 * Add a 1 second delay here. This gives the host controller
1217 * a bit time before the comminucation with the USB devices
1218 * is started (the bus is scanned) and fixes the USB detection
1219 * problems with some problematic USB keys.
1221 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1224 printf("USB DWC2\n");
1229 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1231 /* Put everything in reset. */
1232 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1233 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1234 DWC2_HPRT0_PRTOVRCURRCHNG,
1238 #if !CONFIG_IS_ENABLED(DM_USB)
1239 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1240 int len, struct devrequest *setup)
1242 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1245 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1248 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1251 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1252 int len, int interval, bool nonblock)
1254 return _submit_int_msg(&local, dev, pipe, buffer, len, interval,
1258 /* U-Boot USB control interface */
1259 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1261 struct dwc2_priv *priv = &local;
1263 memset(priv, '\0', sizeof(*priv));
1264 priv->root_hub_devnum = 0;
1265 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1266 priv->aligned_buffer = aligned_buffer_addr;
1267 priv->status_buffer = status_buffer_addr;
1269 /* board-dependant init */
1270 if (board_usb_init(index, USB_INIT_HOST))
1273 return dwc2_init_common(NULL, priv);
1276 int usb_lowlevel_stop(int index)
1278 dwc2_uninit_common(local.regs);
1284 #if CONFIG_IS_ENABLED(DM_USB)
1285 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1286 unsigned long pipe, void *buffer, int length,
1287 struct devrequest *setup)
1289 struct dwc2_priv *priv = dev_get_priv(dev);
1291 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1292 dev->name, udev, udev->dev->name, udev->portnr);
1294 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1297 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1298 unsigned long pipe, void *buffer, int length)
1300 struct dwc2_priv *priv = dev_get_priv(dev);
1302 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1304 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1307 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1308 unsigned long pipe, void *buffer, int length,
1309 int interval, bool nonblock)
1311 struct dwc2_priv *priv = dev_get_priv(dev);
1313 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1315 return _submit_int_msg(priv, udev, pipe, buffer, length, interval,
1319 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1321 struct dwc2_priv *priv = dev_get_priv(dev);
1324 addr = dev_read_addr(dev);
1325 if (addr == FDT_ADDR_T_NONE)
1327 priv->regs = (struct dwc2_core_regs *)addr;
1329 priv->oc_disable = dev_read_bool(dev, "disable-over-current");
1330 priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
1335 static int dwc2_setup_phy(struct udevice *dev)
1337 struct dwc2_priv *priv = dev_get_priv(dev);
1340 ret = generic_phy_get_by_index(dev, 0, &priv->phy);
1343 return 0; /* no PHY, nothing to do */
1344 dev_err(dev, "Failed to get USB PHY: %d.\n", ret);
1348 ret = generic_phy_init(&priv->phy);
1350 dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret);
1354 ret = generic_phy_power_on(&priv->phy);
1356 dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret);
1357 generic_phy_exit(&priv->phy);
1364 static int dwc2_shutdown_phy(struct udevice *dev)
1366 struct dwc2_priv *priv = dev_get_priv(dev);
1369 /* PHY is not valid when generic_phy_get_by_index() = -ENOENT */
1370 if (!generic_phy_valid(&priv->phy))
1371 return 0; /* no PHY, nothing to do */
1373 ret = generic_phy_power_off(&priv->phy);
1375 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1379 ret = generic_phy_exit(&priv->phy);
1381 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1388 static int dwc2_clk_init(struct udevice *dev)
1390 struct dwc2_priv *priv = dev_get_priv(dev);
1393 ret = clk_get_bulk(dev, &priv->clks);
1394 if (ret == -ENOSYS || ret == -ENOENT)
1399 ret = clk_enable_bulk(&priv->clks);
1401 clk_release_bulk(&priv->clks);
1408 static int dwc2_usb_probe(struct udevice *dev)
1410 struct dwc2_priv *priv = dev_get_priv(dev);
1411 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1414 bus_priv->desc_before_addr = true;
1416 ret = dwc2_clk_init(dev);
1420 ret = dwc2_setup_phy(dev);
1424 return dwc2_init_common(dev, priv);
1427 static int dwc2_usb_remove(struct udevice *dev)
1429 struct dwc2_priv *priv = dev_get_priv(dev);
1432 ret = dwc_vbus_supply_exit(dev);
1436 ret = dwc2_shutdown_phy(dev);
1438 dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret);
1442 dwc2_uninit_common(priv->regs);
1444 reset_release_bulk(&priv->resets);
1445 clk_disable_bulk(&priv->clks);
1446 clk_release_bulk(&priv->clks);
1451 struct dm_usb_ops dwc2_usb_ops = {
1452 .control = dwc2_submit_control_msg,
1453 .bulk = dwc2_submit_bulk_msg,
1454 .interrupt = dwc2_submit_int_msg,
1457 static const struct udevice_id dwc2_usb_ids[] = {
1458 { .compatible = "brcm,bcm2835-usb" },
1459 { .compatible = "brcm,bcm2708-usb" },
1460 { .compatible = "snps,dwc2" },
1464 U_BOOT_DRIVER(usb_dwc2) = {
1467 .of_match = dwc2_usb_ids,
1468 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1469 .probe = dwc2_usb_probe,
1470 .remove = dwc2_usb_remove,
1471 .ops = &dwc2_usb_ops,
1472 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1473 .flags = DM_FLAG_ALLOC_PRIV_DMA,