drivers/usb/gadget/s3c_udc_otg_xfer_dma.c

   1 /*
   2  * drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
   3  * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
   4  *
   5  * Copyright (C) 2009 for Samsung Electronics
   6  *
   7  * BSP Support for Samsung's UDC driver
   8  * available at:
   9  * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  10  *
  11  * State machine bugfixes:
  12  * Marek Szyprowski <m.szyprowski@samsung.com>
  13  *
  14  * Ported to u-boot:
  15  * Marek Szyprowski <m.szyprowski@samsung.com>
  16  * Lukasz Majewski <l.majewski@samsumg.com>
  17  *
  18  * SPDX-License-Identifier:     GPL-2.0+
  19  */
  20
  21 static u8 clear_feature_num;
  22 int clear_feature_flag;
  23
  24 /* Bulk-Only Mass Storage Reset (class-specific request) */
  25 #define GET_MAX_LUN_REQUEST     0xFE
  26 #define BOT_RESET_REQUEST       0xFF
  27
  28 static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev)
  29 {
  30         u32 ep_ctrl;
  31
  32         flush_dcache_range((unsigned long) usb_ctrl_dma_addr,
  33                            (unsigned long) usb_ctrl_dma_addr
  34                            + DMA_BUFFER_SIZE);
  35
  36         writel(usb_ctrl_dma_addr, &reg->in_endp[EP0_CON].diepdma);
  37         writel(DIEPT_SIZ_PKT_CNT(1), &reg->in_endp[EP0_CON].dieptsiz);
  38
  39         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  40         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
  41                &reg->in_endp[EP0_CON].diepctl);
  42
  43         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  44                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  45         dev->ep0state = WAIT_FOR_IN_COMPLETE;
  46 }
  47
  48 void s3c_udc_pre_setup(void)
  49 {
  50         u32 ep_ctrl;
  51
  52         debug_cond(DEBUG_IN_EP,
  53                    "%s : Prepare Setup packets.\n", __func__);
  54
  55         invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
  56                                 (unsigned long) usb_ctrl_dma_addr
  57                                 + DMA_BUFFER_SIZE);
  58
  59         writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
  60                &reg->out_endp[EP0_CON].doeptsiz);
  61         writel(usb_ctrl_dma_addr, &reg->out_endp[EP0_CON].doepdma);
  62
  63         ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  64         writel(ep_ctrl|DEPCTL_EPENA, &reg->out_endp[EP0_CON].doepctl);
  65
  66         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  67                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  68         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  69                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  70
  71 }
  72
  73 static inline void s3c_ep0_complete_out(void)
  74 {
  75         u32 ep_ctrl;
  76
  77         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  78                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  79         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  80                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  81
  82         debug_cond(DEBUG_IN_EP,
  83                 "%s : Prepare Complete Out packet.\n", __func__);
  84
  85         invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
  86                                 (unsigned long) usb_ctrl_dma_addr
  87                                 + DMA_BUFFER_SIZE);
  88
  89         writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
  90                &reg->out_endp[EP0_CON].doeptsiz);
  91         writel(usb_ctrl_dma_addr, &reg->out_endp[EP0_CON].doepdma);
  92
  93         ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  94         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
  95                &reg->out_endp[EP0_CON].doepctl);
  96
  97         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  98                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  99         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
 100                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
 101
 102 }
 103
 104
 105 static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req)
 106 {
 107         u32 *buf, ctrl;
 108         u32 length, pktcnt;
 109         u32 ep_num = ep_index(ep);
 110
 111         buf = req->req.buf + req->req.actual;
 112
 113         length = min(req->req.length - req->req.actual, (int)ep->ep.maxpacket);
 114
 115         ep->len = length;
 116         ep->dma_buf = buf;
 117
 118         invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_num],
 119                                 (unsigned long) ep->dev->dma_buf[ep_num]
 120                                 + ROUND(ep->ep.maxpacket,
 121                                         CONFIG_SYS_CACHELINE_SIZE));
 122
 123         if (length == 0)
 124                 pktcnt = 1;
 125         else
 126                 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
 127
 128         pktcnt = 1;
 129         ctrl =  readl(&reg->out_endp[ep_num].doepctl);
 130
 131         writel(the_controller->dma_addr[ep_index(ep)+1],
 132                &reg->out_endp[ep_num].doepdma);
 133         writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
 134                &reg->out_endp[ep_num].doeptsiz);
 135         writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->out_endp[ep_num].doepctl);
 136
 137         debug_cond(DEBUG_OUT_EP != 0,
 138                    "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
 139                    "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
 140                    "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
 141                    __func__, ep_num,
 142                    readl(&reg->out_endp[ep_num].doepdma),
 143                    readl(&reg->out_endp[ep_num].doeptsiz),
 144                    readl(&reg->out_endp[ep_num].doepctl),
 145                    buf, pktcnt, length);
 146         return 0;
 147
 148 }
 149
 150 int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
 151 {
 152         u32 *buf, ctrl = 0;
 153         u32 length, pktcnt;
 154         u32 ep_num = ep_index(ep);
 155         u32 *p = the_controller->dma_buf[ep_index(ep)+1];
 156
 157         buf = req->req.buf + req->req.actual;
 158         length = req->req.length - req->req.actual;
 159
 160         if (ep_num == EP0_CON)
 161                 length = min(length, (u32)ep_maxpacket(ep));
 162
 163         ep->len = length;
 164         ep->dma_buf = buf;
 165         memcpy(p, ep->dma_buf, length);
 166
 167         flush_dcache_range((unsigned long) p ,
 168                            (unsigned long) p + DMA_BUFFER_SIZE);
 169
 170         if (length == 0)
 171                 pktcnt = 1;
 172         else
 173                 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
 174
 175         /* Flush the endpoint's Tx FIFO */
 176         writel(TX_FIFO_NUMBER(ep->fifo_num), &reg->grstctl);
 177         writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, &reg->grstctl);
 178         while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
 179                 ;
 180
 181         writel(the_controller->dma_addr[ep_index(ep)+1],
 182                &reg->in_endp[ep_num].diepdma);
 183         writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
 184                &reg->in_endp[ep_num].dieptsiz);
 185
 186         ctrl = readl(&reg->in_endp[ep_num].diepctl);
 187
 188         /* Write the FIFO number to be used for this endpoint */
 189         ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
 190         ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
 191
 192         /* Clear reserved (Next EP) bits */
 193         ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
 194
 195         writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->in_endp[ep_num].diepctl);
 196
 197         debug_cond(DEBUG_IN_EP,
 198                 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
 199                 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
 200                 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
 201                 __func__, ep_num,
 202                 readl(&reg->in_endp[ep_num].diepdma),
 203                 readl(&reg->in_endp[ep_num].dieptsiz),
 204                 readl(&reg->in_endp[ep_num].diepctl),
 205                 buf, pktcnt, length);
 206
 207         return length;
 208 }
 209
 210 static void complete_rx(struct s3c_udc *dev, u8 ep_num)
 211 {
 212         struct s3c_ep *ep = &dev->ep[ep_num];
 213         struct s3c_request *req = NULL;
 214         u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
 215         u32 *p = the_controller->dma_buf[ep_index(ep)+1];
 216
 217         if (list_empty(&ep->queue)) {
 218                 debug_cond(DEBUG_OUT_EP != 0,
 219                            "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
 220                            __func__, ep_num);
 221                 return;
 222
 223         }
 224
 225         req = list_entry(ep->queue.next, struct s3c_request, queue);
 226         ep_tsr = readl(&reg->out_endp[ep_num].doeptsiz);
 227
 228         if (ep_num == EP0_CON)
 229                 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
 230         else
 231                 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
 232
 233         xfer_size = ep->len - xfer_size;
 234
 235         invalidate_dcache_range((unsigned long) p,
 236                                 (unsigned long) p + DMA_BUFFER_SIZE);
 237
 238         memcpy(ep->dma_buf, p, ep->len);
 239
 240         req->req.actual += min(xfer_size, req->req.length - req->req.actual);
 241         is_short = (xfer_size < ep->ep.maxpacket);
 242
 243         debug_cond(DEBUG_OUT_EP != 0,
 244                    "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
 245                    "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
 246                    __func__, ep_num, req->req.actual, req->req.length,
 247                    is_short, ep_tsr, xfer_size);
 248
 249         if (is_short || req->req.actual == req->req.length) {
 250                 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
 251                         debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
 252                         s3c_udc_ep0_zlp(dev);
 253                         /* packet will be completed in complete_tx() */
 254                         dev->ep0state = WAIT_FOR_IN_COMPLETE;
 255                 } else {
 256                         done(ep, req, 0);
 257
 258                         if (!list_empty(&ep->queue)) {
 259                                 req = list_entry(ep->queue.next,
 260                                         struct s3c_request, queue);
 261                                 debug_cond(DEBUG_OUT_EP != 0,
 262                                            "%s: Next Rx request start...\n",
 263                                            __func__);
 264                                 setdma_rx(ep, req);
 265                         }
 266                 }
 267         } else
 268                 setdma_rx(ep, req);
 269 }
 270
 271 static void complete_tx(struct s3c_udc *dev, u8 ep_num)
 272 {
 273         struct s3c_ep *ep = &dev->ep[ep_num];
 274         struct s3c_request *req;
 275         u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
 276         u32 last;
 277
 278         if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
 279                 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
 280                 s3c_ep0_complete_out();
 281                 return;
 282         }
 283
 284         if (list_empty(&ep->queue)) {
 285                 debug_cond(DEBUG_IN_EP,
 286                         "%s: TX DMA done : NULL REQ on IN EP-%d\n",
 287                         __func__, ep_num);
 288                 return;
 289
 290         }
 291
 292         req = list_entry(ep->queue.next, struct s3c_request, queue);
 293
 294         ep_tsr = readl(&reg->in_endp[ep_num].dieptsiz);
 295
 296         xfer_size = ep->len;
 297         is_short = (xfer_size < ep->ep.maxpacket);
 298         req->req.actual += min(xfer_size, req->req.length - req->req.actual);
 299
 300         debug_cond(DEBUG_IN_EP,
 301                 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
 302                 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
 303                 __func__, ep_num, req->req.actual, req->req.length,
 304                 is_short, ep_tsr, xfer_size);
 305
 306         if (ep_num == 0) {
 307                 if (dev->ep0state == DATA_STATE_XMIT) {
 308                         debug_cond(DEBUG_IN_EP,
 309                                 "%s: ep_num = %d, ep0stat =="
 310                                 "DATA_STATE_XMIT\n",
 311                                 __func__, ep_num);
 312                         last = write_fifo_ep0(ep, req);
 313                         if (last)
 314                                 dev->ep0state = WAIT_FOR_COMPLETE;
 315                 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
 316                         debug_cond(DEBUG_IN_EP,
 317                                 "%s: ep_num = %d, completing request\n",
 318                                 __func__, ep_num);
 319                         done(ep, req, 0);
 320                         dev->ep0state = WAIT_FOR_SETUP;
 321                 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
 322                         debug_cond(DEBUG_IN_EP,
 323                                 "%s: ep_num = %d, completing request\n",
 324                                 __func__, ep_num);
 325                         done(ep, req, 0);
 326                         dev->ep0state = WAIT_FOR_OUT_COMPLETE;
 327                         s3c_ep0_complete_out();
 328                 } else {
 329                         debug_cond(DEBUG_IN_EP,
 330                                 "%s: ep_num = %d, invalid ep state\n",
 331                                 __func__, ep_num);
 332                 }
 333                 return;
 334         }
 335
 336         if (req->req.actual == req->req.length)
 337                 done(ep, req, 0);
 338
 339         if (!list_empty(&ep->queue)) {
 340                 req = list_entry(ep->queue.next, struct s3c_request, queue);
 341                 debug_cond(DEBUG_IN_EP,
 342                         "%s: Next Tx request start...\n", __func__);
 343                 setdma_tx(ep, req);
 344         }
 345 }
 346
 347 static inline void s3c_udc_check_tx_queue(struct s3c_udc *dev, u8 ep_num)
 348 {
 349         struct s3c_ep *ep = &dev->ep[ep_num];
 350         struct s3c_request *req;
 351
 352         debug_cond(DEBUG_IN_EP,
 353                 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
 354
 355         if (!list_empty(&ep->queue)) {
 356                 req = list_entry(ep->queue.next, struct s3c_request, queue);
 357                 debug_cond(DEBUG_IN_EP,
 358                         "%s: Next Tx request(0x%p) start...\n",
 359                         __func__, req);
 360
 361                 if (ep_is_in(ep))
 362                         setdma_tx(ep, req);
 363                 else
 364                         setdma_rx(ep, req);
 365         } else {
 366                 debug_cond(DEBUG_IN_EP,
 367                         "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
 368
 369                 return;
 370         }
 371
 372 }
 373
 374 static void process_ep_in_intr(struct s3c_udc *dev)
 375 {
 376         u32 ep_intr, ep_intr_status;
 377         u8 ep_num = 0;
 378
 379         ep_intr = readl(&reg->daint);
 380         debug_cond(DEBUG_IN_EP,
 381                 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
 382
 383         ep_intr &= DAINT_MASK;
 384
 385         while (ep_intr) {
 386                 if (ep_intr & DAINT_IN_EP_INT(1)) {
 387                         ep_intr_status = readl(&reg->in_endp[ep_num].diepint);
 388                         debug_cond(DEBUG_IN_EP,
 389                                    "\tEP%d-IN : DIEPINT = 0x%x\n",
 390                                    ep_num, ep_intr_status);
 391
 392                         /* Interrupt Clear */
 393                         writel(ep_intr_status, &reg->in_endp[ep_num].diepint);
 394
 395                         if (ep_intr_status & TRANSFER_DONE) {
 396                                 complete_tx(dev, ep_num);
 397
 398                                 if (ep_num == 0) {
 399                                         if (dev->ep0state ==
 400                                             WAIT_FOR_IN_COMPLETE)
 401                                                 dev->ep0state = WAIT_FOR_SETUP;
 402
 403                                         if (dev->ep0state == WAIT_FOR_SETUP)
 404                                                 s3c_udc_pre_setup();
 405
 406                                         /* continue transfer after
 407                                            set_clear_halt for DMA mode */
 408                                         if (clear_feature_flag == 1) {
 409                                                 s3c_udc_check_tx_queue(dev,
 410                                                         clear_feature_num);
 411                                                 clear_feature_flag = 0;
 412                                         }
 413                                 }
 414                         }
 415                 }
 416                 ep_num++;
 417                 ep_intr >>= 1;
 418         }
 419 }
 420
 421 static void process_ep_out_intr(struct s3c_udc *dev)
 422 {
 423         u32 ep_intr, ep_intr_status;
 424         u8 ep_num = 0;
 425
 426         ep_intr = readl(&reg->daint);
 427         debug_cond(DEBUG_OUT_EP != 0,
 428                    "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
 429                    __func__, ep_intr);
 430
 431         ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
 432
 433         while (ep_intr) {
 434                 if (ep_intr & 0x1) {
 435                         ep_intr_status = readl(&reg->out_endp[ep_num].doepint);
 436                         debug_cond(DEBUG_OUT_EP != 0,
 437                                    "\tEP%d-OUT : DOEPINT = 0x%x\n",
 438                                    ep_num, ep_intr_status);
 439
 440                         /* Interrupt Clear */
 441                         writel(ep_intr_status, &reg->out_endp[ep_num].doepint);
 442
 443                         if (ep_num == 0) {
 444                                 if (ep_intr_status & TRANSFER_DONE) {
 445                                         if (dev->ep0state !=
 446                                             WAIT_FOR_OUT_COMPLETE)
 447                                                 complete_rx(dev, ep_num);
 448                                         else {
 449                                                 dev->ep0state = WAIT_FOR_SETUP;
 450                                                 s3c_udc_pre_setup();
 451                                         }
 452                                 }
 453
 454                                 if (ep_intr_status &
 455                                     CTRL_OUT_EP_SETUP_PHASE_DONE) {
 456                                         debug_cond(DEBUG_OUT_EP != 0,
 457                                                    "SETUP packet arrived\n");
 458                                         s3c_handle_ep0(dev);
 459                                 }
 460                         } else {
 461                                 if (ep_intr_status & TRANSFER_DONE)
 462                                         complete_rx(dev, ep_num);
 463                         }
 464                 }
 465                 ep_num++;
 466                 ep_intr >>= 1;
 467         }
 468 }
 469
 470 /*
 471  *      usb client interrupt handler.
 472  */
 473 static int s3c_udc_irq(int irq, void *_dev)
 474 {
 475         struct s3c_udc *dev = _dev;
 476         u32 intr_status;
 477         u32 usb_status, gintmsk;
 478         unsigned long flags;
 479
 480         spin_lock_irqsave(&dev->lock, flags);
 481
 482         intr_status = readl(&reg->gintsts);
 483         gintmsk = readl(&reg->gintmsk);
 484
 485         debug_cond(DEBUG_ISR,
 486                   "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
 487                   "DAINT : 0x%x, DAINTMSK : 0x%x\n",
 488                   __func__, intr_status, state_names[dev->ep0state], gintmsk,
 489                   readl(&reg->daint), readl(&reg->daintmsk));
 490
 491         if (!intr_status) {
 492                 spin_unlock_irqrestore(&dev->lock, flags);
 493                 return IRQ_HANDLED;
 494         }
 495
 496         if (intr_status & INT_ENUMDONE) {
 497                 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
 498
 499                 writel(INT_ENUMDONE, &reg->gintsts);
 500                 usb_status = (readl(&reg->dsts) & 0x6);
 501
 502                 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
 503                         debug_cond(DEBUG_ISR,
 504                                    "\t\tFull Speed Detection\n");
 505                         set_max_pktsize(dev, USB_SPEED_FULL);
 506
 507                 } else {
 508                         debug_cond(DEBUG_ISR,
 509                                 "\t\tHigh Speed Detection : 0x%x\n",
 510                                 usb_status);
 511                         set_max_pktsize(dev, USB_SPEED_HIGH);
 512                 }
 513         }
 514
 515         if (intr_status & INT_EARLY_SUSPEND) {
 516                 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
 517                 writel(INT_EARLY_SUSPEND, &reg->gintsts);
 518         }
 519
 520         if (intr_status & INT_SUSPEND) {
 521                 usb_status = readl(&reg->dsts);
 522                 debug_cond(DEBUG_ISR,
 523                         "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
 524                 writel(INT_SUSPEND, &reg->gintsts);
 525
 526                 if (dev->gadget.speed != USB_SPEED_UNKNOWN
 527                     && dev->driver) {
 528                         if (dev->driver->suspend)
 529                                 dev->driver->suspend(&dev->gadget);
 530
 531                         /* HACK to let gadget detect disconnected state */
 532                         if (dev->driver->disconnect) {
 533                                 spin_unlock_irqrestore(&dev->lock, flags);
 534                                 dev->driver->disconnect(&dev->gadget);
 535                                 spin_lock_irqsave(&dev->lock, flags);
 536                         }
 537                 }
 538         }
 539
 540         if (intr_status & INT_RESUME) {
 541                 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
 542                 writel(INT_RESUME, &reg->gintsts);
 543
 544                 if (dev->gadget.speed != USB_SPEED_UNKNOWN
 545                     && dev->driver
 546                     && dev->driver->resume) {
 547
 548                         dev->driver->resume(&dev->gadget);
 549                 }
 550         }
 551
 552         if (intr_status & INT_RESET) {
 553                 usb_status = readl(&reg->gotgctl);
 554                 debug_cond(DEBUG_ISR,
 555                         "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
 556                 writel(INT_RESET, &reg->gintsts);
 557
 558                 if ((usb_status & 0xc0000) == (0x3 << 18)) {
 559                         if (reset_available) {
 560                                 debug_cond(DEBUG_ISR,
 561                                         "\t\tOTG core got reset (%d)!!\n",
 562                                         reset_available);
 563                                 reconfig_usbd();
 564                                 dev->ep0state = WAIT_FOR_SETUP;
 565                                 reset_available = 0;
 566                                 s3c_udc_pre_setup();
 567                         } else
 568                                 reset_available = 1;
 569
 570                 } else {
 571                         reset_available = 1;
 572                         debug_cond(DEBUG_ISR,
 573                                    "\t\tRESET handling skipped\n");
 574                 }
 575         }
 576
 577         if (intr_status & INT_IN_EP)
 578                 process_ep_in_intr(dev);
 579
 580         if (intr_status & INT_OUT_EP)
 581                 process_ep_out_intr(dev);
 582
 583         spin_unlock_irqrestore(&dev->lock, flags);
 584
 585         return IRQ_HANDLED;
 586 }
 587
 588 /** Queue one request
 589  *  Kickstart transfer if needed
 590  */
 591 static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req,
 592                          gfp_t gfp_flags)
 593 {
 594         struct s3c_request *req;
 595         struct s3c_ep *ep;
 596         struct s3c_udc *dev;
 597         unsigned long flags;
 598         u32 ep_num, gintsts;
 599
 600         req = container_of(_req, struct s3c_request, req);
 601         if (unlikely(!_req || !_req->complete || !_req->buf
 602                      || !list_empty(&req->queue))) {
 603
 604                 debug("%s: bad params\n", __func__);
 605                 return -EINVAL;
 606         }
 607
 608         ep = container_of(_ep, struct s3c_ep, ep);
 609
 610         if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
 611
 612                 debug("%s: bad ep: %s, %d, %p\n", __func__,
 613                       ep->ep.name, !ep->desc, _ep);
 614                 return -EINVAL;
 615         }
 616
 617         ep_num = ep_index(ep);
 618         dev = ep->dev;
 619         if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 620
 621                 debug("%s: bogus device state %p\n", __func__, dev->driver);
 622                 return -ESHUTDOWN;
 623         }
 624
 625         spin_lock_irqsave(&dev->lock, flags);
 626
 627         _req->status = -EINPROGRESS;
 628         _req->actual = 0;
 629
 630         /* kickstart this i/o queue? */
 631         debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
 632                 "Q empty = %d, stopped = %d\n",
 633                 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
 634                 _req, _req->length, _req->buf,
 635                 list_empty(&ep->queue), ep->stopped);
 636
 637 #ifdef DEBUG
 638         {
 639                 int i, len = _req->length;
 640
 641                 printf("pkt = ");
 642                 if (len > 64)
 643                         len = 64;
 644                 for (i = 0; i < len; i++) {
 645                         printf("%02x", ((u8 *)_req->buf)[i]);
 646                         if ((i & 7) == 7)
 647                                 printf(" ");
 648                 }
 649                 printf("\n");
 650         }
 651 #endif
 652
 653         if (list_empty(&ep->queue) && !ep->stopped) {
 654
 655                 if (ep_num == 0) {
 656                         /* EP0 */
 657                         list_add_tail(&req->queue, &ep->queue);
 658                         s3c_ep0_kick(dev, ep);
 659                         req = 0;
 660
 661                 } else if (ep_is_in(ep)) {
 662                         gintsts = readl(&reg->gintsts);
 663                         debug_cond(DEBUG_IN_EP,
 664                                    "%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n",
 665                                    __func__, gintsts);
 666
 667                         setdma_tx(ep, req);
 668                 } else {
 669                         gintsts = readl(&reg->gintsts);
 670                         debug_cond(DEBUG_OUT_EP != 0,
 671                                    "%s:ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n",
 672                                    __func__, gintsts);
 673
 674                         setdma_rx(ep, req);
 675                 }
 676         }
 677
 678         /* pio or dma irq handler advances the queue. */
 679         if (likely(req != 0))
 680                 list_add_tail(&req->queue, &ep->queue);
 681
 682         spin_unlock_irqrestore(&dev->lock, flags);
 683
 684         return 0;
 685 }
 686
 687 /****************************************************************/
 688 /* End Point 0 related functions                                */
 689 /****************************************************************/
 690
 691 /* return:  0 = still running, 1 = completed, negative = errno */
 692 static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
 693 {
 694         u32 max;
 695         unsigned count;
 696         int is_last;
 697
 698         max = ep_maxpacket(ep);
 699
 700         debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
 701
 702         count = setdma_tx(ep, req);
 703
 704         /* last packet is usually short (or a zlp) */
 705         if (likely(count != max))
 706                 is_last = 1;
 707         else {
 708                 if (likely(req->req.length != req->req.actual + count)
 709                     || req->req.zero)
 710                         is_last = 0;
 711                 else
 712                         is_last = 1;
 713         }
 714
 715         debug_cond(DEBUG_EP0 != 0,
 716                    "%s: wrote %s %d bytes%s %d left %p\n", __func__,
 717                    ep->ep.name, count,
 718                    is_last ? "/L" : "",
 719                    req->req.length - req->req.actual - count, req);
 720
 721         /* requests complete when all IN data is in the FIFO */
 722         if (is_last) {
 723                 ep->dev->ep0state = WAIT_FOR_SETUP;
 724                 return 1;
 725         }
 726
 727         return 0;
 728 }
 729
 730 int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max)
 731 {
 732         u32 bytes;
 733
 734         bytes = sizeof(struct usb_ctrlrequest);
 735
 736         invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)],
 737                                 (unsigned long) ep->dev->dma_buf[ep_index(ep)]
 738                                 + DMA_BUFFER_SIZE);
 739
 740         debug_cond(DEBUG_EP0 != 0,
 741                    "%s: bytes=%d, ep_index=%d %p\n", __func__,
 742                    bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]);
 743
 744         return bytes;
 745 }
 746
 747 /**
 748  * udc_set_address - set the USB address for this device
 749  * @address:
 750  *
 751  * Called from control endpoint function
 752  * after it decodes a set address setup packet.
 753  */
 754 static void udc_set_address(struct s3c_udc *dev, unsigned char address)
 755 {
 756         u32 ctrl = readl(&reg->dcfg);
 757         writel(DEVICE_ADDRESS(address) | ctrl, &reg->dcfg);
 758
 759         s3c_udc_ep0_zlp(dev);
 760
 761         debug_cond(DEBUG_EP0 != 0,
 762                    "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
 763                    __func__, address, readl(&reg->dcfg));
 764
 765         dev->usb_address = address;
 766 }
 767
 768 static inline void s3c_udc_ep0_set_stall(struct s3c_ep *ep)
 769 {
 770         struct s3c_udc *dev;
 771         u32             ep_ctrl = 0;
 772
 773         dev = ep->dev;
 774         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
 775
 776         /* set the disable and stall bits */
 777         if (ep_ctrl & DEPCTL_EPENA)
 778                 ep_ctrl |= DEPCTL_EPDIS;
 779
 780         ep_ctrl |= DEPCTL_STALL;
 781
 782         writel(ep_ctrl, &reg->in_endp[EP0_CON].diepctl);
 783
 784         debug_cond(DEBUG_EP0 != 0,
 785                    "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
 786                    __func__, ep_index(ep), &reg->in_endp[EP0_CON].diepctl);
 787         /*
 788          * The application can only set this bit, and the core clears it,
 789          * when a SETUP token is received for this endpoint
 790          */
 791         dev->ep0state = WAIT_FOR_SETUP;
 792
 793         s3c_udc_pre_setup();
 794 }
 795
 796 static void s3c_ep0_read(struct s3c_udc *dev)
 797 {
 798         struct s3c_request *req;
 799         struct s3c_ep *ep = &dev->ep[0];
 800
 801         if (!list_empty(&ep->queue)) {
 802                 req = list_entry(ep->queue.next, struct s3c_request, queue);
 803
 804         } else {
 805                 debug("%s: ---> BUG\n", __func__);
 806                 BUG();
 807                 return;
 808         }
 809
 810         debug_cond(DEBUG_EP0 != 0,
 811                    "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
 812                    __func__, req, req->req.length, req->req.actual);
 813
 814         if (req->req.length == 0) {
 815                 /* zlp for Set_configuration, Set_interface,
 816                  * or Bulk-Only mass storge reset */
 817
 818                 ep->len = 0;
 819                 s3c_udc_ep0_zlp(dev);
 820
 821                 debug_cond(DEBUG_EP0 != 0,
 822                            "%s: req.length = 0, bRequest = %d\n",
 823                            __func__, usb_ctrl->bRequest);
 824                 return;
 825         }
 826
 827         setdma_rx(ep, req);
 828 }
 829
 830 /*
 831  * DATA_STATE_XMIT
 832  */
 833 static int s3c_ep0_write(struct s3c_udc *dev)
 834 {
 835         struct s3c_request *req;
 836         struct s3c_ep *ep = &dev->ep[0];
 837         int ret, need_zlp = 0;
 838
 839         if (list_empty(&ep->queue))
 840                 req = 0;
 841         else
 842                 req = list_entry(ep->queue.next, struct s3c_request, queue);
 843
 844         if (!req) {
 845                 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
 846                 return 0;
 847         }
 848
 849         debug_cond(DEBUG_EP0 != 0,
 850                    "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
 851                    __func__, req, req->req.length, req->req.actual);
 852
 853         if (req->req.length - req->req.actual == ep0_fifo_size) {
 854                 /* Next write will end with the packet size, */
 855                 /* so we need Zero-length-packet */
 856                 need_zlp = 1;
 857         }
 858
 859         ret = write_fifo_ep0(ep, req);
 860
 861         if ((ret == 1) && !need_zlp) {
 862                 /* Last packet */
 863                 dev->ep0state = WAIT_FOR_COMPLETE;
 864                 debug_cond(DEBUG_EP0 != 0,
 865                            "%s: finished, waiting for status\n", __func__);
 866
 867         } else {
 868                 dev->ep0state = DATA_STATE_XMIT;
 869                 debug_cond(DEBUG_EP0 != 0,
 870                            "%s: not finished\n", __func__);
 871         }
 872
 873         return 1;
 874 }
 875
 876 u16     g_status;
 877
 878 int s3c_udc_get_status(struct s3c_udc *dev,
 879                 struct usb_ctrlrequest *crq)
 880 {
 881         u8 ep_num = crq->wIndex & 0x7F;
 882         u32 ep_ctrl;
 883         u32 *p = the_controller->dma_buf[1];
 884
 885         debug_cond(DEBUG_SETUP != 0,
 886                    "%s: *** USB_REQ_GET_STATUS\n", __func__);
 887         printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
 888         switch (crq->bRequestType & USB_RECIP_MASK) {
 889         case USB_RECIP_INTERFACE:
 890                 g_status = 0;
 891                 debug_cond(DEBUG_SETUP != 0,
 892                            "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
 893                            g_status);
 894                 break;
 895
 896         case USB_RECIP_DEVICE:
 897                 g_status = 0x1; /* Self powered */
 898                 debug_cond(DEBUG_SETUP != 0,
 899                            "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
 900                            g_status);
 901                 break;
 902
 903         case USB_RECIP_ENDPOINT:
 904                 if (crq->wLength > 2) {
 905                         debug_cond(DEBUG_SETUP != 0,
 906                                    "\tGET_STATUS:Not support EP or wLength\n");
 907                         return 1;
 908                 }
 909
 910                 g_status = dev->ep[ep_num].stopped;
 911                 debug_cond(DEBUG_SETUP != 0,
 912                            "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
 913                            g_status);
 914
 915                 break;
 916
 917         default:
 918                 return 1;
 919         }
 920
 921         memcpy(p, &g_status, sizeof(g_status));
 922
 923         flush_dcache_range((unsigned long) p,
 924                            (unsigned long) p + DMA_BUFFER_SIZE);
 925
 926         writel(the_controller->dma_addr[1], &reg->in_endp[EP0_CON].diepdma);
 927         writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
 928                &reg->in_endp[EP0_CON].dieptsiz);
 929
 930         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
 931         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
 932                &reg->in_endp[EP0_CON].diepctl);
 933         dev->ep0state = WAIT_FOR_NULL_COMPLETE;
 934
 935         return 0;
 936 }
 937
 938 static void s3c_udc_set_nak(struct s3c_ep *ep)
 939 {
 940         u8              ep_num;
 941         u32             ep_ctrl = 0;
 942
 943         ep_num = ep_index(ep);
 944         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
 945
 946         if (ep_is_in(ep)) {
 947                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
 948                 ep_ctrl |= DEPCTL_SNAK;
 949                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
 950                 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
 951                         __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
 952         } else {
 953                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
 954                 ep_ctrl |= DEPCTL_SNAK;
 955                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
 956                 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
 957                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
 958         }
 959
 960         return;
 961 }
 962
 963
 964 void s3c_udc_ep_set_stall(struct s3c_ep *ep)
 965 {
 966         u8              ep_num;
 967         u32             ep_ctrl = 0;
 968
 969         ep_num = ep_index(ep);
 970         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
 971
 972         if (ep_is_in(ep)) {
 973                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
 974
 975                 /* set the disable and stall bits */
 976                 if (ep_ctrl & DEPCTL_EPENA)
 977                         ep_ctrl |= DEPCTL_EPDIS;
 978
 979                 ep_ctrl |= DEPCTL_STALL;
 980
 981                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
 982                 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
 983                       __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
 984
 985         } else {
 986                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
 987
 988                 /* set the stall bit */
 989                 ep_ctrl |= DEPCTL_STALL;
 990
 991                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
 992                 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
 993                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
 994         }
 995
 996         return;
 997 }
 998
 999 void s3c_udc_ep_clear_stall(struct s3c_ep *ep)
1000 {
1001         u8              ep_num;
1002         u32             ep_ctrl = 0;
1003
1004         ep_num = ep_index(ep);
1005         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
1006
1007         if (ep_is_in(ep)) {
1008                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
1009
1010                 /* clear stall bit */
1011                 ep_ctrl &= ~DEPCTL_STALL;
1012
1013                 /*
1014                  * USB Spec 9.4.5: For endpoints using data toggle, regardless
1015                  * of whether an endpoint has the Halt feature set, a
1016                  * ClearFeature(ENDPOINT_HALT) request always results in the
1017                  * data toggle being reinitialized to DATA0.
1018                  */
1019                 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1020                     || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1021                         ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1022                 }
1023
1024                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
1025                 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1026                         __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
1027
1028         } else {
1029                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
1030
1031                 /* clear stall bit */
1032                 ep_ctrl &= ~DEPCTL_STALL;
1033
1034                 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1035                     || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1036                         ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1037                 }
1038
1039                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1040                 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1041                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
1042         }
1043
1044         return;
1045 }
1046
1047 static int s3c_udc_set_halt(struct usb_ep *_ep, int value)
1048 {
1049         struct s3c_ep   *ep;
1050         struct s3c_udc  *dev;
1051         unsigned long   flags;
1052         u8              ep_num;
1053
1054         ep = container_of(_ep, struct s3c_ep, ep);
1055         ep_num = ep_index(ep);
1056
1057         if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1058                      ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1059                 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1060                 return -EINVAL;
1061         }
1062
1063         /* Attempt to halt IN ep will fail if any transfer requests
1064          * are still queue */
1065         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1066                 debug("%s: %s queue not empty, req = %p\n",
1067                         __func__, ep->ep.name,
1068                         list_entry(ep->queue.next, struct s3c_request, queue));
1069
1070                 return -EAGAIN;
1071         }
1072
1073         dev = ep->dev;
1074         debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1075
1076         spin_lock_irqsave(&dev->lock, flags);
1077
1078         if (value == 0) {
1079                 ep->stopped = 0;
1080                 s3c_udc_ep_clear_stall(ep);
1081         } else {
1082                 if (ep_num == 0)
1083                         dev->ep0state = WAIT_FOR_SETUP;
1084
1085                 ep->stopped = 1;
1086                 s3c_udc_ep_set_stall(ep);
1087         }
1088
1089         spin_unlock_irqrestore(&dev->lock, flags);
1090
1091         return 0;
1092 }
1093
1094 void s3c_udc_ep_activate(struct s3c_ep *ep)
1095 {
1096         u8 ep_num;
1097         u32 ep_ctrl = 0, daintmsk = 0;
1098
1099         ep_num = ep_index(ep);
1100
1101         /* Read DEPCTLn register */
1102         if (ep_is_in(ep)) {
1103                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
1104                 daintmsk = 1 << ep_num;
1105         } else {
1106                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
1107                 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1108         }
1109
1110         debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1111                 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1112
1113         /* If the EP is already active don't change the EP Control
1114          * register. */
1115         if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1116                 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1117                         (ep->bmAttributes << DEPCTL_TYPE_BIT);
1118                 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1119                         (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1120                 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1121
1122                 if (ep_is_in(ep)) {
1123                         writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
1124                         debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1125                               __func__, ep_num, ep_num,
1126                               readl(&reg->in_endp[ep_num].diepctl));
1127                 } else {
1128                         writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1129                         debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1130                               __func__, ep_num, ep_num,
1131                               readl(&reg->out_endp[ep_num].doepctl));
1132                 }
1133         }
1134
1135         /* Unmask EP Interrtupt */
1136         writel(readl(&reg->daintmsk)|daintmsk, &reg->daintmsk);
1137         debug("%s: DAINTMSK = 0x%x\n", __func__, readl(&reg->daintmsk));
1138
1139 }
1140
1141 static int s3c_udc_clear_feature(struct usb_ep *_ep)
1142 {
1143         struct s3c_udc  *dev;
1144         struct s3c_ep   *ep;
1145         u8              ep_num;
1146
1147         ep = container_of(_ep, struct s3c_ep, ep);
1148         ep_num = ep_index(ep);
1149
1150         dev = ep->dev;
1151         debug_cond(DEBUG_SETUP != 0,
1152                    "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1153                    __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1154
1155         if (usb_ctrl->wLength != 0) {
1156                 debug_cond(DEBUG_SETUP != 0,
1157                            "\tCLEAR_FEATURE: wLength is not zero.....\n");
1158                 return 1;
1159         }
1160
1161         switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1162         case USB_RECIP_DEVICE:
1163                 switch (usb_ctrl->wValue) {
1164                 case USB_DEVICE_REMOTE_WAKEUP:
1165                         debug_cond(DEBUG_SETUP != 0,
1166                                    "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1167                         break;
1168
1169                 case USB_DEVICE_TEST_MODE:
1170                         debug_cond(DEBUG_SETUP != 0,
1171                                    "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1172                         /** @todo Add CLEAR_FEATURE for TEST modes. */
1173                         break;
1174                 }
1175
1176                 s3c_udc_ep0_zlp(dev);
1177                 break;
1178
1179         case USB_RECIP_ENDPOINT:
1180                 debug_cond(DEBUG_SETUP != 0,
1181                            "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1182                            usb_ctrl->wValue);
1183
1184                 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1185                         if (ep_num == 0) {
1186                                 s3c_udc_ep0_set_stall(ep);
1187                                 return 0;
1188                         }
1189
1190                         s3c_udc_ep0_zlp(dev);
1191
1192                         s3c_udc_ep_clear_stall(ep);
1193                         s3c_udc_ep_activate(ep);
1194                         ep->stopped = 0;
1195
1196                         clear_feature_num = ep_num;
1197                         clear_feature_flag = 1;
1198                 }
1199                 break;
1200         }
1201
1202         return 0;
1203 }
1204
1205 static int s3c_udc_set_feature(struct usb_ep *_ep)
1206 {
1207         struct s3c_udc  *dev;
1208         struct s3c_ep   *ep;
1209         u8              ep_num;
1210
1211         ep = container_of(_ep, struct s3c_ep, ep);
1212         ep_num = ep_index(ep);
1213         dev = ep->dev;
1214
1215         debug_cond(DEBUG_SETUP != 0,
1216                    "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1217                     __func__, ep_num);
1218
1219         if (usb_ctrl->wLength != 0) {
1220                 debug_cond(DEBUG_SETUP != 0,
1221                            "\tSET_FEATURE: wLength is not zero.....\n");
1222                 return 1;
1223         }
1224
1225         switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1226         case USB_RECIP_DEVICE:
1227                 switch (usb_ctrl->wValue) {
1228                 case USB_DEVICE_REMOTE_WAKEUP:
1229                         debug_cond(DEBUG_SETUP != 0,
1230                                    "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1231                         break;
1232                 case USB_DEVICE_B_HNP_ENABLE:
1233                         debug_cond(DEBUG_SETUP != 0,
1234                                    "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1235                         break;
1236
1237                 case USB_DEVICE_A_HNP_SUPPORT:
1238                         /* RH port supports HNP */
1239                         debug_cond(DEBUG_SETUP != 0,
1240                                    "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1241                         break;
1242
1243                 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1244                         /* other RH port does */
1245                         debug_cond(DEBUG_SETUP != 0,
1246                                    "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1247                         break;
1248                 }
1249
1250                 s3c_udc_ep0_zlp(dev);
1251                 return 0;
1252
1253         case USB_RECIP_INTERFACE:
1254                 debug_cond(DEBUG_SETUP != 0,
1255                            "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1256                 break;
1257
1258         case USB_RECIP_ENDPOINT:
1259                 debug_cond(DEBUG_SETUP != 0,
1260                            "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1261                 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1262                         if (ep_num == 0) {
1263                                 s3c_udc_ep0_set_stall(ep);
1264                                 return 0;
1265                         }
1266                         ep->stopped = 1;
1267                         s3c_udc_ep_set_stall(ep);
1268                 }
1269
1270                 s3c_udc_ep0_zlp(dev);
1271                 return 0;
1272         }
1273
1274         return 1;
1275 }
1276
1277 /*
1278  * WAIT_FOR_SETUP (OUT_PKT_RDY)
1279  */
1280 void s3c_ep0_setup(struct s3c_udc *dev)
1281 {
1282         struct s3c_ep *ep = &dev->ep[0];
1283         int i;
1284         u8 ep_num;
1285
1286         /* Nuke all previous transfers */
1287         nuke(ep, -EPROTO);
1288
1289         /* read control req from fifo (8 bytes) */
1290         s3c_fifo_read(ep, (u32 *)usb_ctrl, 8);
1291
1292         debug_cond(DEBUG_SETUP != 0,
1293                    "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1294                    "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1295                    __func__, usb_ctrl->bRequestType,
1296                    (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1297                    usb_ctrl->bRequest,
1298                    usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1299
1300 #ifdef DEBUG
1301         {
1302                 int i, len = sizeof(*usb_ctrl);
1303                 char *p = (char *)usb_ctrl;
1304
1305                 printf("pkt = ");
1306                 for (i = 0; i < len; i++) {
1307                         printf("%02x", ((u8 *)p)[i]);
1308                         if ((i & 7) == 7)
1309                                 printf(" ");
1310                 }
1311                 printf("\n");
1312         }
1313 #endif
1314
1315         if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1316             usb_ctrl->wLength != 1) {
1317                 debug_cond(DEBUG_SETUP != 0,
1318                            "\t%s:GET_MAX_LUN_REQUEST:invalid",
1319                            __func__);
1320                 debug_cond(DEBUG_SETUP != 0,
1321                            "wLength = %d, setup returned\n",
1322                            usb_ctrl->wLength);
1323
1324                 s3c_udc_ep0_set_stall(ep);
1325                 dev->ep0state = WAIT_FOR_SETUP;
1326
1327                 return;
1328         } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1329                  usb_ctrl->wLength != 0) {
1330                 /* Bulk-Only *mass storge reset of class-specific request */
1331                 debug_cond(DEBUG_SETUP != 0,
1332                            "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1333                            __func__, usb_ctrl->wLength);
1334
1335                 s3c_udc_ep0_set_stall(ep);
1336                 dev->ep0state = WAIT_FOR_SETUP;
1337
1338                 return;
1339         }
1340
1341         /* Set direction of EP0 */
1342         if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1343                 ep->bEndpointAddress |= USB_DIR_IN;
1344         } else {
1345                 ep->bEndpointAddress &= ~USB_DIR_IN;
1346         }
1347         /* cope with automagic for some standard requests. */
1348         dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1349                 == USB_TYPE_STANDARD;
1350
1351         dev->req_pending = 1;
1352
1353         /* Handle some SETUP packets ourselves */
1354         if (dev->req_std) {
1355                 switch (usb_ctrl->bRequest) {
1356                 case USB_REQ_SET_ADDRESS:
1357                 debug_cond(DEBUG_SETUP != 0,
1358                            "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1359                            __func__, usb_ctrl->wValue);
1360                         if (usb_ctrl->bRequestType
1361                                 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1362                                 break;
1363
1364                         udc_set_address(dev, usb_ctrl->wValue);
1365                         return;
1366
1367                 case USB_REQ_SET_CONFIGURATION:
1368                         debug_cond(DEBUG_SETUP != 0,
1369                                    "=====================================\n");
1370                         debug_cond(DEBUG_SETUP != 0,
1371                                    "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1372                                    __func__, usb_ctrl->wValue);
1373
1374                         if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1375                                 reset_available = 1;
1376
1377                         break;
1378
1379                 case USB_REQ_GET_DESCRIPTOR:
1380                         debug_cond(DEBUG_SETUP != 0,
1381                                    "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1382                                    __func__);
1383                         break;
1384
1385                 case USB_REQ_SET_INTERFACE:
1386                         debug_cond(DEBUG_SETUP != 0,
1387                                    "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1388                                    __func__, usb_ctrl->wValue);
1389
1390                         if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1391                                 reset_available = 1;
1392
1393                         break;
1394
1395                 case USB_REQ_GET_CONFIGURATION:
1396                         debug_cond(DEBUG_SETUP != 0,
1397                                    "%s: *** USB_REQ_GET_CONFIGURATION\n",
1398                                    __func__);
1399                         break;
1400
1401                 case USB_REQ_GET_STATUS:
1402                         if (!s3c_udc_get_status(dev, usb_ctrl))
1403                                 return;
1404
1405                         break;
1406
1407                 case USB_REQ_CLEAR_FEATURE:
1408                         ep_num = usb_ctrl->wIndex & 0x7f;
1409
1410                         if (!s3c_udc_clear_feature(&dev->ep[ep_num].ep))
1411                                 return;
1412
1413                         break;
1414
1415                 case USB_REQ_SET_FEATURE:
1416                         ep_num = usb_ctrl->wIndex & 0x7f;
1417
1418                         if (!s3c_udc_set_feature(&dev->ep[ep_num].ep))
1419                                 return;
1420
1421                         break;
1422
1423                 default:
1424                         debug_cond(DEBUG_SETUP != 0,
1425                                    "%s: *** Default of usb_ctrl->bRequest=0x%x"
1426                                    "happened.\n", __func__, usb_ctrl->bRequest);
1427                         break;
1428                 }
1429         }
1430
1431
1432         if (likely(dev->driver)) {
1433                 /* device-2-host (IN) or no data setup command,
1434                  * process immediately */
1435                 debug_cond(DEBUG_SETUP != 0,
1436                            "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1437                             __func__);
1438
1439                 spin_unlock(&dev->lock);
1440                 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1441                 spin_lock(&dev->lock);
1442
1443                 if (i < 0) {
1444                         /* setup processing failed, force stall */
1445                         s3c_udc_ep0_set_stall(ep);
1446                         dev->ep0state = WAIT_FOR_SETUP;
1447
1448                         debug_cond(DEBUG_SETUP != 0,
1449                                    "\tdev->driver->setup failed (%d),"
1450                                     " bRequest = %d\n",
1451                                 i, usb_ctrl->bRequest);
1452
1453
1454                 } else if (dev->req_pending) {
1455                         dev->req_pending = 0;
1456                         debug_cond(DEBUG_SETUP != 0,
1457                                    "\tdev->req_pending...\n");
1458                 }
1459
1460                 debug_cond(DEBUG_SETUP != 0,
1461                            "\tep0state = %s\n", state_names[dev->ep0state]);
1462
1463         }
1464 }
1465
1466 /*
1467  * handle ep0 interrupt
1468  */
1469 static void s3c_handle_ep0(struct s3c_udc *dev)
1470 {
1471         if (dev->ep0state == WAIT_FOR_SETUP) {
1472                 debug_cond(DEBUG_OUT_EP != 0,
1473                            "%s: WAIT_FOR_SETUP\n", __func__);
1474                 s3c_ep0_setup(dev);
1475
1476         } else {
1477                 debug_cond(DEBUG_OUT_EP != 0,
1478                            "%s: strange state!!(state = %s)\n",
1479                         __func__, state_names[dev->ep0state]);
1480         }
1481 }
1482
1483 static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep)
1484 {
1485         debug_cond(DEBUG_EP0 != 0,
1486                    "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1487         if (ep_is_in(ep)) {
1488                 dev->ep0state = DATA_STATE_XMIT;
1489                 s3c_ep0_write(dev);
1490
1491         } else {
1492                 dev->ep0state = DATA_STATE_RECV;
1493                 s3c_ep0_read(dev);
1494         }
1495 }