drivers/usb/gadget/s3c_udc_otg_xfer_dma.c

   1 /*
   2  * drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
   3  * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
   4  *
   5  * Copyright (C) 2009 for Samsung Electronics
   6  *
   7  * BSP Support for Samsung's UDC driver
   8  * available at:
   9  * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  10  *
  11  * State machine bugfixes:
  12  * Marek Szyprowski <m.szyprowski@samsung.com>
  13  *
  14  * Ported to u-boot:
  15  * Marek Szyprowski <m.szyprowski@samsung.com>
  16  * Lukasz Majewski <l.majewski@samsumg.com>
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  */
  33
  34 static u8 clear_feature_num;
  35 int clear_feature_flag;
  36
  37 /* Bulk-Only Mass Storage Reset (class-specific request) */
  38 #define GET_MAX_LUN_REQUEST     0xFE
  39 #define BOT_RESET_REQUEST       0xFF
  40
  41 static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev)
  42 {
  43         u32 ep_ctrl;
  44
  45         flush_dcache_range((unsigned long) usb_ctrl_dma_addr,
  46                            (unsigned long) usb_ctrl_dma_addr
  47                            + DMA_BUFFER_SIZE);
  48
  49         writel(usb_ctrl_dma_addr, &reg->in_endp[EP0_CON].diepdma);
  50         writel(DIEPT_SIZ_PKT_CNT(1), &reg->in_endp[EP0_CON].dieptsiz);
  51
  52         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  53         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
  54                &reg->in_endp[EP0_CON].diepctl);
  55
  56         DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  57                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  58         dev->ep0state = WAIT_FOR_IN_COMPLETE;
  59 }
  60
  61 void s3c_udc_pre_setup(void)
  62 {
  63         u32 ep_ctrl;
  64
  65         debug_cond(DEBUG_IN_EP, "%s : Prepare Setup packets.\n", __func__);
  66
  67         invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
  68                                 (unsigned long) usb_ctrl_dma_addr
  69                                 + DMA_BUFFER_SIZE);
  70
  71         writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
  72                &reg->out_endp[EP0_CON].doeptsiz);
  73         writel(usb_ctrl_dma_addr, &reg->out_endp[EP0_CON].doepdma);
  74
  75         ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  76         writel(ep_ctrl|DEPCTL_EPENA, &reg->out_endp[EP0_CON].doepctl);
  77
  78         DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  79                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  80         DEBUG_EP0("%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  81                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  82
  83 }
  84
  85 static inline void s3c_ep0_complete_out(void)
  86 {
  87         u32 ep_ctrl;
  88
  89         DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  90                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  91         DEBUG_EP0("%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  92                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  93
  94         debug_cond(DEBUG_IN_EP,
  95                 "%s : Prepare Complete Out packet.\n", __func__);
  96
  97         invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
  98                                 (unsigned long) usb_ctrl_dma_addr
  99                                 + DMA_BUFFER_SIZE);
 100
 101         writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
 102                &reg->out_endp[EP0_CON].doeptsiz);
 103         writel(usb_ctrl_dma_addr, &reg->out_endp[EP0_CON].doepdma);
 104
 105         ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
 106         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
 107                &reg->out_endp[EP0_CON].doepctl);
 108
 109         DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
 110                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
 111         DEBUG_EP0("%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
 112                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
 113
 114 }
 115
 116
 117 static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req)
 118 {
 119         u32 *buf, ctrl;
 120         u32 length, pktcnt;
 121         u32 ep_num = ep_index(ep);
 122
 123         buf = req->req.buf + req->req.actual;
 124
 125         length = min(req->req.length - req->req.actual, (int)ep->ep.maxpacket);
 126
 127         ep->len = length;
 128         ep->dma_buf = buf;
 129
 130         invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_num],
 131                                 (unsigned long) ep->dev->dma_buf[ep_num]
 132                                 + DMA_BUFFER_SIZE);
 133
 134         if (length == 0)
 135                 pktcnt = 1;
 136         else
 137                 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
 138
 139         pktcnt = 1;
 140         ctrl =  readl(&reg->out_endp[ep_num].doepctl);
 141
 142         writel(the_controller->dma_addr[ep_index(ep)+1],
 143                &reg->out_endp[ep_num].doepdma);
 144         writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
 145                &reg->out_endp[ep_num].doeptsiz);
 146         writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->out_endp[ep_num].doepctl);
 147
 148         DEBUG_OUT_EP("%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
 149                      "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
 150                      "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
 151                      __func__, ep_num,
 152                      readl(&reg->out_endp[ep_num].doepdma),
 153                      readl(&reg->out_endp[ep_num].doeptsiz),
 154                      readl(&reg->out_endp[ep_num].doepctl),
 155                      buf, pktcnt, length);
 156         return 0;
 157
 158 }
 159
 160 int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
 161 {
 162         u32 *buf, ctrl = 0;
 163         u32 length, pktcnt;
 164         u32 ep_num = ep_index(ep);
 165         u32 *p = the_controller->dma_buf[ep_index(ep)+1];
 166
 167         buf = req->req.buf + req->req.actual;
 168         length = req->req.length - req->req.actual;
 169
 170         if (ep_num == EP0_CON)
 171                 length = min_t(length, (u32)ep_maxpacket(ep));
 172
 173         ep->len = length;
 174         ep->dma_buf = buf;
 175         memcpy(p, ep->dma_buf, length);
 176
 177         flush_dcache_range((unsigned long) p ,
 178                            (unsigned long) p + DMA_BUFFER_SIZE);
 179
 180         if (length == 0)
 181                 pktcnt = 1;
 182         else
 183                 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
 184
 185         /* Flush the endpoint's Tx FIFO */
 186         writel(TX_FIFO_NUMBER(ep->fifo_num), &reg->grstctl);
 187         writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, &reg->grstctl);
 188         while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
 189                 ;
 190
 191         writel(the_controller->dma_addr[ep_index(ep)+1],
 192                &reg->in_endp[ep_num].diepdma);
 193         writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
 194                &reg->in_endp[ep_num].dieptsiz);
 195
 196         ctrl = readl(&reg->in_endp[ep_num].diepctl);
 197
 198         /* Write the FIFO number to be used for this endpoint */
 199         ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
 200         ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
 201
 202         /* Clear reserved (Next EP) bits */
 203         ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
 204
 205         writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->in_endp[ep_num].diepctl);
 206
 207         debug_cond(DEBUG_IN_EP,
 208                 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
 209                 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
 210                 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
 211                 __func__, ep_num,
 212                 readl(&reg->in_endp[ep_num].diepdma),
 213                 readl(&reg->in_endp[ep_num].dieptsiz),
 214                 readl(&reg->in_endp[ep_num].diepctl),
 215                 buf, pktcnt, length);
 216
 217         return length;
 218 }
 219
 220 static void complete_rx(struct s3c_udc *dev, u8 ep_num)
 221 {
 222         struct s3c_ep *ep = &dev->ep[ep_num];
 223         struct s3c_request *req = NULL;
 224         u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
 225         u32 *p = the_controller->dma_buf[ep_index(ep)+1];
 226
 227         if (list_empty(&ep->queue)) {
 228                 DEBUG_OUT_EP("%s: RX DMA done : NULL REQ on OUT EP-%d\n",
 229                                         __func__, ep_num);
 230                 return;
 231
 232         }
 233
 234         req = list_entry(ep->queue.next, struct s3c_request, queue);
 235         ep_tsr = readl(&reg->out_endp[ep_num].doeptsiz);
 236
 237         if (ep_num == EP0_CON)
 238                 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
 239         else
 240                 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
 241
 242         xfer_size = ep->len - xfer_size;
 243
 244         invalidate_dcache_range((unsigned long) p,
 245                                 (unsigned long) p + DMA_BUFFER_SIZE);
 246
 247         memcpy(ep->dma_buf, p, ep->len);
 248
 249         req->req.actual += min(xfer_size, req->req.length - req->req.actual);
 250         is_short = (xfer_size < ep->ep.maxpacket);
 251
 252         DEBUG_OUT_EP("%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
 253                      "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
 254                         __func__, ep_num, req->req.actual, req->req.length,
 255                         is_short, ep_tsr, xfer_size);
 256
 257         if (is_short || req->req.actual == req->req.length) {
 258                 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
 259                         DEBUG_OUT_EP("  => Send ZLP\n");
 260                         s3c_udc_ep0_zlp(dev);
 261                         /* packet will be completed in complete_tx() */
 262                         dev->ep0state = WAIT_FOR_IN_COMPLETE;
 263                 } else {
 264                         done(ep, req, 0);
 265
 266                         if (!list_empty(&ep->queue)) {
 267                                 req = list_entry(ep->queue.next,
 268                                         struct s3c_request, queue);
 269                                 DEBUG_OUT_EP("%s: Next Rx request start...\n",
 270                                          __func__);
 271                                 setdma_rx(ep, req);
 272                         }
 273                 }
 274         } else
 275                 setdma_rx(ep, req);
 276 }
 277
 278 static void complete_tx(struct s3c_udc *dev, u8 ep_num)
 279 {
 280         struct s3c_ep *ep = &dev->ep[ep_num];
 281         struct s3c_request *req;
 282         u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
 283         u32 last;
 284
 285         if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
 286                 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
 287                 s3c_ep0_complete_out();
 288                 return;
 289         }
 290
 291         if (list_empty(&ep->queue)) {
 292                 debug_cond(DEBUG_IN_EP,
 293                         "%s: TX DMA done : NULL REQ on IN EP-%d\n",
 294                         __func__, ep_num);
 295                 return;
 296
 297         }
 298
 299         req = list_entry(ep->queue.next, struct s3c_request, queue);
 300
 301         ep_tsr = readl(&reg->in_endp[ep_num].dieptsiz);
 302
 303         xfer_size = ep->len;
 304         is_short = (xfer_size < ep->ep.maxpacket);
 305         req->req.actual += min(xfer_size, req->req.length - req->req.actual);
 306
 307         debug_cond(DEBUG_IN_EP,
 308                 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
 309                 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
 310                 __func__, ep_num, req->req.actual, req->req.length,
 311                 is_short, ep_tsr, xfer_size);
 312
 313         if (ep_num == 0) {
 314                 if (dev->ep0state == DATA_STATE_XMIT) {
 315                         debug_cond(DEBUG_IN_EP,
 316                                 "%s: ep_num = %d, ep0stat =="
 317                                 "DATA_STATE_XMIT\n",
 318                                 __func__, ep_num);
 319                         last = write_fifo_ep0(ep, req);
 320                         if (last)
 321                                 dev->ep0state = WAIT_FOR_COMPLETE;
 322                 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
 323                         debug_cond(DEBUG_IN_EP,
 324                                 "%s: ep_num = %d, completing request\n",
 325                                 __func__, ep_num);
 326                         done(ep, req, 0);
 327                         dev->ep0state = WAIT_FOR_SETUP;
 328                 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
 329                         debug_cond(DEBUG_IN_EP,
 330                                 "%s: ep_num = %d, completing request\n",
 331                                 __func__, ep_num);
 332                         done(ep, req, 0);
 333                         dev->ep0state = WAIT_FOR_OUT_COMPLETE;
 334                         s3c_ep0_complete_out();
 335                 } else {
 336                         debug_cond(DEBUG_IN_EP,
 337                                 "%s: ep_num = %d, invalid ep state\n",
 338                                 __func__, ep_num);
 339                 }
 340                 return;
 341         }
 342
 343         if (req->req.actual == req->req.length)
 344                 done(ep, req, 0);
 345
 346         if (!list_empty(&ep->queue)) {
 347                 req = list_entry(ep->queue.next, struct s3c_request, queue);
 348                 debug_cond(DEBUG_IN_EP,
 349                         "%s: Next Tx request start...\n", __func__);
 350                 setdma_tx(ep, req);
 351         }
 352 }
 353
 354 static inline void s3c_udc_check_tx_queue(struct s3c_udc *dev, u8 ep_num)
 355 {
 356         struct s3c_ep *ep = &dev->ep[ep_num];
 357         struct s3c_request *req;
 358
 359         debug_cond(DEBUG_IN_EP,
 360                 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
 361
 362         if (!list_empty(&ep->queue)) {
 363                 req = list_entry(ep->queue.next, struct s3c_request, queue);
 364                 debug_cond(DEBUG_IN_EP,
 365                         "%s: Next Tx request(0x%p) start...\n",
 366                         __func__, req);
 367
 368                 if (ep_is_in(ep))
 369                         setdma_tx(ep, req);
 370                 else
 371                         setdma_rx(ep, req);
 372         } else {
 373                 debug_cond(DEBUG_IN_EP,
 374                         "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
 375
 376                 return;
 377         }
 378
 379 }
 380
 381 static void process_ep_in_intr(struct s3c_udc *dev)
 382 {
 383         u32 ep_intr, ep_intr_status;
 384         u8 ep_num = 0;
 385
 386         ep_intr = readl(&reg->daint);
 387         debug_cond(DEBUG_IN_EP,
 388                 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
 389
 390         ep_intr &= DAINT_MASK;
 391
 392         while (ep_intr) {
 393                 if (ep_intr & DAINT_IN_EP_INT(1)) {
 394                         ep_intr_status = readl(&reg->in_endp[ep_num].diepint);
 395                         debug_cond(DEBUG_IN_EP, "\tEP%d-IN : DIEPINT = 0x%x\n",
 396                                                 ep_num, ep_intr_status);
 397
 398                         /* Interrupt Clear */
 399                         writel(ep_intr_status, &reg->in_endp[ep_num].diepint);
 400
 401                         if (ep_intr_status & TRANSFER_DONE) {
 402                                 complete_tx(dev, ep_num);
 403
 404                                 if (ep_num == 0) {
 405                                         if (dev->ep0state ==
 406                                             WAIT_FOR_IN_COMPLETE)
 407                                                 dev->ep0state = WAIT_FOR_SETUP;
 408
 409                                         if (dev->ep0state == WAIT_FOR_SETUP)
 410                                                 s3c_udc_pre_setup();
 411
 412                                         /* continue transfer after
 413                                            set_clear_halt for DMA mode */
 414                                         if (clear_feature_flag == 1) {
 415                                                 s3c_udc_check_tx_queue(dev,
 416                                                         clear_feature_num);
 417                                                 clear_feature_flag = 0;
 418                                         }
 419                                 }
 420                         }
 421                 }
 422                 ep_num++;
 423                 ep_intr >>= 1;
 424         }
 425 }
 426
 427 static void process_ep_out_intr(struct s3c_udc *dev)
 428 {
 429         u32 ep_intr, ep_intr_status;
 430         u8 ep_num = 0;
 431
 432         ep_intr = readl(&reg->daint);
 433         DEBUG_OUT_EP("*** %s: EP OUT interrupt : DAINT = 0x%x\n",
 434                                 __func__, ep_intr);
 435
 436         ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
 437
 438         while (ep_intr) {
 439                 if (ep_intr & 0x1) {
 440                         ep_intr_status = readl(&reg->out_endp[ep_num].doepint);
 441                         DEBUG_OUT_EP("\tEP%d-OUT : DOEPINT = 0x%x\n",
 442                                                 ep_num, ep_intr_status);
 443
 444                         /* Interrupt Clear */
 445                         writel(ep_intr_status, &reg->out_endp[ep_num].doepint);
 446
 447                         if (ep_num == 0) {
 448                                 if (ep_intr_status & TRANSFER_DONE) {
 449                                         if (dev->ep0state !=
 450                                             WAIT_FOR_OUT_COMPLETE)
 451                                                 complete_rx(dev, ep_num);
 452                                         else {
 453                                                 dev->ep0state = WAIT_FOR_SETUP;
 454                                                 s3c_udc_pre_setup();
 455                                         }
 456                                 }
 457
 458                                 if (ep_intr_status &
 459                                     CTRL_OUT_EP_SETUP_PHASE_DONE) {
 460                                         DEBUG_OUT_EP("SETUP packet arrived\n");
 461                                         s3c_handle_ep0(dev);
 462                                 }
 463                         } else {
 464                                 if (ep_intr_status & TRANSFER_DONE)
 465                                         complete_rx(dev, ep_num);
 466                         }
 467                 }
 468                 ep_num++;
 469                 ep_intr >>= 1;
 470         }
 471 }
 472
 473 /*
 474  *      usb client interrupt handler.
 475  */
 476 static int s3c_udc_irq(int irq, void *_dev)
 477 {
 478         struct s3c_udc *dev = _dev;
 479         u32 intr_status;
 480         u32 usb_status, gintmsk;
 481         unsigned long flags;
 482
 483         spin_lock_irqsave(&dev->lock, flags);
 484
 485         intr_status = readl(&reg->gintsts);
 486         gintmsk = readl(&reg->gintmsk);
 487
 488         debug_cond(DEBUG_ISR,
 489                   "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
 490                   "DAINT : 0x%x, DAINTMSK : 0x%x\n",
 491                   __func__, intr_status, state_names[dev->ep0state], gintmsk,
 492                   readl(&reg->daint), readl(&reg->daintmsk));
 493
 494         if (!intr_status) {
 495                 spin_unlock_irqrestore(&dev->lock, flags);
 496                 return IRQ_HANDLED;
 497         }
 498
 499         if (intr_status & INT_ENUMDONE) {
 500                 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
 501
 502                 writel(INT_ENUMDONE, &reg->gintsts);
 503                 usb_status = (readl(&reg->dsts) & 0x6);
 504
 505                 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
 506                         debug_cond(DEBUG_ISR, "\t\tFull Speed Detection\n");
 507                         set_max_pktsize(dev, USB_SPEED_FULL);
 508
 509                 } else {
 510                         debug_cond(DEBUG_ISR,
 511                                 "\t\tHigh Speed Detection : 0x%x\n",
 512                                 usb_status);
 513                         set_max_pktsize(dev, USB_SPEED_HIGH);
 514                 }
 515         }
 516
 517         if (intr_status & INT_EARLY_SUSPEND) {
 518                 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
 519                 writel(INT_EARLY_SUSPEND, &reg->gintsts);
 520         }
 521
 522         if (intr_status & INT_SUSPEND) {
 523                 usb_status = readl(&reg->dsts);
 524                 debug_cond(DEBUG_ISR,
 525                         "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
 526                 writel(INT_SUSPEND, &reg->gintsts);
 527
 528                 if (dev->gadget.speed != USB_SPEED_UNKNOWN
 529                     && dev->driver) {
 530                         if (dev->driver->suspend)
 531                                 dev->driver->suspend(&dev->gadget);
 532
 533                         /* HACK to let gadget detect disconnected state */
 534                         if (dev->driver->disconnect) {
 535                                 spin_unlock_irqrestore(&dev->lock, flags);
 536                                 dev->driver->disconnect(&dev->gadget);
 537                                 spin_lock_irqsave(&dev->lock, flags);
 538                         }
 539                 }
 540         }
 541
 542         if (intr_status & INT_RESUME) {
 543                 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
 544                 writel(INT_RESUME, &reg->gintsts);
 545
 546                 if (dev->gadget.speed != USB_SPEED_UNKNOWN
 547                     && dev->driver
 548                     && dev->driver->resume) {
 549
 550                         dev->driver->resume(&dev->gadget);
 551                 }
 552         }
 553
 554         if (intr_status & INT_RESET) {
 555                 usb_status = readl(&reg->gotgctl);
 556                 debug_cond(DEBUG_ISR,
 557                         "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
 558                 writel(INT_RESET, &reg->gintsts);
 559
 560                 if ((usb_status & 0xc0000) == (0x3 << 18)) {
 561                         if (reset_available) {
 562                                 debug_cond(DEBUG_ISR,
 563                                         "\t\tOTG core got reset (%d)!!\n",
 564                                         reset_available);
 565                                 reconfig_usbd();
 566                                 dev->ep0state = WAIT_FOR_SETUP;
 567                                 reset_available = 0;
 568                                 s3c_udc_pre_setup();
 569                         } else
 570                                 reset_available = 1;
 571
 572                 } else {
 573                         reset_available = 1;
 574                         debug_cond(DEBUG_ISR, "\t\tRESET handling skipped\n");
 575                 }
 576         }
 577
 578         if (intr_status & INT_IN_EP)
 579                 process_ep_in_intr(dev);
 580
 581         if (intr_status & INT_OUT_EP)
 582                 process_ep_out_intr(dev);
 583
 584         spin_unlock_irqrestore(&dev->lock, flags);
 585
 586         return IRQ_HANDLED;
 587 }
 588
 589 /** Queue one request
 590  *  Kickstart transfer if needed
 591  */
 592 static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req,
 593                          gfp_t gfp_flags)
 594 {
 595         struct s3c_request *req;
 596         struct s3c_ep *ep;
 597         struct s3c_udc *dev;
 598         unsigned long flags;
 599         u32 ep_num, gintsts;
 600
 601         req = container_of(_req, struct s3c_request, req);
 602         if (unlikely(!_req || !_req->complete || !_req->buf
 603                      || !list_empty(&req->queue))) {
 604
 605                 debug("%s: bad params\n", __func__);
 606                 return -EINVAL;
 607         }
 608
 609         ep = container_of(_ep, struct s3c_ep, ep);
 610
 611         if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
 612
 613                 debug("%s: bad ep: %s, %d, %p\n", __func__,
 614                       ep->ep.name, !ep->desc, _ep);
 615                 return -EINVAL;
 616         }
 617
 618         ep_num = ep_index(ep);
 619         dev = ep->dev;
 620         if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 621
 622                 debug("%s: bogus device state %p\n", __func__, dev->driver);
 623                 return -ESHUTDOWN;
 624         }
 625
 626         spin_lock_irqsave(&dev->lock, flags);
 627
 628         _req->status = -EINPROGRESS;
 629         _req->actual = 0;
 630
 631         /* kickstart this i/o queue? */
 632         debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
 633                 "Q empty = %d, stopped = %d\n",
 634                 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
 635                 _req, _req->length, _req->buf,
 636                 list_empty(&ep->queue), ep->stopped);
 637
 638 #ifdef DEBUG_S3C_UDC
 639         {
 640                 int i, len = _req->length;
 641
 642                 printf("pkt = ");
 643                 if (len > 64)
 644                         len = 64;
 645                 for (i = 0; i < len; i++) {
 646                         printf("%02x", ((u8 *)_req->buf)[i]);
 647                         if ((i & 7) == 7)
 648                                 printf(" ");
 649                 }
 650                 printf("\n");
 651         }
 652 #endif
 653
 654         if (list_empty(&ep->queue) && !ep->stopped) {
 655
 656                 if (ep_num == 0) {
 657                         /* EP0 */
 658                         list_add_tail(&req->queue, &ep->queue);
 659                         s3c_ep0_kick(dev, ep);
 660                         req = 0;
 661
 662                 } else if (ep_is_in(ep)) {
 663                         gintsts = readl(&reg->gintsts);
 664                         debug_cond(DEBUG_IN_EP,
 665                                 "%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n",
 666                                 __func__, gintsts);
 667
 668                         setdma_tx(ep, req);
 669                 } else {
 670                         gintsts = readl(&reg->gintsts);
 671                         DEBUG_OUT_EP("%s:ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n",
 672                                 __func__, gintsts);
 673
 674                         setdma_rx(ep, req);
 675                 }
 676         }
 677
 678         /* pio or dma irq handler advances the queue. */
 679         if (likely(req != 0))
 680                 list_add_tail(&req->queue, &ep->queue);
 681
 682         spin_unlock_irqrestore(&dev->lock, flags);
 683
 684         return 0;
 685 }
 686
 687 /****************************************************************/
 688 /* End Point 0 related functions                                */
 689 /****************************************************************/
 690
 691 /* return:  0 = still running, 1 = completed, negative = errno */
 692 static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
 693 {
 694         u32 max;
 695         unsigned count;
 696         int is_last;
 697
 698         max = ep_maxpacket(ep);
 699
 700         DEBUG_EP0("%s: max = %d\n", __func__, max);
 701
 702         count = setdma_tx(ep, req);
 703
 704         /* last packet is usually short (or a zlp) */
 705         if (likely(count != max))
 706                 is_last = 1;
 707         else {
 708                 if (likely(req->req.length != req->req.actual + count)
 709                     || req->req.zero)
 710                         is_last = 0;
 711                 else
 712                         is_last = 1;
 713         }
 714
 715         DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __func__,
 716                   ep->ep.name, count,
 717                   is_last ? "/L" : "",
 718                   req->req.length - req->req.actual - count, req);
 719
 720         /* requests complete when all IN data is in the FIFO */
 721         if (is_last) {
 722                 ep->dev->ep0state = WAIT_FOR_SETUP;
 723                 return 1;
 724         }
 725
 726         return 0;
 727 }
 728
 729 int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max)
 730 {
 731         u32 bytes;
 732
 733         bytes = sizeof(struct usb_ctrlrequest);
 734
 735         invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)],
 736                                 (unsigned long) ep->dev->dma_buf[ep_index(ep)]
 737                                 + DMA_BUFFER_SIZE);
 738
 739         DEBUG_EP0("%s: bytes=%d, ep_index=%d %p\n", __func__,
 740                   bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]);
 741
 742         return bytes;
 743 }
 744
 745 /**
 746  * udc_set_address - set the USB address for this device
 747  * @address:
 748  *
 749  * Called from control endpoint function
 750  * after it decodes a set address setup packet.
 751  */
 752 static void udc_set_address(struct s3c_udc *dev, unsigned char address)
 753 {
 754         u32 ctrl = readl(&reg->dcfg);
 755         writel(DEVICE_ADDRESS(address) | ctrl, &reg->dcfg);
 756
 757         s3c_udc_ep0_zlp(dev);
 758
 759         DEBUG_EP0("%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
 760                 __func__, address, readl(&reg->dcfg));
 761
 762         dev->usb_address = address;
 763 }
 764
 765 static inline void s3c_udc_ep0_set_stall(struct s3c_ep *ep)
 766 {
 767         struct s3c_udc *dev;
 768         u32             ep_ctrl = 0;
 769
 770         dev = ep->dev;
 771         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
 772
 773         /* set the disable and stall bits */
 774         if (ep_ctrl & DEPCTL_EPENA)
 775                 ep_ctrl |= DEPCTL_EPDIS;
 776
 777         ep_ctrl |= DEPCTL_STALL;
 778
 779         writel(ep_ctrl, &reg->in_endp[EP0_CON].diepctl);
 780
 781         DEBUG_EP0("%s: set ep%d stall, DIEPCTL0 = 0x%x\n",
 782                 __func__, ep_index(ep), &reg->in_endp[EP0_CON].diepctl);
 783         /*
 784          * The application can only set this bit, and the core clears it,
 785          * when a SETUP token is received for this endpoint
 786          */
 787         dev->ep0state = WAIT_FOR_SETUP;
 788
 789         s3c_udc_pre_setup();
 790 }
 791
 792 static void s3c_ep0_read(struct s3c_udc *dev)
 793 {
 794         struct s3c_request *req;
 795         struct s3c_ep *ep = &dev->ep[0];
 796
 797         if (!list_empty(&ep->queue)) {
 798                 req = list_entry(ep->queue.next, struct s3c_request, queue);
 799
 800         } else {
 801                 debug("%s: ---> BUG\n", __func__);
 802                 BUG();
 803                 return;
 804         }
 805
 806         DEBUG_EP0("%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
 807                 __func__, req, req->req.length, req->req.actual);
 808
 809         if (req->req.length == 0) {
 810                 /* zlp for Set_configuration, Set_interface,
 811                  * or Bulk-Only mass storge reset */
 812
 813                 ep->len = 0;
 814                 s3c_udc_ep0_zlp(dev);
 815
 816                 DEBUG_EP0("%s: req.length = 0, bRequest = %d\n",
 817                           __func__, usb_ctrl->bRequest);
 818                 return;
 819         }
 820
 821         setdma_rx(ep, req);
 822 }
 823
 824 /*
 825  * DATA_STATE_XMIT
 826  */
 827 static int s3c_ep0_write(struct s3c_udc *dev)
 828 {
 829         struct s3c_request *req;
 830         struct s3c_ep *ep = &dev->ep[0];
 831         int ret, need_zlp = 0;
 832
 833         if (list_empty(&ep->queue))
 834                 req = 0;
 835         else
 836                 req = list_entry(ep->queue.next, struct s3c_request, queue);
 837
 838         if (!req) {
 839                 DEBUG_EP0("%s: NULL REQ\n", __func__);
 840                 return 0;
 841         }
 842
 843         DEBUG_EP0("%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
 844                 __func__, req, req->req.length, req->req.actual);
 845
 846         if (req->req.length - req->req.actual == ep0_fifo_size) {
 847                 /* Next write will end with the packet size, */
 848                 /* so we need Zero-length-packet */
 849                 need_zlp = 1;
 850         }
 851
 852         ret = write_fifo_ep0(ep, req);
 853
 854         if ((ret == 1) && !need_zlp) {
 855                 /* Last packet */
 856                 dev->ep0state = WAIT_FOR_COMPLETE;
 857                 DEBUG_EP0("%s: finished, waiting for status\n", __func__);
 858
 859         } else {
 860                 dev->ep0state = DATA_STATE_XMIT;
 861                 DEBUG_EP0("%s: not finished\n", __func__);
 862         }
 863
 864         return 1;
 865 }
 866
 867 u16     g_status;
 868
 869 int s3c_udc_get_status(struct s3c_udc *dev,
 870                 struct usb_ctrlrequest *crq)
 871 {
 872         u8 ep_num = crq->wIndex & 0x7F;
 873         u32 ep_ctrl;
 874         u32 *p = the_controller->dma_buf[1];
 875
 876         DEBUG_SETUP("%s: *** USB_REQ_GET_STATUS\n", __func__);
 877         printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
 878         switch (crq->bRequestType & USB_RECIP_MASK) {
 879         case USB_RECIP_INTERFACE:
 880                 g_status = 0;
 881                 DEBUG_SETUP("\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
 882                             g_status);
 883                 break;
 884
 885         case USB_RECIP_DEVICE:
 886                 g_status = 0x1; /* Self powered */
 887                 DEBUG_SETUP("\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
 888                             g_status);
 889                 break;
 890
 891         case USB_RECIP_ENDPOINT:
 892                 if (crq->wLength > 2) {
 893                         DEBUG_SETUP("\tGET_STATUS:Not support EP or wLength\n");
 894                         return 1;
 895                 }
 896
 897                 g_status = dev->ep[ep_num].stopped;
 898                 DEBUG_SETUP("\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
 899                             g_status);
 900
 901                 break;
 902
 903         default:
 904                 return 1;
 905         }
 906
 907         memcpy(p, &g_status, sizeof(g_status));
 908
 909         flush_dcache_range((unsigned long) p,
 910                            (unsigned long) p + DMA_BUFFER_SIZE);
 911
 912         writel(the_controller->dma_addr[1], &reg->in_endp[EP0_CON].diepdma);
 913         writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
 914                &reg->in_endp[EP0_CON].dieptsiz);
 915
 916         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
 917         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
 918                &reg->in_endp[EP0_CON].diepctl);
 919         dev->ep0state = WAIT_FOR_NULL_COMPLETE;
 920
 921         return 0;
 922 }
 923
 924 static void s3c_udc_set_nak(struct s3c_ep *ep)
 925 {
 926         u8              ep_num;
 927         u32             ep_ctrl = 0;
 928
 929         ep_num = ep_index(ep);
 930         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
 931
 932         if (ep_is_in(ep)) {
 933                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
 934                 ep_ctrl |= DEPCTL_SNAK;
 935                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
 936                 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
 937                         __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
 938         } else {
 939                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
 940                 ep_ctrl |= DEPCTL_SNAK;
 941                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
 942                 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
 943                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
 944         }
 945
 946         return;
 947 }
 948
 949
 950 void s3c_udc_ep_set_stall(struct s3c_ep *ep)
 951 {
 952         u8              ep_num;
 953         u32             ep_ctrl = 0;
 954
 955         ep_num = ep_index(ep);
 956         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
 957
 958         if (ep_is_in(ep)) {
 959                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
 960
 961                 /* set the disable and stall bits */
 962                 if (ep_ctrl & DEPCTL_EPENA)
 963                         ep_ctrl |= DEPCTL_EPDIS;
 964
 965                 ep_ctrl |= DEPCTL_STALL;
 966
 967                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
 968                 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
 969                       __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
 970
 971         } else {
 972                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
 973
 974                 /* set the stall bit */
 975                 ep_ctrl |= DEPCTL_STALL;
 976
 977                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
 978                 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
 979                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
 980         }
 981
 982         return;
 983 }
 984
 985 void s3c_udc_ep_clear_stall(struct s3c_ep *ep)
 986 {
 987         u8              ep_num;
 988         u32             ep_ctrl = 0;
 989
 990         ep_num = ep_index(ep);
 991         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
 992
 993         if (ep_is_in(ep)) {
 994                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
 995
 996                 /* clear stall bit */
 997                 ep_ctrl &= ~DEPCTL_STALL;
 998
 999                 /*
1000                  * USB Spec 9.4.5: For endpoints using data toggle, regardless
1001                  * of whether an endpoint has the Halt feature set, a
1002                  * ClearFeature(ENDPOINT_HALT) request always results in the
1003                  * data toggle being reinitialized to DATA0.
1004                  */
1005                 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1006                     || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1007                         ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1008                 }
1009
1010                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
1011                 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1012                         __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
1013
1014         } else {
1015                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
1016
1017                 /* clear stall bit */
1018                 ep_ctrl &= ~DEPCTL_STALL;
1019
1020                 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1021                     || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1022                         ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1023                 }
1024
1025                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1026                 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1027                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
1028         }
1029
1030         return;
1031 }
1032
1033 static int s3c_udc_set_halt(struct usb_ep *_ep, int value)
1034 {
1035         struct s3c_ep   *ep;
1036         struct s3c_udc  *dev;
1037         unsigned long   flags;
1038         u8              ep_num;
1039
1040         ep = container_of(_ep, struct s3c_ep, ep);
1041         ep_num = ep_index(ep);
1042
1043         if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1044                      ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1045                 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1046                 return -EINVAL;
1047         }
1048
1049         /* Attempt to halt IN ep will fail if any transfer requests
1050          * are still queue */
1051         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1052                 debug("%s: %s queue not empty, req = %p\n",
1053                         __func__, ep->ep.name,
1054                         list_entry(ep->queue.next, struct s3c_request, queue));
1055
1056                 return -EAGAIN;
1057         }
1058
1059         dev = ep->dev;
1060         debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1061
1062         spin_lock_irqsave(&dev->lock, flags);
1063
1064         if (value == 0) {
1065                 ep->stopped = 0;
1066                 s3c_udc_ep_clear_stall(ep);
1067         } else {
1068                 if (ep_num == 0)
1069                         dev->ep0state = WAIT_FOR_SETUP;
1070
1071                 ep->stopped = 1;
1072                 s3c_udc_ep_set_stall(ep);
1073         }
1074
1075         spin_unlock_irqrestore(&dev->lock, flags);
1076
1077         return 0;
1078 }
1079
1080 void s3c_udc_ep_activate(struct s3c_ep *ep)
1081 {
1082         u8 ep_num;
1083         u32 ep_ctrl = 0, daintmsk = 0;
1084
1085         ep_num = ep_index(ep);
1086
1087         /* Read DEPCTLn register */
1088         if (ep_is_in(ep)) {
1089                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
1090                 daintmsk = 1 << ep_num;
1091         } else {
1092                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
1093                 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1094         }
1095
1096         debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1097                 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1098
1099         /* If the EP is already active don't change the EP Control
1100          * register. */
1101         if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1102                 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1103                         (ep->bmAttributes << DEPCTL_TYPE_BIT);
1104                 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1105                         (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1106                 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1107
1108                 if (ep_is_in(ep)) {
1109                         writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
1110                         debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1111                               __func__, ep_num, ep_num,
1112                               readl(&reg->in_endp[ep_num].diepctl));
1113                 } else {
1114                         writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1115                         debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1116                               __func__, ep_num, ep_num,
1117                               readl(&reg->out_endp[ep_num].doepctl));
1118                 }
1119         }
1120
1121         /* Unmask EP Interrtupt */
1122         writel(readl(&reg->daintmsk)|daintmsk, &reg->daintmsk);
1123         debug("%s: DAINTMSK = 0x%x\n", __func__, readl(&reg->daintmsk));
1124
1125 }
1126
1127 static int s3c_udc_clear_feature(struct usb_ep *_ep)
1128 {
1129         struct s3c_udc  *dev;
1130         struct s3c_ep   *ep;
1131         u8              ep_num;
1132
1133         ep = container_of(_ep, struct s3c_ep, ep);
1134         ep_num = ep_index(ep);
1135
1136         dev = ep->dev;
1137         DEBUG_SETUP("%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1138                 __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1139
1140         if (usb_ctrl->wLength != 0) {
1141                 DEBUG_SETUP("\tCLEAR_FEATURE: wLength is not zero.....\n");
1142                 return 1;
1143         }
1144
1145         switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1146         case USB_RECIP_DEVICE:
1147                 switch (usb_ctrl->wValue) {
1148                 case USB_DEVICE_REMOTE_WAKEUP:
1149                         DEBUG_SETUP("\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1150                         break;
1151
1152                 case USB_DEVICE_TEST_MODE:
1153                         DEBUG_SETUP("\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1154                         /** @todo Add CLEAR_FEATURE for TEST modes. */
1155                         break;
1156                 }
1157
1158                 s3c_udc_ep0_zlp(dev);
1159                 break;
1160
1161         case USB_RECIP_ENDPOINT:
1162                 DEBUG_SETUP("\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1163                                 usb_ctrl->wValue);
1164
1165                 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1166                         if (ep_num == 0) {
1167                                 s3c_udc_ep0_set_stall(ep);
1168                                 return 0;
1169                         }
1170
1171                         s3c_udc_ep0_zlp(dev);
1172
1173                         s3c_udc_ep_clear_stall(ep);
1174                         s3c_udc_ep_activate(ep);
1175                         ep->stopped = 0;
1176
1177                         clear_feature_num = ep_num;
1178                         clear_feature_flag = 1;
1179                 }
1180                 break;
1181         }
1182
1183         return 0;
1184 }
1185
1186 static int s3c_udc_set_feature(struct usb_ep *_ep)
1187 {
1188         struct s3c_udc  *dev;
1189         struct s3c_ep   *ep;
1190         u8              ep_num;
1191
1192         ep = container_of(_ep, struct s3c_ep, ep);
1193         ep_num = ep_index(ep);
1194         dev = ep->dev;
1195
1196         DEBUG_SETUP("%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1197                     __func__, ep_num);
1198
1199         if (usb_ctrl->wLength != 0) {
1200                 DEBUG_SETUP("\tSET_FEATURE: wLength is not zero.....\n");
1201                 return 1;
1202         }
1203
1204         switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1205         case USB_RECIP_DEVICE:
1206                 switch (usb_ctrl->wValue) {
1207                 case USB_DEVICE_REMOTE_WAKEUP:
1208                         DEBUG_SETUP("\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1209                         break;
1210                 case USB_DEVICE_B_HNP_ENABLE:
1211                         DEBUG_SETUP("\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1212                         break;
1213
1214                 case USB_DEVICE_A_HNP_SUPPORT:
1215                         /* RH port supports HNP */
1216                         DEBUG_SETUP("\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1217                         break;
1218
1219                 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1220                         /* other RH port does */
1221                         DEBUG_SETUP("\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1222                         break;
1223                 }
1224
1225                 s3c_udc_ep0_zlp(dev);
1226                 return 0;
1227
1228         case USB_RECIP_INTERFACE:
1229                 DEBUG_SETUP("\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1230                 break;
1231
1232         case USB_RECIP_ENDPOINT:
1233                 DEBUG_SETUP("\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1234                 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1235                         if (ep_num == 0) {
1236                                 s3c_udc_ep0_set_stall(ep);
1237                                 return 0;
1238                         }
1239                         ep->stopped = 1;
1240                         s3c_udc_ep_set_stall(ep);
1241                 }
1242
1243                 s3c_udc_ep0_zlp(dev);
1244                 return 0;
1245         }
1246
1247         return 1;
1248 }
1249
1250 /*
1251  * WAIT_FOR_SETUP (OUT_PKT_RDY)
1252  */
1253 void s3c_ep0_setup(struct s3c_udc *dev)
1254 {
1255         struct s3c_ep *ep = &dev->ep[0];
1256         int i;
1257         u8 ep_num;
1258
1259         /* Nuke all previous transfers */
1260         nuke(ep, -EPROTO);
1261
1262         /* read control req from fifo (8 bytes) */
1263         s3c_fifo_read(ep, (u32 *)usb_ctrl, 8);
1264
1265         DEBUG_SETUP("%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1266                     "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1267                     __func__, usb_ctrl->bRequestType,
1268                     (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1269                     usb_ctrl->bRequest,
1270                     usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1271
1272 #ifdef DEBUG_S3C_UDC
1273         {
1274                 int i, len = sizeof(*usb_ctrl);
1275                 char *p = (char *)usb_ctrl;
1276
1277                 printf("pkt = ");
1278                 for (i = 0; i < len; i++) {
1279                         printf("%02x", ((u8 *)p)[i]);
1280                         if ((i & 7) == 7)
1281                                 printf(" ");
1282                 }
1283                 printf("\n");
1284         }
1285 #endif
1286
1287         if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1288             usb_ctrl->wLength != 1) {
1289                 DEBUG_SETUP("\t%s:GET_MAX_LUN_REQUEST:invalid",
1290                               __func__);
1291                 DEBUG_SETUP("wLength = %d, setup returned\n",
1292                             usb_ctrl->wLength);
1293
1294                 s3c_udc_ep0_set_stall(ep);
1295                 dev->ep0state = WAIT_FOR_SETUP;
1296
1297                 return;
1298         } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1299                  usb_ctrl->wLength != 0) {
1300                 /* Bulk-Only *mass storge reset of class-specific request */
1301                 DEBUG_SETUP("%s:BOT Rest:invalid wLength =%d, setup returned\n",
1302                             __func__, usb_ctrl->wLength);
1303
1304                 s3c_udc_ep0_set_stall(ep);
1305                 dev->ep0state = WAIT_FOR_SETUP;
1306
1307                 return;
1308         }
1309
1310         /* Set direction of EP0 */
1311         if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1312                 ep->bEndpointAddress |= USB_DIR_IN;
1313         } else {
1314                 ep->bEndpointAddress &= ~USB_DIR_IN;
1315         }
1316         /* cope with automagic for some standard requests. */
1317         dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1318                 == USB_TYPE_STANDARD;
1319
1320         dev->req_pending = 1;
1321
1322         /* Handle some SETUP packets ourselves */
1323         if (dev->req_std) {
1324                 switch (usb_ctrl->bRequest) {
1325                 case USB_REQ_SET_ADDRESS:
1326                 DEBUG_SETUP("%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1327                                 __func__, usb_ctrl->wValue);
1328                         if (usb_ctrl->bRequestType
1329                                 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1330                                 break;
1331
1332                         udc_set_address(dev, usb_ctrl->wValue);
1333                         return;
1334
1335                 case USB_REQ_SET_CONFIGURATION:
1336                         DEBUG_SETUP("=====================================\n");
1337                         DEBUG_SETUP("%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1338                                         __func__, usb_ctrl->wValue);
1339
1340                         if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1341                                 reset_available = 1;
1342
1343                         break;
1344
1345                 case USB_REQ_GET_DESCRIPTOR:
1346                         DEBUG_SETUP("%s: *** USB_REQ_GET_DESCRIPTOR\n",
1347                                     __func__);
1348                         break;
1349
1350                 case USB_REQ_SET_INTERFACE:
1351                         DEBUG_SETUP("%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1352                                         __func__, usb_ctrl->wValue);
1353
1354                         if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1355                                 reset_available = 1;
1356
1357                         break;
1358
1359                 case USB_REQ_GET_CONFIGURATION:
1360                         DEBUG_SETUP("%s: *** USB_REQ_GET_CONFIGURATION\n",
1361                                     __func__);
1362                         break;
1363
1364                 case USB_REQ_GET_STATUS:
1365                         if (!s3c_udc_get_status(dev, usb_ctrl))
1366                                 return;
1367
1368                         break;
1369
1370                 case USB_REQ_CLEAR_FEATURE:
1371                         ep_num = usb_ctrl->wIndex & 0x7f;
1372
1373                         if (!s3c_udc_clear_feature(&dev->ep[ep_num].ep))
1374                                 return;
1375
1376                         break;
1377
1378                 case USB_REQ_SET_FEATURE:
1379                         ep_num = usb_ctrl->wIndex & 0x7f;
1380
1381                         if (!s3c_udc_set_feature(&dev->ep[ep_num].ep))
1382                                 return;
1383
1384                         break;
1385
1386                 default:
1387                         DEBUG_SETUP("%s: *** Default of usb_ctrl->bRequest=0x%x"
1388                                 "happened.\n", __func__, usb_ctrl->bRequest);
1389                         break;
1390                 }
1391         }
1392
1393
1394         if (likely(dev->driver)) {
1395                 /* device-2-host (IN) or no data setup command,
1396                  * process immediately */
1397                 DEBUG_SETUP("%s:usb_ctrlreq will be passed to fsg_setup()\n",
1398                             __func__);
1399
1400                 spin_unlock(&dev->lock);
1401                 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1402                 spin_lock(&dev->lock);
1403
1404                 if (i < 0) {
1405                         /* setup processing failed, force stall */
1406                         s3c_udc_ep0_set_stall(ep);
1407                         dev->ep0state = WAIT_FOR_SETUP;
1408
1409                         DEBUG_SETUP("\tdev->driver->setup failed (%d),"
1410                                     " bRequest = %d\n",
1411                                 i, usb_ctrl->bRequest);
1412
1413
1414                 } else if (dev->req_pending) {
1415                         dev->req_pending = 0;
1416                         DEBUG_SETUP("\tdev->req_pending...\n");
1417                 }
1418
1419                 DEBUG_SETUP("\tep0state = %s\n", state_names[dev->ep0state]);
1420
1421         }
1422 }
1423
1424 /*
1425  * handle ep0 interrupt
1426  */
1427 static void s3c_handle_ep0(struct s3c_udc *dev)
1428 {
1429         if (dev->ep0state == WAIT_FOR_SETUP) {
1430                 DEBUG_OUT_EP("%s: WAIT_FOR_SETUP\n", __func__);
1431                 s3c_ep0_setup(dev);
1432
1433         } else {
1434                 DEBUG_OUT_EP("%s: strange state!!(state = %s)\n",
1435                         __func__, state_names[dev->ep0state]);
1436         }
1437 }
1438
1439 static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep)
1440 {
1441         DEBUG_EP0("%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1442         if (ep_is_in(ep)) {
1443                 dev->ep0state = DATA_STATE_XMIT;
1444                 s3c_ep0_write(dev);
1445
1446         } else {
1447                 dev->ep0state = DATA_STATE_RECV;
1448                 s3c_ep0_read(dev);
1449         }
1450 }