1 // SPDX-License-Identifier: GPL-2.0+
3 * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
5 * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
6 * Copyright (C) 2003 Robert Schwebel, Pengutronix
7 * Copyright (C) 2003 Benedikt Spranger, Pengutronix
8 * Copyright (C) 2003 David Brownell
9 * Copyright (C) 2003 Joshua Wise
10 * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
12 * MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
15 #define CONFIG_USB_PXA25X_SMALL
16 #define DRIVER_NAME "pxa25x_udc_linux"
17 #define ARCH_HAS_PREFETCH
21 #include <asm/byteorder.h>
22 #include <asm/system.h>
23 #include <asm/mach-types.h>
24 #include <asm/unaligned.h>
25 #include <linux/compat.h>
28 #include <asm/arch/pxa.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <usb/lin_gadget_compat.h>
33 #include <asm/arch/pxa-regs.h>
35 #include "pxa25x_udc.h"
38 * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
39 * series processors. The UDC for the IXP 4xx series is very similar.
40 * There are fifteen endpoints, in addition to ep0.
42 * Such controller drivers work with a gadget driver. The gadget driver
43 * returns descriptors, implements configuration and data protocols used
44 * by the host to interact with this device, and allocates endpoints to
45 * the different protocol interfaces. The controller driver virtualizes
46 * usb hardware so that the gadget drivers will be more portable.
48 * This UDC hardware wants to implement a bit too much USB protocol, so
49 * it constrains the sorts of USB configuration change events that work.
50 * The errata for these chips are misleading; some "fixed" bugs from
51 * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
53 * Note that the UDC hardware supports DMA (except on IXP) but that's
54 * not used here. IN-DMA (to host) is simple enough, when the data is
55 * suitably aligned (16 bytes) ... the network stack doesn't do that,
56 * other software can. OUT-DMA is buggy in most chip versions, as well
57 * as poorly designed (data toggle not automatic). So this driver won't
58 * bother using DMA. (Mostly-working IN-DMA support was available in
59 * kernels before 2.6.23, but was never enabled or well tested.)
62 #define DRIVER_VERSION "18-August-2012"
63 #define DRIVER_DESC "PXA 25x USB Device Controller driver"
65 static const char driver_name[] = "pxa25x_udc";
66 static const char ep0name[] = "ep0";
69 static inline void start_watchdog(struct pxa25x_udc *udc)
71 debug("Started watchdog\n");
72 udc->watchdog.base = get_timer(0);
73 udc->watchdog.running = 1;
76 static inline void stop_watchdog(struct pxa25x_udc *udc)
78 udc->watchdog.running = 0;
79 debug("Stopped watchdog\n");
82 static inline void test_watchdog(struct pxa25x_udc *udc)
84 if (!udc->watchdog.running)
87 debug("watchdog %ld %ld\n", get_timer(udc->watchdog.base),
88 udc->watchdog.period);
90 if (get_timer(udc->watchdog.base) >= udc->watchdog.period) {
92 udc->watchdog.function(udc);
96 static void udc_watchdog(struct pxa25x_udc *dev)
98 uint32_t udccs0 = readl(&dev->regs->udccs[0]);
100 debug("Fired up udc_watchdog\n");
103 if (dev->ep0state == EP0_STALL
104 && (udccs0 & UDCCS0_FST) == 0
105 && (udccs0 & UDCCS0_SST) == 0) {
106 writel(UDCCS0_FST|UDCCS0_FTF, &dev->regs->udccs[0]);
107 debug("ep0 re-stall\n");
115 static const char * const state_name[] = {
117 "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
118 "EP0_END_XFER", "EP0_STALL"
122 dump_udccr(const char *label)
124 u32 udccr = readl(&UDC_REGS->udccr);
125 debug("%s %02X =%s%s%s%s%s%s%s%s\n",
127 (udccr & UDCCR_REM) ? " rem" : "",
128 (udccr & UDCCR_RSTIR) ? " rstir" : "",
129 (udccr & UDCCR_SRM) ? " srm" : "",
130 (udccr & UDCCR_SUSIR) ? " susir" : "",
131 (udccr & UDCCR_RESIR) ? " resir" : "",
132 (udccr & UDCCR_RSM) ? " rsm" : "",
133 (udccr & UDCCR_UDA) ? " uda" : "",
134 (udccr & UDCCR_UDE) ? " ude" : "");
138 dump_udccs0(const char *label)
140 u32 udccs0 = readl(&UDC_REGS->udccs[0]);
142 debug("%s %s %02X =%s%s%s%s%s%s%s%s\n",
143 label, state_name[the_controller->ep0state], udccs0,
144 (udccs0 & UDCCS0_SA) ? " sa" : "",
145 (udccs0 & UDCCS0_RNE) ? " rne" : "",
146 (udccs0 & UDCCS0_FST) ? " fst" : "",
147 (udccs0 & UDCCS0_SST) ? " sst" : "",
148 (udccs0 & UDCCS0_DRWF) ? " dwrf" : "",
149 (udccs0 & UDCCS0_FTF) ? " ftf" : "",
150 (udccs0 & UDCCS0_IPR) ? " ipr" : "",
151 (udccs0 & UDCCS0_OPR) ? " opr" : "");
155 dump_state(struct pxa25x_udc *dev)
160 debug("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
161 state_name[dev->ep0state],
162 readl(&UDC_REGS->uicr1), readl(&UDC_REGS->uicr0),
163 readl(&UDC_REGS->usir1), readl(&UDC_REGS->usir0),
164 readl(&UDC_REGS->ufnrh), readl(&UDC_REGS->ufnrl));
167 tmp = readl(&UDC_REGS->udccfr);
168 debug("udccfr %02X =%s%s\n", tmp,
169 (tmp & UDCCFR_AREN) ? " aren" : "",
170 (tmp & UDCCFR_ACM) ? " acm" : "");
174 debug("no gadget driver bound\n");
177 debug("ep0 driver '%s'\n", "ether");
179 dump_udccs0("udccs0");
180 debug("ep0 IN %lu/%lu, OUT %lu/%lu\n",
181 dev->stats.write.bytes, dev->stats.write.ops,
182 dev->stats.read.bytes, dev->stats.read.ops);
184 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) {
185 if (dev->ep[i].desc == NULL)
187 debug("udccs%d = %02x\n", i, *dev->ep->reg_udccs);
193 static inline void dump_udccr(const char *label) { }
194 static inline void dump_udccs0(const char *label) { }
195 static inline void dump_state(struct pxa25x_udc *dev) { }
200 * ---------------------------------------------------------------------------
201 * endpoint related parts of the api to the usb controller hardware,
202 * used by gadget driver; and the inner talker-to-hardware core.
203 * ---------------------------------------------------------------------------
206 static void pxa25x_ep_fifo_flush(struct usb_ep *ep);
207 static void nuke(struct pxa25x_ep *, int status);
209 /* one GPIO should control a D+ pullup, so host sees this device (or not) */
210 static void pullup_off(void)
212 struct pxa2xx_udc_mach_info *mach = the_controller->mach;
214 if (mach->udc_command)
215 mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
218 static void pullup_on(void)
220 struct pxa2xx_udc_mach_info *mach = the_controller->mach;
222 if (mach->udc_command)
223 mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
226 static void pio_irq_enable(int bEndpointAddress)
228 bEndpointAddress &= 0xf;
229 if (bEndpointAddress < 8) {
230 clrbits_le32(&the_controller->regs->uicr0,
231 1 << bEndpointAddress);
233 bEndpointAddress -= 8;
234 clrbits_le32(&the_controller->regs->uicr1,
235 1 << bEndpointAddress);
239 static void pio_irq_disable(int bEndpointAddress)
241 bEndpointAddress &= 0xf;
242 if (bEndpointAddress < 8) {
243 setbits_le32(&the_controller->regs->uicr0,
244 1 << bEndpointAddress);
246 bEndpointAddress -= 8;
247 setbits_le32(&the_controller->regs->uicr1,
248 1 << bEndpointAddress);
252 static inline void udc_set_mask_UDCCR(int mask)
255 * The UDCCR reg contains mask and interrupt status bits,
256 * so using '|=' isn't safe as it may ack an interrupt.
258 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
261 clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
264 static inline void udc_clear_mask_UDCCR(int mask)
266 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
268 mask = ~mask & mask_bits;
269 clrbits_le32(&the_controller->regs->udccr, ~mask);
272 static inline void udc_ack_int_UDCCR(int mask)
274 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
277 clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
281 * endpoint enable/disable
283 * we need to verify the descriptors used to enable endpoints. since pxa25x
284 * endpoint configurations are fixed, and are pretty much always enabled,
285 * there's not a lot to manage here.
287 * because pxa25x can't selectively initialize bulk (or interrupt) endpoints,
288 * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
289 * for a single interface (with only the default altsetting) and for gadget
290 * drivers that don't halt endpoints (not reset by set_interface). that also
291 * means that if you use ISO, you must violate the USB spec rule that all
292 * iso endpoints must be in non-default altsettings.
294 static int pxa25x_ep_enable(struct usb_ep *_ep,
295 const struct usb_endpoint_descriptor *desc)
297 struct pxa25x_ep *ep;
298 struct pxa25x_udc *dev;
300 ep = container_of(_ep, struct pxa25x_ep, ep);
301 if (!_ep || !desc || ep->desc || _ep->name == ep0name
302 || desc->bDescriptorType != USB_DT_ENDPOINT
303 || ep->bEndpointAddress != desc->bEndpointAddress
305 le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
306 printf("%s, bad ep or descriptor\n", __func__);
310 /* xfer types must match, except that interrupt ~= bulk */
311 if (ep->bmAttributes != desc->bmAttributes
312 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
313 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
314 printf("%s, %s type mismatch\n", __func__, _ep->name);
318 /* hardware _could_ do smaller, but driver doesn't */
319 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
320 && le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))
322 || !get_unaligned(&desc->wMaxPacketSize)) {
323 printf("%s, bad %s maxpacket\n", __func__, _ep->name);
328 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
329 printf("%s, bogus device state\n", __func__);
336 ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
338 /* flush fifo (mostly for OUT buffers) */
339 pxa25x_ep_fifo_flush(_ep);
341 /* ... reset halt state too, if we could ... */
343 debug("enabled %s\n", _ep->name);
347 static int pxa25x_ep_disable(struct usb_ep *_ep)
349 struct pxa25x_ep *ep;
352 ep = container_of(_ep, struct pxa25x_ep, ep);
353 if (!_ep || !ep->desc) {
354 printf("%s, %s not enabled\n", __func__,
355 _ep ? ep->ep.name : NULL);
358 local_irq_save(flags);
360 nuke(ep, -ESHUTDOWN);
362 /* flush fifo (mostly for IN buffers) */
363 pxa25x_ep_fifo_flush(_ep);
368 local_irq_restore(flags);
369 debug("%s disabled\n", _ep->name);
373 /*-------------------------------------------------------------------------*/
376 * for the pxa25x, these can just wrap kmalloc/kfree. gadget drivers
377 * must still pass correctly initialized endpoints, since other controller
378 * drivers may care about how it's currently set up (dma issues etc).
382 * pxa25x_ep_alloc_request - allocate a request data structure
384 static struct usb_request *
385 pxa25x_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
387 struct pxa25x_request *req;
389 req = kzalloc(sizeof(*req), gfp_flags);
393 INIT_LIST_HEAD(&req->queue);
399 * pxa25x_ep_free_request - deallocate a request data structure
402 pxa25x_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
404 struct pxa25x_request *req;
406 req = container_of(_req, struct pxa25x_request, req);
407 WARN_ON(!list_empty(&req->queue));
411 /*-------------------------------------------------------------------------*/
414 * done - retire a request; caller blocked irqs
416 static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status)
418 unsigned stopped = ep->stopped;
420 list_del_init(&req->queue);
422 if (likely(req->req.status == -EINPROGRESS))
423 req->req.status = status;
425 status = req->req.status;
427 if (status && status != -ESHUTDOWN)
428 debug("complete %s req %p stat %d len %u/%u\n",
429 ep->ep.name, &req->req, status,
430 req->req.actual, req->req.length);
432 /* don't modify queue heads during completion callback */
434 req->req.complete(&ep->ep, &req->req);
435 ep->stopped = stopped;
439 static inline void ep0_idle(struct pxa25x_udc *dev)
441 dev->ep0state = EP0_IDLE;
445 write_packet(u32 *uddr, struct pxa25x_request *req, unsigned max)
448 unsigned length, count;
450 debug("%s(): uddr %p\n", __func__, uddr);
452 buf = req->req.buf + req->req.actual;
455 /* how big will this packet be? */
456 length = min(req->req.length - req->req.actual, max);
457 req->req.actual += length;
460 while (likely(count--))
461 writeb(*buf++, uddr);
467 * write to an IN endpoint fifo, as many packets as possible.
468 * irqs will use this to write the rest later.
469 * caller guarantees at least one packet buffer is ready (or a zlp).
472 write_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
476 max = le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize));
479 int is_last, is_short;
481 count = write_packet(ep->reg_uddr, req, max);
483 /* last packet is usually short (or a zlp) */
484 if (unlikely(count != max))
485 is_last = is_short = 1;
487 if (likely(req->req.length != req->req.actual)
492 /* interrupt/iso maxpacket may not fill the fifo */
493 is_short = unlikely(max < ep->fifo_size);
496 debug_cond(NOISY, "wrote %s %d bytes%s%s %d left %p\n",
498 is_last ? "/L" : "", is_short ? "/S" : "",
499 req->req.length - req->req.actual, req);
502 * let loose that packet. maybe try writing another one,
503 * double buffering might work. TSP, TPC, and TFS
504 * bit values are the same for all normal IN endpoints.
506 writel(UDCCS_BI_TPC, ep->reg_udccs);
508 writel(UDCCS_BI_TSP, ep->reg_udccs);
510 /* requests complete when all IN data is in the FIFO */
513 if (list_empty(&ep->queue))
514 pio_irq_disable(ep->bEndpointAddress);
519 * TODO experiment: how robust can fifo mode tweaking be?
520 * double buffering is off in the default fifo mode, which
521 * prevents TFS from being set here.
524 } while (readl(ep->reg_udccs) & UDCCS_BI_TFS);
529 * caller asserts req->pending (ep0 irq status nyet cleared); starts
530 * ep0 data stage. these chips want very simple state transitions.
533 void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag)
535 writel(flags|UDCCS0_SA|UDCCS0_OPR, &dev->regs->udccs[0]);
536 writel(USIR0_IR0, &dev->regs->usir0);
537 dev->req_pending = 0;
538 debug_cond(NOISY, "%s() %s, udccs0: %02x/%02x usir: %X.%X\n",
539 __func__, tag, readl(&dev->regs->udccs[0]), flags,
540 readl(&dev->regs->usir1), readl(&dev->regs->usir0));
544 write_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
549 count = write_packet(&ep->dev->regs->uddr0, req, EP0_FIFO_SIZE);
550 ep->dev->stats.write.bytes += count;
552 /* last packet "must be" short (or a zlp) */
553 is_short = (count != EP0_FIFO_SIZE);
555 debug_cond(NOISY, "ep0in %d bytes %d left %p\n", count,
556 req->req.length - req->req.actual, req);
558 if (unlikely(is_short)) {
559 if (ep->dev->req_pending)
560 ep0start(ep->dev, UDCCS0_IPR, "short IN");
562 writel(UDCCS0_IPR, &ep->dev->regs->udccs[0]);
564 count = req->req.length;
569 * This seems to get rid of lost status irqs in some cases:
570 * host responds quickly, or next request involves config
571 * change automagic, or should have been hidden, or ...
573 * FIXME get rid of all udelays possible...
575 if (count >= EP0_FIFO_SIZE) {
578 if ((readl(&ep->dev->regs->udccs[0]) &
580 /* clear OPR, generate ack */
582 &ep->dev->regs->udccs[0]);
589 } else if (ep->dev->req_pending)
590 ep0start(ep->dev, 0, "IN");
597 * read_fifo - unload packet(s) from the fifo we use for usb OUT
598 * transfers and put them into the request. caller should have made
599 * sure there's at least one packet ready.
601 * returns true if the request completed because of short packet or the
602 * request buffer having filled (and maybe overran till end-of-packet).
605 read_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
609 unsigned bufferspace, count, is_short;
613 * make sure there's a packet in the FIFO.
614 * UDCCS_{BO,IO}_RPC are all the same bit value.
615 * UDCCS_{BO,IO}_RNE are all the same bit value.
617 udccs = readl(ep->reg_udccs);
618 if (unlikely((udccs & UDCCS_BO_RPC) == 0))
620 buf = req->req.buf + req->req.actual;
622 bufferspace = req->req.length - req->req.actual;
624 /* read all bytes from this packet */
625 if (likely(udccs & UDCCS_BO_RNE)) {
626 count = 1 + (0x0ff & readl(ep->reg_ubcr));
627 req->req.actual += min(count, bufferspace);
630 is_short = (count < ep->ep.maxpacket);
631 debug_cond(NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
632 ep->ep.name, udccs, count,
633 is_short ? "/S" : "",
634 req, req->req.actual, req->req.length);
635 while (likely(count-- != 0)) {
636 u8 byte = readb(ep->reg_uddr);
638 if (unlikely(bufferspace == 0)) {
640 * this happens when the driver's buffer
641 * is smaller than what the host sent.
642 * discard the extra data.
644 if (req->req.status != -EOVERFLOW)
645 printf("%s overflow %d\n",
647 req->req.status = -EOVERFLOW;
653 writel(UDCCS_BO_RPC, ep->reg_udccs);
654 /* RPC/RSP/RNE could now reflect the other packet buffer */
656 /* iso is one request per packet */
657 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
658 if (udccs & UDCCS_IO_ROF)
659 req->req.status = -EHOSTUNREACH;
660 /* more like "is_done" */
665 if (is_short || req->req.actual == req->req.length) {
667 if (list_empty(&ep->queue))
668 pio_irq_disable(ep->bEndpointAddress);
672 /* finished that packet. the next one may be waiting... */
678 * special ep0 version of the above. no UBCR0 or double buffering; status
679 * handshaking is magic. most device protocols don't need control-OUT.
680 * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
681 * protocols do use them.
684 read_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
687 unsigned bufferspace;
689 buf = req->req.buf + req->req.actual;
690 bufferspace = req->req.length - req->req.actual;
692 while (readl(&ep->dev->regs->udccs[0]) & UDCCS0_RNE) {
693 byte = (u8)readb(&ep->dev->regs->uddr0);
695 if (unlikely(bufferspace == 0)) {
697 * this happens when the driver's buffer
698 * is smaller than what the host sent.
699 * discard the extra data.
701 if (req->req.status != -EOVERFLOW)
702 printf("%s overflow\n", ep->ep.name);
703 req->req.status = -EOVERFLOW;
711 writel(UDCCS0_OPR | UDCCS0_IPR, &ep->dev->regs->udccs[0]);
714 if (req->req.actual >= req->req.length)
717 /* finished that packet. the next one may be waiting... */
721 /*-------------------------------------------------------------------------*/
724 pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
726 struct pxa25x_request *req;
727 struct pxa25x_ep *ep;
728 struct pxa25x_udc *dev;
731 req = container_of(_req, struct pxa25x_request, req);
732 if (unlikely(!_req || !_req->complete || !_req->buf
733 || !list_empty(&req->queue))) {
734 printf("%s, bad params\n", __func__);
738 ep = container_of(_ep, struct pxa25x_ep, ep);
739 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
740 printf("%s, bad ep\n", __func__);
745 if (unlikely(!dev->driver
746 || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
747 printf("%s, bogus device state\n", __func__);
752 * iso is always one packet per request, that's the only way
753 * we can report per-packet status. that also helps with dma.
755 if (unlikely(ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
757 le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize))))
760 debug_cond(NOISY, "%s queue req %p, len %d buf %p\n",
761 _ep->name, _req, _req->length, _req->buf);
763 local_irq_save(flags);
765 _req->status = -EINPROGRESS;
768 /* kickstart this i/o queue? */
769 if (list_empty(&ep->queue) && !ep->stopped) {
770 if (ep->desc == NULL/* ep0 */) {
771 unsigned length = _req->length;
773 switch (dev->ep0state) {
774 case EP0_IN_DATA_PHASE:
775 dev->stats.write.ops++;
776 if (write_ep0_fifo(ep, req))
780 case EP0_OUT_DATA_PHASE:
781 dev->stats.read.ops++;
783 if (dev->req_config) {
784 debug("ep0 config ack%s\n",
785 dev->has_cfr ? "" : " raced");
787 writel(UDCCFR_AREN|UDCCFR_ACM
789 &ep->dev->regs->udccfr);
791 dev->ep0state = EP0_END_XFER;
792 local_irq_restore(flags);
795 if (dev->req_pending)
796 ep0start(dev, UDCCS0_IPR, "OUT");
799 &ep->dev->regs->udccs[0])
801 && read_ep0_fifo(ep, req))) {
809 printf("ep0 i/o, odd state %d\n",
811 local_irq_restore(flags);
814 /* can the FIFO can satisfy the request immediately? */
815 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
816 if ((readl(ep->reg_udccs) & UDCCS_BI_TFS) != 0
817 && write_fifo(ep, req))
819 } else if ((readl(ep->reg_udccs) & UDCCS_BO_RFS) != 0
820 && read_fifo(ep, req)) {
824 if (likely(req && ep->desc))
825 pio_irq_enable(ep->bEndpointAddress);
828 /* pio or dma irq handler advances the queue. */
829 if (likely(req != NULL))
830 list_add_tail(&req->queue, &ep->queue);
831 local_irq_restore(flags);
838 * nuke - dequeue ALL requests
840 static void nuke(struct pxa25x_ep *ep, int status)
842 struct pxa25x_request *req;
844 /* called with irqs blocked */
845 while (!list_empty(&ep->queue)) {
846 req = list_entry(ep->queue.next,
847 struct pxa25x_request,
849 done(ep, req, status);
852 pio_irq_disable(ep->bEndpointAddress);
856 /* dequeue JUST ONE request */
857 static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
859 struct pxa25x_ep *ep;
860 struct pxa25x_request *req;
863 ep = container_of(_ep, struct pxa25x_ep, ep);
864 if (!_ep || ep->ep.name == ep0name)
867 local_irq_save(flags);
869 /* make sure it's actually queued on this endpoint */
870 list_for_each_entry(req, &ep->queue, queue) {
871 if (&req->req == _req)
874 if (&req->req != _req) {
875 local_irq_restore(flags);
879 done(ep, req, -ECONNRESET);
881 local_irq_restore(flags);
885 /*-------------------------------------------------------------------------*/
887 static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value)
889 struct pxa25x_ep *ep;
892 ep = container_of(_ep, struct pxa25x_ep, ep);
894 || (!ep->desc && ep->ep.name != ep0name))
895 || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
896 printf("%s, bad ep\n", __func__);
901 * this path (reset toggle+halt) is needed to implement
902 * SET_INTERFACE on normal hardware. but it can't be
903 * done from software on the PXA UDC, and the hardware
904 * forgets to do it as part of SET_INTERFACE automagic.
906 printf("only host can clear %s halt\n", _ep->name);
910 local_irq_save(flags);
912 if ((ep->bEndpointAddress & USB_DIR_IN) != 0
913 && ((readl(ep->reg_udccs) & UDCCS_BI_TFS) == 0
914 || !list_empty(&ep->queue))) {
915 local_irq_restore(flags);
919 /* FST bit is the same for control, bulk in, bulk out, interrupt in */
920 writel(UDCCS_BI_FST|UDCCS_BI_FTF, ep->reg_udccs);
922 /* ep0 needs special care */
924 start_watchdog(ep->dev);
925 ep->dev->req_pending = 0;
926 ep->dev->ep0state = EP0_STALL;
928 /* and bulk/intr endpoints like dropping stalls too */
931 for (i = 0; i < 1000; i += 20) {
932 if (readl(ep->reg_udccs) & UDCCS_BI_SST)
937 local_irq_restore(flags);
939 debug("%s halt\n", _ep->name);
943 static int pxa25x_ep_fifo_status(struct usb_ep *_ep)
945 struct pxa25x_ep *ep;
947 ep = container_of(_ep, struct pxa25x_ep, ep);
949 printf("%s, bad ep\n", __func__);
952 /* pxa can't report unclaimed bytes from IN fifos */
953 if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
955 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
956 || (readl(ep->reg_udccs) & UDCCS_BO_RFS) == 0)
959 return (readl(ep->reg_ubcr) & 0xfff) + 1;
962 static void pxa25x_ep_fifo_flush(struct usb_ep *_ep)
964 struct pxa25x_ep *ep;
966 ep = container_of(_ep, struct pxa25x_ep, ep);
967 if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
968 printf("%s, bad ep\n", __func__);
972 /* toggle and halt bits stay unchanged */
974 /* for OUT, just read and discard the FIFO contents. */
975 if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
976 while (((readl(ep->reg_udccs)) & UDCCS_BO_RNE) != 0)
977 (void)readb(ep->reg_uddr);
981 /* most IN status is the same, but ISO can't stall */
982 writel(UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
983 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
984 ? 0 : UDCCS_BI_SST), ep->reg_udccs);
988 static struct usb_ep_ops pxa25x_ep_ops = {
989 .enable = pxa25x_ep_enable,
990 .disable = pxa25x_ep_disable,
992 .alloc_request = pxa25x_ep_alloc_request,
993 .free_request = pxa25x_ep_free_request,
995 .queue = pxa25x_ep_queue,
996 .dequeue = pxa25x_ep_dequeue,
998 .set_halt = pxa25x_ep_set_halt,
999 .fifo_status = pxa25x_ep_fifo_status,
1000 .fifo_flush = pxa25x_ep_fifo_flush,
1004 /* ---------------------------------------------------------------------------
1005 * device-scoped parts of the api to the usb controller hardware
1006 * ---------------------------------------------------------------------------
1009 static int pxa25x_udc_get_frame(struct usb_gadget *_gadget)
1011 return ((readl(&the_controller->regs->ufnrh) & 0x07) << 8) |
1012 (readl(&the_controller->regs->ufnrl) & 0xff);
1015 static int pxa25x_udc_wakeup(struct usb_gadget *_gadget)
1017 /* host may not have enabled remote wakeup */
1018 if ((readl(&the_controller->regs->udccs[0]) & UDCCS0_DRWF) == 0)
1019 return -EHOSTUNREACH;
1020 udc_set_mask_UDCCR(UDCCR_RSM);
1024 static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *);
1025 static void udc_enable(struct pxa25x_udc *);
1026 static void udc_disable(struct pxa25x_udc *);
1029 * We disable the UDC -- and its 48 MHz clock -- whenever it's not
1032 static int pullup(struct pxa25x_udc *udc)
1040 int is_active = udc->pullup;
1048 if (udc->gadget.speed != USB_SPEED_UNKNOWN)
1049 stop_activity(udc, udc->driver);
1058 /* VBUS reporting logically comes from a transceiver */
1059 static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
1061 struct pxa25x_udc *udc;
1063 udc = container_of(_gadget, struct pxa25x_udc, gadget);
1064 printf("vbus %s\n", is_active ? "supplied" : "inactive");
1069 /* drivers may have software control over D+ pullup */
1070 static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active)
1072 struct pxa25x_udc *udc;
1074 udc = container_of(_gadget, struct pxa25x_udc, gadget);
1076 /* not all boards support pullup control */
1077 if (!udc->mach->udc_command)
1080 udc->pullup = (is_active != 0);
1086 * boards may consume current from VBUS, up to 100-500mA based on config.
1087 * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs
1088 * violate USB specs.
1090 static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1095 static const struct usb_gadget_ops pxa25x_udc_ops = {
1096 .get_frame = pxa25x_udc_get_frame,
1097 .wakeup = pxa25x_udc_wakeup,
1098 .vbus_session = pxa25x_udc_vbus_session,
1099 .pullup = pxa25x_udc_pullup,
1100 .vbus_draw = pxa25x_udc_vbus_draw,
1103 /*-------------------------------------------------------------------------*/
1106 * udc_disable - disable USB device controller
1108 static void udc_disable(struct pxa25x_udc *dev)
1110 /* block all irqs */
1111 udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
1112 writel(0xff, &dev->regs->uicr0);
1113 writel(0xff, &dev->regs->uicr1);
1114 writel(UFNRH_SIM, &dev->regs->ufnrh);
1116 /* if hardware supports it, disconnect from usb */
1119 udc_clear_mask_UDCCR(UDCCR_UDE);
1122 dev->gadget.speed = USB_SPEED_UNKNOWN;
1126 * udc_reinit - initialize software state
1128 static void udc_reinit(struct pxa25x_udc *dev)
1132 /* device/ep0 records init */
1133 INIT_LIST_HEAD(&dev->gadget.ep_list);
1134 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1135 dev->ep0state = EP0_IDLE;
1137 /* basic endpoint records init */
1138 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1139 struct pxa25x_ep *ep = &dev->ep[i];
1142 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
1146 INIT_LIST_HEAD(&ep->queue);
1150 /* the rest was statically initialized, and is read-only */
1154 * until it's enabled, this UDC should be completely invisible
1157 static void udc_enable(struct pxa25x_udc *dev)
1159 debug("udc: enabling udc\n");
1161 udc_clear_mask_UDCCR(UDCCR_UDE);
1164 * Try to clear these bits before we enable the udc.
1165 * Do not touch reset ack bit, we would take care of it in
1166 * interrupt handle routine
1168 udc_ack_int_UDCCR(UDCCR_SUSIR|UDCCR_RESIR);
1171 dev->gadget.speed = USB_SPEED_UNKNOWN;
1172 dev->stats.irqs = 0;
1175 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1177 * - if RESET is already in progress, ack interrupt
1178 * - unmask reset interrupt
1180 udc_set_mask_UDCCR(UDCCR_UDE);
1181 if (!(readl(&dev->regs->udccr) & UDCCR_UDA))
1182 udc_ack_int_UDCCR(UDCCR_RSTIR);
1184 if (dev->has_cfr /* UDC_RES2 is defined */) {
1186 * pxa255 (a0+) can avoid a set_config race that could
1187 * prevent gadget drivers from configuring correctly
1189 writel(UDCCFR_ACM | UDCCFR_MB1, &dev->regs->udccfr);
1192 /* enable suspend/resume and reset irqs */
1193 udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1195 /* enable ep0 irqs */
1196 clrbits_le32(&dev->regs->uicr0, UICR0_IM0);
1198 /* if hardware supports it, pullup D+ and wait for reset */
1202 static inline void clear_ep_state(struct pxa25x_udc *dev)
1207 * hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1208 * fifos, and pending transactions mustn't be continued in any case.
1210 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1211 nuke(&dev->ep[i], -ECONNABORTED);
1214 static void handle_ep0(struct pxa25x_udc *dev)
1216 u32 udccs0 = readl(&dev->regs->udccs[0]);
1217 struct pxa25x_ep *ep = &dev->ep[0];
1218 struct pxa25x_request *req;
1220 struct usb_ctrlrequest r;
1225 if (list_empty(&ep->queue))
1228 req = list_entry(ep->queue.next, struct pxa25x_request, queue);
1230 /* clear stall status */
1231 if (udccs0 & UDCCS0_SST) {
1233 writel(UDCCS0_SST, &dev->regs->udccs[0]);
1238 /* previous request unfinished? non-error iff back-to-back ... */
1239 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1245 switch (dev->ep0state) {
1247 /* late-breaking status? */
1248 udccs0 = readl(&dev->regs->udccs[0]);
1250 /* start control request? */
1251 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1252 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1257 /* read SETUP packet */
1258 for (i = 0; i < 8; i++) {
1259 if (unlikely(!(readl(&dev->regs->udccs[0]) &
1262 debug("SETUP %d!\n", i);
1265 u.raw[i] = (u8)readb(&dev->regs->uddr0);
1267 if (unlikely((readl(&dev->regs->udccs[0]) &
1272 debug("SETUP %02x.%02x v%04x i%04x l%04x\n",
1273 u.r.bRequestType, u.r.bRequest,
1274 le16_to_cpu(u.r.wValue),
1275 le16_to_cpu(u.r.wIndex),
1276 le16_to_cpu(u.r.wLength));
1278 /* cope with automagic for some standard requests. */
1279 dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1280 == USB_TYPE_STANDARD;
1281 dev->req_config = 0;
1282 dev->req_pending = 1;
1283 switch (u.r.bRequest) {
1284 /* hardware restricts gadget drivers here! */
1285 case USB_REQ_SET_CONFIGURATION:
1286 debug("GOT SET_CONFIGURATION\n");
1287 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1289 * reflect hardware's automagic
1290 * up to the gadget driver.
1293 dev->req_config = 1;
1294 clear_ep_state(dev);
1296 * if !has_cfr, there's no synch
1297 * else use AREN (later) not SA|OPR
1298 * USIR0_IR0 acts edge sensitive
1302 /* ... and here, even more ... */
1303 case USB_REQ_SET_INTERFACE:
1304 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1306 * udc hardware is broken by design:
1307 * - altsetting may only be zero;
1308 * - hw resets all interfaces' eps;
1309 * - ep reset doesn't include halt(?).
1311 printf("broken set_interface (%d/%d)\n",
1312 le16_to_cpu(u.r.wIndex),
1313 le16_to_cpu(u.r.wValue));
1317 /* hardware was supposed to hide this */
1318 case USB_REQ_SET_ADDRESS:
1319 debug("GOT SET ADDRESS\n");
1320 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1321 ep0start(dev, 0, "address");
1327 if (u.r.bRequestType & USB_DIR_IN)
1328 dev->ep0state = EP0_IN_DATA_PHASE;
1330 dev->ep0state = EP0_OUT_DATA_PHASE;
1332 i = dev->driver->setup(&dev->gadget, &u.r);
1334 /* hardware automagic preventing STALL... */
1335 if (dev->req_config) {
1337 * hardware sometimes neglects to tell
1338 * tell us about config change events,
1339 * so later ones may fail...
1341 printf("config change %02x fail %d?\n",
1345 * TODO experiment: if has_cfr,
1346 * hardware didn't ACK; maybe we
1347 * could actually STALL!
1352 /* uninitialized when goto stall */
1355 debug("protocol STALL, "
1357 readl(&dev->regs->udccs[0]), i);
1360 * the watchdog timer helps deal with cases
1361 * where udc seems to clear FST wrongly, and
1362 * then NAKs instead of STALLing.
1364 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1365 start_watchdog(dev);
1366 dev->ep0state = EP0_STALL;
1368 /* deferred i/o == no response yet */
1369 } else if (dev->req_pending) {
1370 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1371 || dev->req_std || u.r.wLength))
1372 ep0start(dev, 0, "defer");
1374 ep0start(dev, UDCCS0_IPR, "defer/IPR");
1377 /* expect at least one data or status stage irq */
1380 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1381 == (UDCCS0_OPR|UDCCS0_SA))) {
1385 * pxa210/250 erratum 131 for B0/B1 says RNE lies.
1386 * still observed on a pxa255 a0.
1391 /* read SETUP data, but don't trust it too much */
1392 for (i = 0; i < 8; i++)
1393 u.raw[i] = (u8)readb(&dev->regs->uddr0);
1394 if ((u.r.bRequestType & USB_RECIP_MASK)
1397 if (u.word[0] == 0 && u.word[1] == 0)
1402 * some random early IRQ:
1405 * - OPR got set, without SA (likely status stage)
1407 debug("random IRQ %X %X\n", udccs0,
1408 readl(&dev->regs->udccs[0]));
1409 writel(udccs0 & (UDCCS0_SA|UDCCS0_OPR),
1410 &dev->regs->udccs[0]);
1413 case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
1414 if (udccs0 & UDCCS0_OPR) {
1415 debug("ep0in premature status\n");
1419 } else /* irq was IPR clearing */ {
1421 debug("next ep0 in packet\n");
1422 /* this IN packet might finish the request */
1423 (void) write_ep0_fifo(ep, req);
1424 } /* else IN token before response was written */
1427 case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
1428 if (udccs0 & UDCCS0_OPR) {
1430 /* this OUT packet might finish the request */
1431 if (read_ep0_fifo(ep, req))
1433 /* else more OUT packets expected */
1434 } /* else OUT token before read was issued */
1435 } else /* irq was IPR clearing */ {
1436 debug("ep0out premature status\n");
1446 * ack control-IN status (maybe in-zlp was skipped)
1447 * also appears after some config change events.
1449 if (udccs0 & UDCCS0_OPR)
1450 writel(UDCCS0_OPR, &dev->regs->udccs[0]);
1454 writel(UDCCS0_FST, &dev->regs->udccs[0]);
1458 writel(USIR0_IR0, &dev->regs->usir0);
1461 static void handle_ep(struct pxa25x_ep *ep)
1463 struct pxa25x_request *req;
1464 int is_in = ep->bEndpointAddress & USB_DIR_IN;
1470 if (likely(!list_empty(&ep->queue)))
1471 req = list_entry(ep->queue.next,
1472 struct pxa25x_request, queue);
1476 /* TODO check FST handling */
1478 udccs = readl(ep->reg_udccs);
1479 if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */
1481 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1482 tmp |= UDCCS_BI_SST;
1485 writel(tmp, ep->reg_udccs);
1486 if (req && likely((udccs & UDCCS_BI_TFS) != 0))
1487 completed = write_fifo(ep, req);
1489 } else { /* irq from RPC (or for ISO, ROF) */
1490 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1491 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
1493 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
1496 writel(tmp, ep->reg_udccs);
1498 /* fifos can hold packets, ready for reading... */
1500 completed = read_fifo(ep, req);
1502 pio_irq_disable(ep->bEndpointAddress);
1505 } while (completed);
1509 * pxa25x_udc_irq - interrupt handler
1511 * avoid delays in ep0 processing. the control handshaking isn't always
1512 * under software control (pxa250c0 and the pxa255 are better), and delays
1513 * could cause usb protocol errors.
1515 static struct pxa25x_udc memory;
1517 pxa25x_udc_irq(void)
1519 struct pxa25x_udc *dev = &memory;
1526 u32 udccr = readl(&dev->regs->udccr);
1530 /* SUSpend Interrupt Request */
1531 if (unlikely(udccr & UDCCR_SUSIR)) {
1532 udc_ack_int_UDCCR(UDCCR_SUSIR);
1534 debug("USB suspend\n");
1536 if (dev->gadget.speed != USB_SPEED_UNKNOWN
1538 && dev->driver->suspend)
1539 dev->driver->suspend(&dev->gadget);
1543 /* RESume Interrupt Request */
1544 if (unlikely(udccr & UDCCR_RESIR)) {
1545 udc_ack_int_UDCCR(UDCCR_RESIR);
1547 debug("USB resume\n");
1549 if (dev->gadget.speed != USB_SPEED_UNKNOWN
1551 && dev->driver->resume)
1552 dev->driver->resume(&dev->gadget);
1555 /* ReSeT Interrupt Request - USB reset */
1556 if (unlikely(udccr & UDCCR_RSTIR)) {
1557 udc_ack_int_UDCCR(UDCCR_RSTIR);
1560 if ((readl(&dev->regs->udccr) & UDCCR_UDA) == 0) {
1561 debug("USB reset start\n");
1564 * reset driver and endpoints,
1565 * in case that's not yet done
1567 stop_activity(dev, dev->driver);
1570 debug("USB reset end\n");
1571 dev->gadget.speed = USB_SPEED_FULL;
1572 memset(&dev->stats, 0, sizeof dev->stats);
1573 /* driver and endpoints are still reset */
1577 u32 uicr0 = readl(&dev->regs->uicr0);
1578 u32 uicr1 = readl(&dev->regs->uicr1);
1579 u32 usir0 = readl(&dev->regs->usir0);
1580 u32 usir1 = readl(&dev->regs->usir1);
1582 usir0 = usir0 & ~uicr0;
1583 usir1 = usir1 & ~uicr1;
1586 if (unlikely(!usir0 && !usir1))
1589 debug_cond(NOISY, "irq %02x.%02x\n", usir1, usir0);
1591 /* control traffic */
1592 if (usir0 & USIR0_IR0) {
1593 dev->ep[0].pio_irqs++;
1598 /* endpoint data transfers */
1599 for (i = 0; i < 8; i++) {
1602 if (i && (usir0 & tmp)) {
1603 handle_ep(&dev->ep[i]);
1604 setbits_le32(&dev->regs->usir0, tmp);
1607 #ifndef CONFIG_USB_PXA25X_SMALL
1609 handle_ep(&dev->ep[i+8]);
1610 setbits_le32(&dev->regs->usir1, tmp);
1617 /* we could also ask for 1 msec SOF (SIR) interrupts */
1623 /*-------------------------------------------------------------------------*/
1626 * this uses load-time allocation and initialization (instead of
1627 * doing it at run-time) to save code, eliminate fault paths, and
1628 * be more obviously correct.
1630 static struct pxa25x_udc memory = {
1634 .ops = &pxa25x_udc_ops,
1635 .ep0 = &memory.ep[0].ep,
1636 .name = driver_name,
1639 /* control endpoint */
1643 .ops = &pxa25x_ep_ops,
1644 .maxpacket = EP0_FIFO_SIZE,
1647 .reg_udccs = &UDC_REGS->udccs[0],
1648 .reg_uddr = &UDC_REGS->uddr0,
1651 /* first group of endpoints */
1654 .name = "ep1in-bulk",
1655 .ops = &pxa25x_ep_ops,
1656 .maxpacket = BULK_FIFO_SIZE,
1659 .fifo_size = BULK_FIFO_SIZE,
1660 .bEndpointAddress = USB_DIR_IN | 1,
1661 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1662 .reg_udccs = &UDC_REGS->udccs[1],
1663 .reg_uddr = &UDC_REGS->uddr1,
1667 .name = "ep2out-bulk",
1668 .ops = &pxa25x_ep_ops,
1669 .maxpacket = BULK_FIFO_SIZE,
1672 .fifo_size = BULK_FIFO_SIZE,
1673 .bEndpointAddress = 2,
1674 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1675 .reg_udccs = &UDC_REGS->udccs[2],
1676 .reg_ubcr = &UDC_REGS->ubcr2,
1677 .reg_uddr = &UDC_REGS->uddr2,
1679 #ifndef CONFIG_USB_PXA25X_SMALL
1682 .name = "ep3in-iso",
1683 .ops = &pxa25x_ep_ops,
1684 .maxpacket = ISO_FIFO_SIZE,
1687 .fifo_size = ISO_FIFO_SIZE,
1688 .bEndpointAddress = USB_DIR_IN | 3,
1689 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1690 .reg_udccs = &UDC_REGS->udccs[3],
1691 .reg_uddr = &UDC_REGS->uddr3,
1695 .name = "ep4out-iso",
1696 .ops = &pxa25x_ep_ops,
1697 .maxpacket = ISO_FIFO_SIZE,
1700 .fifo_size = ISO_FIFO_SIZE,
1701 .bEndpointAddress = 4,
1702 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1703 .reg_udccs = &UDC_REGS->udccs[4],
1704 .reg_ubcr = &UDC_REGS->ubcr4,
1705 .reg_uddr = &UDC_REGS->uddr4,
1709 .name = "ep5in-int",
1710 .ops = &pxa25x_ep_ops,
1711 .maxpacket = INT_FIFO_SIZE,
1714 .fifo_size = INT_FIFO_SIZE,
1715 .bEndpointAddress = USB_DIR_IN | 5,
1716 .bmAttributes = USB_ENDPOINT_XFER_INT,
1717 .reg_udccs = &UDC_REGS->udccs[5],
1718 .reg_uddr = &UDC_REGS->uddr5,
1721 /* second group of endpoints */
1724 .name = "ep6in-bulk",
1725 .ops = &pxa25x_ep_ops,
1726 .maxpacket = BULK_FIFO_SIZE,
1729 .fifo_size = BULK_FIFO_SIZE,
1730 .bEndpointAddress = USB_DIR_IN | 6,
1731 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1732 .reg_udccs = &UDC_REGS->udccs[6],
1733 .reg_uddr = &UDC_REGS->uddr6,
1737 .name = "ep7out-bulk",
1738 .ops = &pxa25x_ep_ops,
1739 .maxpacket = BULK_FIFO_SIZE,
1742 .fifo_size = BULK_FIFO_SIZE,
1743 .bEndpointAddress = 7,
1744 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1745 .reg_udccs = &UDC_REGS->udccs[7],
1746 .reg_ubcr = &UDC_REGS->ubcr7,
1747 .reg_uddr = &UDC_REGS->uddr7,
1751 .name = "ep8in-iso",
1752 .ops = &pxa25x_ep_ops,
1753 .maxpacket = ISO_FIFO_SIZE,
1756 .fifo_size = ISO_FIFO_SIZE,
1757 .bEndpointAddress = USB_DIR_IN | 8,
1758 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1759 .reg_udccs = &UDC_REGS->udccs[8],
1760 .reg_uddr = &UDC_REGS->uddr8,
1764 .name = "ep9out-iso",
1765 .ops = &pxa25x_ep_ops,
1766 .maxpacket = ISO_FIFO_SIZE,
1769 .fifo_size = ISO_FIFO_SIZE,
1770 .bEndpointAddress = 9,
1771 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1772 .reg_udccs = &UDC_REGS->udccs[9],
1773 .reg_ubcr = &UDC_REGS->ubcr9,
1774 .reg_uddr = &UDC_REGS->uddr9,
1778 .name = "ep10in-int",
1779 .ops = &pxa25x_ep_ops,
1780 .maxpacket = INT_FIFO_SIZE,
1783 .fifo_size = INT_FIFO_SIZE,
1784 .bEndpointAddress = USB_DIR_IN | 10,
1785 .bmAttributes = USB_ENDPOINT_XFER_INT,
1786 .reg_udccs = &UDC_REGS->udccs[10],
1787 .reg_uddr = &UDC_REGS->uddr10,
1790 /* third group of endpoints */
1793 .name = "ep11in-bulk",
1794 .ops = &pxa25x_ep_ops,
1795 .maxpacket = BULK_FIFO_SIZE,
1798 .fifo_size = BULK_FIFO_SIZE,
1799 .bEndpointAddress = USB_DIR_IN | 11,
1800 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1801 .reg_udccs = &UDC_REGS->udccs[11],
1802 .reg_uddr = &UDC_REGS->uddr11,
1806 .name = "ep12out-bulk",
1807 .ops = &pxa25x_ep_ops,
1808 .maxpacket = BULK_FIFO_SIZE,
1811 .fifo_size = BULK_FIFO_SIZE,
1812 .bEndpointAddress = 12,
1813 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1814 .reg_udccs = &UDC_REGS->udccs[12],
1815 .reg_ubcr = &UDC_REGS->ubcr12,
1816 .reg_uddr = &UDC_REGS->uddr12,
1820 .name = "ep13in-iso",
1821 .ops = &pxa25x_ep_ops,
1822 .maxpacket = ISO_FIFO_SIZE,
1825 .fifo_size = ISO_FIFO_SIZE,
1826 .bEndpointAddress = USB_DIR_IN | 13,
1827 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1828 .reg_udccs = &UDC_REGS->udccs[13],
1829 .reg_uddr = &UDC_REGS->uddr13,
1833 .name = "ep14out-iso",
1834 .ops = &pxa25x_ep_ops,
1835 .maxpacket = ISO_FIFO_SIZE,
1838 .fifo_size = ISO_FIFO_SIZE,
1839 .bEndpointAddress = 14,
1840 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1841 .reg_udccs = &UDC_REGS->udccs[14],
1842 .reg_ubcr = &UDC_REGS->ubcr14,
1843 .reg_uddr = &UDC_REGS->uddr14,
1847 .name = "ep15in-int",
1848 .ops = &pxa25x_ep_ops,
1849 .maxpacket = INT_FIFO_SIZE,
1852 .fifo_size = INT_FIFO_SIZE,
1853 .bEndpointAddress = USB_DIR_IN | 15,
1854 .bmAttributes = USB_ENDPOINT_XFER_INT,
1855 .reg_udccs = &UDC_REGS->udccs[15],
1856 .reg_uddr = &UDC_REGS->uddr15,
1858 #endif /* !CONFIG_USB_PXA25X_SMALL */
1861 static void udc_command(int cmd)
1864 case PXA2XX_UDC_CMD_CONNECT:
1865 setbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
1866 GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
1869 writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
1870 GPCR(CONFIG_USB_DEV_PULLUP_GPIO));
1872 debug("Connected to USB\n");
1875 case PXA2XX_UDC_CMD_DISCONNECT:
1876 /* disable pullup resistor */
1877 writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
1878 GPSR(CONFIG_USB_DEV_PULLUP_GPIO));
1880 /* setup pin as input, line will float */
1881 clrbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
1882 GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
1884 debug("Disconnected from USB\n");
1889 static struct pxa2xx_udc_mach_info mach_info = {
1890 .udc_command = udc_command,
1894 * when a driver is successfully registered, it will receive
1895 * control requests including set_configuration(), which enables
1896 * non-control requests. then usb traffic follows until a
1897 * disconnect is reported. then a host may connect again, or
1898 * the driver might get unbound.
1900 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1902 struct pxa25x_udc *dev = &memory;
1907 || driver->speed < USB_SPEED_FULL
1908 || !driver->disconnect
1916 /* Enable clock for usb controller */
1917 setbits_le32(CKEN, CKEN11_USB);
1919 /* first hook up the driver ... */
1920 dev->driver = driver;
1923 /* trigger chiprev-specific logic */
1924 switch ((chiprev = pxa_get_cpu_revision())) {
1930 /* A0/A1 "not released"; ep 13, 15 unusable */
1932 case PXA250_B2: case PXA210_B2:
1933 case PXA250_B1: case PXA210_B1:
1934 case PXA250_B0: case PXA210_B0:
1935 /* OUT-DMA is broken ... */
1937 case PXA250_C0: case PXA210_C0:
1940 printf("%s: unrecognized processor: %08x\n",
1941 DRIVER_NAME, chiprev);
1945 the_controller = dev;
1947 /* prepare watchdog timer */
1948 dev->watchdog.running = 0;
1949 dev->watchdog.period = 5000 * CONFIG_SYS_HZ / 1000000; /* 5 ms */
1950 dev->watchdog.function = udc_watchdog;
1952 dev->mach = &mach_info;
1957 dev->gadget.name = "pxa2xx_udc";
1958 retval = driver->bind(&dev->gadget);
1960 printf("bind to driver %s --> error %d\n",
1961 DRIVER_NAME, retval);
1967 * ... then enable host detection and ep0; and we're ready
1968 * for set_configuration as well as eventual disconnect.
1970 printf("registered gadget driver '%s'\n", DRIVER_NAME);
1978 stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
1982 /* don't disconnect drivers more than once */
1983 if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1985 dev->gadget.speed = USB_SPEED_UNKNOWN;
1987 /* prevent new request submissions, kill any outstanding requests */
1988 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1989 struct pxa25x_ep *ep = &dev->ep[i];
1992 nuke(ep, -ESHUTDOWN);
1996 /* report disconnect; the driver is already quiesced */
1998 driver->disconnect(&dev->gadget);
2000 /* re-init driver-visible data structures */
2004 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2006 struct pxa25x_udc *dev = the_controller;
2010 if (!driver || driver != dev->driver || !driver->unbind)
2013 local_irq_disable();
2016 stop_activity(dev, driver);
2019 driver->unbind(&dev->gadget);
2022 printf("unregistered gadget driver '%s'\n", DRIVER_NAME);
2025 the_controller = NULL;
2027 clrbits_le32(CKEN, CKEN11_USB);
2032 extern void udc_disconnect(void)
2034 setbits_le32(CKEN, CKEN11_USB);
2035 udc_clear_mask_UDCCR(UDCCR_UDE);
2036 udc_command(PXA2XX_UDC_CMD_DISCONNECT);
2037 clrbits_le32(CKEN, CKEN11_USB);
2040 /*-------------------------------------------------------------------------*/
2043 usb_gadget_handle_interrupts(int index)
2045 return pxa25x_udc_irq();