drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
   4  * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
   5  *
   6  * Copyright (C) 2009 for Samsung Electronics
   7  *
   8  * BSP Support for Samsung's UDC driver
   9  * available at:
  10  * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  11  *
  12  * State machine bugfixes:
  13  * Marek Szyprowski <m.szyprowski@samsung.com>
  14  *
  15  * Ported to u-boot:
  16  * Marek Szyprowski <m.szyprowski@samsung.com>
  17  * Lukasz Majewski <l.majewski@samsumg.com>
  18  */
  19
  20 static u8 clear_feature_num;
  21 int clear_feature_flag;
  22
  23 /* Bulk-Only Mass Storage Reset (class-specific request) */
  24 #define GET_MAX_LUN_REQUEST     0xFE
  25 #define BOT_RESET_REQUEST       0xFF
  26
  27 static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev)
  28 {
  29         u32 ep_ctrl;
  30
  31         writel(usb_ctrl_dma_addr, &reg->in_endp[EP0_CON].diepdma);
  32         writel(DIEPT_SIZ_PKT_CNT(1), &reg->in_endp[EP0_CON].dieptsiz);
  33
  34         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  35         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
  36                &reg->in_endp[EP0_CON].diepctl);
  37
  38         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  39                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  40         dev->ep0state = WAIT_FOR_IN_COMPLETE;
  41 }
  42
  43 static void dwc2_udc_pre_setup(void)
  44 {
  45         u32 ep_ctrl;
  46
  47         debug_cond(DEBUG_IN_EP,
  48                    "%s : Prepare Setup packets.\n", __func__);
  49
  50         writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
  51                &reg->out_endp[EP0_CON].doeptsiz);
  52         writel(usb_ctrl_dma_addr, &reg->out_endp[EP0_CON].doepdma);
  53
  54         ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  55         writel(ep_ctrl|DEPCTL_EPENA, &reg->out_endp[EP0_CON].doepctl);
  56
  57         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  58                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  59         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  60                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  61
  62 }
  63
  64 static inline void dwc2_ep0_complete_out(void)
  65 {
  66         u32 ep_ctrl;
  67
  68         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  69                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  70         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  71                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  72
  73         debug_cond(DEBUG_IN_EP,
  74                 "%s : Prepare Complete Out packet.\n", __func__);
  75
  76         writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
  77                &reg->out_endp[EP0_CON].doeptsiz);
  78         writel(usb_ctrl_dma_addr, &reg->out_endp[EP0_CON].doepdma);
  79
  80         ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  81         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
  82                &reg->out_endp[EP0_CON].doepctl);
  83
  84         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  85                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  86         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  87                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  88
  89 }
  90
  91
  92 static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req)
  93 {
  94         u32 *buf, ctrl;
  95         u32 length, pktcnt;
  96         u32 ep_num = ep_index(ep);
  97
  98         buf = req->req.buf + req->req.actual;
  99         length = min_t(u32, req->req.length - req->req.actual,
 100                        ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket);
 101
 102         ep->len = length;
 103         ep->dma_buf = buf;
 104
 105         if (ep_num == EP0_CON || length == 0)
 106                 pktcnt = 1;
 107         else
 108                 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
 109
 110         ctrl =  readl(&reg->out_endp[ep_num].doepctl);
 111
 112         invalidate_dcache_range((unsigned long) ep->dma_buf,
 113                                 (unsigned long) ep->dma_buf +
 114                                 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
 115
 116         writel((unsigned long) ep->dma_buf, &reg->out_endp[ep_num].doepdma);
 117         writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
 118                &reg->out_endp[ep_num].doeptsiz);
 119         writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->out_endp[ep_num].doepctl);
 120
 121         debug_cond(DEBUG_OUT_EP != 0,
 122                    "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
 123                    "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
 124                    "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
 125                    __func__, ep_num,
 126                    readl(&reg->out_endp[ep_num].doepdma),
 127                    readl(&reg->out_endp[ep_num].doeptsiz),
 128                    readl(&reg->out_endp[ep_num].doepctl),
 129                    buf, pktcnt, length);
 130         return 0;
 131
 132 }
 133
 134 static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req)
 135 {
 136         u32 *buf, ctrl = 0;
 137         u32 length, pktcnt;
 138         u32 ep_num = ep_index(ep);
 139
 140         buf = req->req.buf + req->req.actual;
 141         length = req->req.length - req->req.actual;
 142
 143         if (ep_num == EP0_CON)
 144                 length = min(length, (u32)ep_maxpacket(ep));
 145
 146         ep->len = length;
 147         ep->dma_buf = buf;
 148
 149         flush_dcache_range((unsigned long) ep->dma_buf,
 150                            (unsigned long) ep->dma_buf +
 151                            ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
 152
 153         if (length == 0)
 154                 pktcnt = 1;
 155         else
 156                 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
 157
 158         /* Flush the endpoint's Tx FIFO */
 159         writel(TX_FIFO_NUMBER(ep->fifo_num), &reg->grstctl);
 160         writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, &reg->grstctl);
 161         while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
 162                 ;
 163
 164         writel((unsigned long) ep->dma_buf, &reg->in_endp[ep_num].diepdma);
 165         writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
 166                &reg->in_endp[ep_num].dieptsiz);
 167
 168         ctrl = readl(&reg->in_endp[ep_num].diepctl);
 169
 170         /* Write the FIFO number to be used for this endpoint */
 171         ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
 172         ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
 173
 174         /* Clear reserved (Next EP) bits */
 175         ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
 176
 177         writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->in_endp[ep_num].diepctl);
 178
 179         debug_cond(DEBUG_IN_EP,
 180                 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
 181                 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
 182                 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
 183                 __func__, ep_num,
 184                 readl(&reg->in_endp[ep_num].diepdma),
 185                 readl(&reg->in_endp[ep_num].dieptsiz),
 186                 readl(&reg->in_endp[ep_num].diepctl),
 187                 buf, pktcnt, length);
 188
 189         return length;
 190 }
 191
 192 static void complete_rx(struct dwc2_udc *dev, u8 ep_num)
 193 {
 194         struct dwc2_ep *ep = &dev->ep[ep_num];
 195         struct dwc2_request *req = NULL;
 196         u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
 197
 198         if (list_empty(&ep->queue)) {
 199                 debug_cond(DEBUG_OUT_EP != 0,
 200                            "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
 201                            __func__, ep_num);
 202                 return;
 203
 204         }
 205
 206         req = list_entry(ep->queue.next, struct dwc2_request, queue);
 207         ep_tsr = readl(&reg->out_endp[ep_num].doeptsiz);
 208
 209         if (ep_num == EP0_CON)
 210                 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
 211         else
 212                 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
 213
 214         xfer_size = ep->len - xfer_size;
 215
 216         /*
 217          * NOTE:
 218          *
 219          * Please be careful with proper buffer allocation for USB request,
 220          * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only
 221          * with starting address, but also its size shall be a cache line
 222          * multiplication.
 223          *
 224          * This will prevent from corruption of data allocated immediatelly
 225          * before or after the buffer.
 226          *
 227          * For armv7, the cache_v7.c provides proper code to emit "ERROR"
 228          * message to warn users.
 229          */
 230         invalidate_dcache_range((unsigned long) ep->dma_buf,
 231                                 (unsigned long) ep->dma_buf +
 232                                 ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE));
 233
 234         req->req.actual += min(xfer_size, req->req.length - req->req.actual);
 235         is_short = !!(xfer_size % ep->ep.maxpacket);
 236
 237         debug_cond(DEBUG_OUT_EP != 0,
 238                    "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
 239                    "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
 240                    __func__, ep_num, req->req.actual, req->req.length,
 241                    is_short, ep_tsr, req->req.length - req->req.actual);
 242
 243         if (is_short || req->req.actual == req->req.length) {
 244                 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
 245                         debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
 246                         dwc2_udc_ep0_zlp(dev);
 247                         /* packet will be completed in complete_tx() */
 248                         dev->ep0state = WAIT_FOR_IN_COMPLETE;
 249                 } else {
 250                         done(ep, req, 0);
 251
 252                         if (!list_empty(&ep->queue)) {
 253                                 req = list_entry(ep->queue.next,
 254                                         struct dwc2_request, queue);
 255                                 debug_cond(DEBUG_OUT_EP != 0,
 256                                            "%s: Next Rx request start...\n",
 257                                            __func__);
 258                                 setdma_rx(ep, req);
 259                         }
 260                 }
 261         } else
 262                 setdma_rx(ep, req);
 263 }
 264
 265 static void complete_tx(struct dwc2_udc *dev, u8 ep_num)
 266 {
 267         struct dwc2_ep *ep = &dev->ep[ep_num];
 268         struct dwc2_request *req;
 269         u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
 270         u32 last;
 271
 272         if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
 273                 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
 274                 dwc2_ep0_complete_out();
 275                 return;
 276         }
 277
 278         if (list_empty(&ep->queue)) {
 279                 debug_cond(DEBUG_IN_EP,
 280                         "%s: TX DMA done : NULL REQ on IN EP-%d\n",
 281                         __func__, ep_num);
 282                 return;
 283
 284         }
 285
 286         req = list_entry(ep->queue.next, struct dwc2_request, queue);
 287
 288         ep_tsr = readl(&reg->in_endp[ep_num].dieptsiz);
 289
 290         xfer_size = ep->len;
 291         is_short = (xfer_size < ep->ep.maxpacket);
 292         req->req.actual += min(xfer_size, req->req.length - req->req.actual);
 293
 294         debug_cond(DEBUG_IN_EP,
 295                 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
 296                 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
 297                 __func__, ep_num, req->req.actual, req->req.length,
 298                 is_short, ep_tsr, req->req.length - req->req.actual);
 299
 300         if (ep_num == 0) {
 301                 if (dev->ep0state == DATA_STATE_XMIT) {
 302                         debug_cond(DEBUG_IN_EP,
 303                                 "%s: ep_num = %d, ep0stat =="
 304                                 "DATA_STATE_XMIT\n",
 305                                 __func__, ep_num);
 306                         last = write_fifo_ep0(ep, req);
 307                         if (last)
 308                                 dev->ep0state = WAIT_FOR_COMPLETE;
 309                 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
 310                         debug_cond(DEBUG_IN_EP,
 311                                 "%s: ep_num = %d, completing request\n",
 312                                 __func__, ep_num);
 313                         done(ep, req, 0);
 314                         dev->ep0state = WAIT_FOR_SETUP;
 315                 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
 316                         debug_cond(DEBUG_IN_EP,
 317                                 "%s: ep_num = %d, completing request\n",
 318                                 __func__, ep_num);
 319                         done(ep, req, 0);
 320                         dev->ep0state = WAIT_FOR_OUT_COMPLETE;
 321                         dwc2_ep0_complete_out();
 322                 } else {
 323                         debug_cond(DEBUG_IN_EP,
 324                                 "%s: ep_num = %d, invalid ep state\n",
 325                                 __func__, ep_num);
 326                 }
 327                 return;
 328         }
 329
 330         if (req->req.actual == req->req.length)
 331                 done(ep, req, 0);
 332
 333         if (!list_empty(&ep->queue)) {
 334                 req = list_entry(ep->queue.next, struct dwc2_request, queue);
 335                 debug_cond(DEBUG_IN_EP,
 336                         "%s: Next Tx request start...\n", __func__);
 337                 setdma_tx(ep, req);
 338         }
 339 }
 340
 341 static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num)
 342 {
 343         struct dwc2_ep *ep = &dev->ep[ep_num];
 344         struct dwc2_request *req;
 345
 346         debug_cond(DEBUG_IN_EP,
 347                 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
 348
 349         if (!list_empty(&ep->queue)) {
 350                 req = list_entry(ep->queue.next, struct dwc2_request, queue);
 351                 debug_cond(DEBUG_IN_EP,
 352                         "%s: Next Tx request(0x%p) start...\n",
 353                         __func__, req);
 354
 355                 if (ep_is_in(ep))
 356                         setdma_tx(ep, req);
 357                 else
 358                         setdma_rx(ep, req);
 359         } else {
 360                 debug_cond(DEBUG_IN_EP,
 361                         "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
 362
 363                 return;
 364         }
 365
 366 }
 367
 368 static void process_ep_in_intr(struct dwc2_udc *dev)
 369 {
 370         u32 ep_intr, ep_intr_status;
 371         u8 ep_num = 0;
 372
 373         ep_intr = readl(&reg->daint);
 374         debug_cond(DEBUG_IN_EP,
 375                 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
 376
 377         ep_intr &= DAINT_MASK;
 378
 379         while (ep_intr) {
 380                 if (ep_intr & DAINT_IN_EP_INT(1)) {
 381                         ep_intr_status = readl(&reg->in_endp[ep_num].diepint);
 382                         debug_cond(DEBUG_IN_EP,
 383                                    "\tEP%d-IN : DIEPINT = 0x%x\n",
 384                                    ep_num, ep_intr_status);
 385
 386                         /* Interrupt Clear */
 387                         writel(ep_intr_status, &reg->in_endp[ep_num].diepint);
 388
 389                         if (ep_intr_status & TRANSFER_DONE) {
 390                                 complete_tx(dev, ep_num);
 391
 392                                 if (ep_num == 0) {
 393                                         if (dev->ep0state ==
 394                                             WAIT_FOR_IN_COMPLETE)
 395                                                 dev->ep0state = WAIT_FOR_SETUP;
 396
 397                                         if (dev->ep0state == WAIT_FOR_SETUP)
 398                                                 dwc2_udc_pre_setup();
 399
 400                                         /* continue transfer after
 401                                            set_clear_halt for DMA mode */
 402                                         if (clear_feature_flag == 1) {
 403                                                 dwc2_udc_check_tx_queue(dev,
 404                                                         clear_feature_num);
 405                                                 clear_feature_flag = 0;
 406                                         }
 407                                 }
 408                         }
 409                 }
 410                 ep_num++;
 411                 ep_intr >>= 1;
 412         }
 413 }
 414
 415 static void process_ep_out_intr(struct dwc2_udc *dev)
 416 {
 417         u32 ep_intr, ep_intr_status;
 418         u8 ep_num = 0;
 419
 420         ep_intr = readl(&reg->daint);
 421         debug_cond(DEBUG_OUT_EP != 0,
 422                    "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
 423                    __func__, ep_intr);
 424
 425         ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
 426
 427         while (ep_intr) {
 428                 if (ep_intr & 0x1) {
 429                         ep_intr_status = readl(&reg->out_endp[ep_num].doepint);
 430                         debug_cond(DEBUG_OUT_EP != 0,
 431                                    "\tEP%d-OUT : DOEPINT = 0x%x\n",
 432                                    ep_num, ep_intr_status);
 433
 434                         /* Interrupt Clear */
 435                         writel(ep_intr_status, &reg->out_endp[ep_num].doepint);
 436
 437                         if (ep_num == 0) {
 438                                 if (ep_intr_status & TRANSFER_DONE) {
 439                                         if (dev->ep0state !=
 440                                             WAIT_FOR_OUT_COMPLETE)
 441                                                 complete_rx(dev, ep_num);
 442                                         else {
 443                                                 dev->ep0state = WAIT_FOR_SETUP;
 444                                                 dwc2_udc_pre_setup();
 445                                         }
 446                                 }
 447
 448                                 if (ep_intr_status &
 449                                     CTRL_OUT_EP_SETUP_PHASE_DONE) {
 450                                         debug_cond(DEBUG_OUT_EP != 0,
 451                                                    "SETUP packet arrived\n");
 452                                         dwc2_handle_ep0(dev);
 453                                 }
 454                         } else {
 455                                 if (ep_intr_status & TRANSFER_DONE)
 456                                         complete_rx(dev, ep_num);
 457                         }
 458                 }
 459                 ep_num++;
 460                 ep_intr >>= 1;
 461         }
 462 }
 463
 464 /*
 465  *      usb client interrupt handler.
 466  */
 467 static int dwc2_udc_irq(int irq, void *_dev)
 468 {
 469         struct dwc2_udc *dev = _dev;
 470         u32 intr_status, gotgint;
 471         u32 usb_status, gintmsk;
 472         unsigned long flags = 0;
 473
 474         spin_lock_irqsave(&dev->lock, flags);
 475
 476         intr_status = readl(&reg->gintsts);
 477         gintmsk = readl(&reg->gintmsk);
 478
 479         debug_cond(DEBUG_ISR,
 480                   "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
 481                   "DAINT : 0x%x, DAINTMSK : 0x%x\n",
 482                   __func__, intr_status, state_names[dev->ep0state], gintmsk,
 483                   readl(&reg->daint), readl(&reg->daintmsk));
 484
 485         if (!intr_status) {
 486                 spin_unlock_irqrestore(&dev->lock, flags);
 487                 return IRQ_HANDLED;
 488         }
 489
 490         if (intr_status & INT_ENUMDONE) {
 491                 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
 492
 493                 writel(INT_ENUMDONE, &reg->gintsts);
 494                 usb_status = (readl(&reg->dsts) & 0x6);
 495
 496                 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
 497                         debug_cond(DEBUG_ISR,
 498                                    "\t\tFull Speed Detection\n");
 499                         set_max_pktsize(dev, USB_SPEED_FULL);
 500
 501                 } else {
 502                         debug_cond(DEBUG_ISR,
 503                                 "\t\tHigh Speed Detection : 0x%x\n",
 504                                 usb_status);
 505                         set_max_pktsize(dev, USB_SPEED_HIGH);
 506                 }
 507         }
 508
 509         if (intr_status & INT_EARLY_SUSPEND) {
 510                 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
 511                 writel(INT_EARLY_SUSPEND, &reg->gintsts);
 512         }
 513
 514         if (intr_status & INT_SUSPEND) {
 515                 usb_status = readl(&reg->dsts);
 516                 debug_cond(DEBUG_ISR,
 517                         "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
 518                 writel(INT_SUSPEND, &reg->gintsts);
 519
 520                 if (dev->gadget.speed != USB_SPEED_UNKNOWN
 521                     && dev->driver) {
 522                         if (dev->driver->suspend)
 523                                 dev->driver->suspend(&dev->gadget);
 524                 }
 525         }
 526
 527         if (intr_status & INT_OTG) {
 528                 gotgint = readl(&reg->gotgint);
 529                 debug_cond(DEBUG_ISR,
 530                            "\tOTG interrupt: (GOTGINT):0x%x\n", gotgint);
 531
 532                 if (gotgint & GOTGINT_SES_END_DET) {
 533                         debug_cond(DEBUG_ISR, "\t\tSession End Detected\n");
 534                         /* Let gadget detect disconnected state */
 535                         if (dev->driver->disconnect) {
 536                                 spin_unlock_irqrestore(&dev->lock, flags);
 537                                 dev->driver->disconnect(&dev->gadget);
 538                                 spin_lock_irqsave(&dev->lock, flags);
 539                         }
 540                 }
 541                 writel(gotgint, &reg->gotgint);
 542         }
 543
 544         if (intr_status & INT_RESUME) {
 545                 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
 546                 writel(INT_RESUME, &reg->gintsts);
 547
 548                 if (dev->gadget.speed != USB_SPEED_UNKNOWN
 549                     && dev->driver
 550                     && dev->driver->resume) {
 551
 552                         dev->driver->resume(&dev->gadget);
 553                 }
 554         }
 555
 556         if (intr_status & INT_RESET) {
 557                 usb_status = readl(&reg->gotgctl);
 558                 debug_cond(DEBUG_ISR,
 559                         "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
 560                 writel(INT_RESET, &reg->gintsts);
 561
 562                 if ((usb_status & 0xc0000) == (0x3 << 18)) {
 563                         if (reset_available) {
 564                                 debug_cond(DEBUG_ISR,
 565                                         "\t\tOTG core got reset (%d)!!\n",
 566                                         reset_available);
 567                                 reconfig_usbd(dev);
 568                                 dev->ep0state = WAIT_FOR_SETUP;
 569                                 reset_available = 0;
 570                                 dwc2_udc_pre_setup();
 571                         } else
 572                                 reset_available = 1;
 573
 574                 } else {
 575                         reset_available = 1;
 576                         debug_cond(DEBUG_ISR,
 577                                    "\t\tRESET handling skipped\n");
 578                 }
 579         }
 580
 581         if (intr_status & INT_IN_EP)
 582                 process_ep_in_intr(dev);
 583
 584         if (intr_status & INT_OUT_EP)
 585                 process_ep_out_intr(dev);
 586
 587         spin_unlock_irqrestore(&dev->lock, flags);
 588
 589         return IRQ_HANDLED;
 590 }
 591
 592 /** Queue one request
 593  *  Kickstart transfer if needed
 594  */
 595 static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req,
 596                          gfp_t gfp_flags)
 597 {
 598         struct dwc2_request *req;
 599         struct dwc2_ep *ep;
 600         struct dwc2_udc *dev;
 601         unsigned long flags = 0;
 602         u32 ep_num, gintsts;
 603
 604         req = container_of(_req, struct dwc2_request, req);
 605         if (unlikely(!_req || !_req->complete || !_req->buf
 606                      || !list_empty(&req->queue))) {
 607
 608                 debug("%s: bad params\n", __func__);
 609                 return -EINVAL;
 610         }
 611
 612         ep = container_of(_ep, struct dwc2_ep, ep);
 613
 614         if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
 615
 616                 debug("%s: bad ep: %s, %d, %p\n", __func__,
 617                       ep->ep.name, !ep->desc, _ep);
 618                 return -EINVAL;
 619         }
 620
 621         ep_num = ep_index(ep);
 622         dev = ep->dev;
 623         if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 624
 625                 debug("%s: bogus device state %p\n", __func__, dev->driver);
 626                 return -ESHUTDOWN;
 627         }
 628
 629         spin_lock_irqsave(&dev->lock, flags);
 630
 631         _req->status = -EINPROGRESS;
 632         _req->actual = 0;
 633
 634         /* kickstart this i/o queue? */
 635         debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
 636                 "Q empty = %d, stopped = %d\n",
 637                 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
 638                 _req, _req->length, _req->buf,
 639                 list_empty(&ep->queue), ep->stopped);
 640
 641 #ifdef DEBUG
 642         {
 643                 int i, len = _req->length;
 644
 645                 printf("pkt = ");
 646                 if (len > 64)
 647                         len = 64;
 648                 for (i = 0; i < len; i++) {
 649                         printf("%02x", ((u8 *)_req->buf)[i]);
 650                         if ((i & 7) == 7)
 651                                 printf(" ");
 652                 }
 653                 printf("\n");
 654         }
 655 #endif
 656
 657         if (list_empty(&ep->queue) && !ep->stopped) {
 658
 659                 if (ep_num == 0) {
 660                         /* EP0 */
 661                         list_add_tail(&req->queue, &ep->queue);
 662                         dwc2_ep0_kick(dev, ep);
 663                         req = 0;
 664
 665                 } else if (ep_is_in(ep)) {
 666                         gintsts = readl(&reg->gintsts);
 667                         debug_cond(DEBUG_IN_EP,
 668                                    "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n",
 669                                    __func__, gintsts);
 670
 671                         setdma_tx(ep, req);
 672                 } else {
 673                         gintsts = readl(&reg->gintsts);
 674                         debug_cond(DEBUG_OUT_EP != 0,
 675                                    "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n",
 676                                    __func__, gintsts);
 677
 678                         setdma_rx(ep, req);
 679                 }
 680         }
 681
 682         /* pio or dma irq handler advances the queue. */
 683         if (likely(req != 0))
 684                 list_add_tail(&req->queue, &ep->queue);
 685
 686         spin_unlock_irqrestore(&dev->lock, flags);
 687
 688         return 0;
 689 }
 690
 691 /****************************************************************/
 692 /* End Point 0 related functions                                */
 693 /****************************************************************/
 694
 695 /* return:  0 = still running, 1 = completed, negative = errno */
 696 static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req)
 697 {
 698         u32 max;
 699         unsigned count;
 700         int is_last;
 701
 702         max = ep_maxpacket(ep);
 703
 704         debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
 705
 706         count = setdma_tx(ep, req);
 707
 708         /* last packet is usually short (or a zlp) */
 709         if (likely(count != max))
 710                 is_last = 1;
 711         else {
 712                 if (likely(req->req.length != req->req.actual + count)
 713                     || req->req.zero)
 714                         is_last = 0;
 715                 else
 716                         is_last = 1;
 717         }
 718
 719         debug_cond(DEBUG_EP0 != 0,
 720                    "%s: wrote %s %d bytes%s %d left %p\n", __func__,
 721                    ep->ep.name, count,
 722                    is_last ? "/L" : "",
 723                    req->req.length - req->req.actual - count, req);
 724
 725         /* requests complete when all IN data is in the FIFO */
 726         if (is_last) {
 727                 ep->dev->ep0state = WAIT_FOR_SETUP;
 728                 return 1;
 729         }
 730
 731         return 0;
 732 }
 733
 734 static int dwc2_fifo_read(struct dwc2_ep *ep, void *cp, int max)
 735 {
 736         invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
 737                                 ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
 738
 739         debug_cond(DEBUG_EP0 != 0,
 740                    "%s: bytes=%d, ep_index=%d 0x%p\n", __func__,
 741                    max, ep_index(ep), cp);
 742
 743         return max;
 744 }
 745
 746 /**
 747  * udc_set_address - set the USB address for this device
 748  * @address:
 749  *
 750  * Called from control endpoint function
 751  * after it decodes a set address setup packet.
 752  */
 753 static void udc_set_address(struct dwc2_udc *dev, unsigned char address)
 754 {
 755         u32 ctrl = readl(&reg->dcfg);
 756         writel(DEVICE_ADDRESS(address) | ctrl, &reg->dcfg);
 757
 758         dwc2_udc_ep0_zlp(dev);
 759
 760         debug_cond(DEBUG_EP0 != 0,
 761                    "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
 762                    __func__, address, readl(&reg->dcfg));
 763
 764         dev->usb_address = address;
 765 }
 766
 767 static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep)
 768 {
 769         struct dwc2_udc *dev;
 770         u32             ep_ctrl = 0;
 771
 772         dev = ep->dev;
 773         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
 774
 775         /* set the disable and stall bits */
 776         if (ep_ctrl & DEPCTL_EPENA)
 777                 ep_ctrl |= DEPCTL_EPDIS;
 778
 779         ep_ctrl |= DEPCTL_STALL;
 780
 781         writel(ep_ctrl, &reg->in_endp[EP0_CON].diepctl);
 782
 783         debug_cond(DEBUG_EP0 != 0,
 784                    "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
 785                    __func__, ep_index(ep), &reg->in_endp[EP0_CON].diepctl);
 786         /*
 787          * The application can only set this bit, and the core clears it,
 788          * when a SETUP token is received for this endpoint
 789          */
 790         dev->ep0state = WAIT_FOR_SETUP;
 791
 792         dwc2_udc_pre_setup();
 793 }
 794
 795 static void dwc2_ep0_read(struct dwc2_udc *dev)
 796 {
 797         struct dwc2_request *req;
 798         struct dwc2_ep *ep = &dev->ep[0];
 799
 800         if (!list_empty(&ep->queue)) {
 801                 req = list_entry(ep->queue.next, struct dwc2_request, queue);
 802
 803         } else {
 804                 debug("%s: ---> BUG\n", __func__);
 805                 BUG();
 806                 return;
 807         }
 808
 809         debug_cond(DEBUG_EP0 != 0,
 810                    "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
 811                    __func__, req, req->req.length, req->req.actual);
 812
 813         if (req->req.length == 0) {
 814                 /* zlp for Set_configuration, Set_interface,
 815                  * or Bulk-Only mass storge reset */
 816
 817                 ep->len = 0;
 818                 dwc2_udc_ep0_zlp(dev);
 819
 820                 debug_cond(DEBUG_EP0 != 0,
 821                            "%s: req.length = 0, bRequest = %d\n",
 822                            __func__, usb_ctrl->bRequest);
 823                 return;
 824         }
 825
 826         setdma_rx(ep, req);
 827 }
 828
 829 /*
 830  * DATA_STATE_XMIT
 831  */
 832 static int dwc2_ep0_write(struct dwc2_udc *dev)
 833 {
 834         struct dwc2_request *req;
 835         struct dwc2_ep *ep = &dev->ep[0];
 836         int ret, need_zlp = 0;
 837
 838         if (list_empty(&ep->queue))
 839                 req = 0;
 840         else
 841                 req = list_entry(ep->queue.next, struct dwc2_request, queue);
 842
 843         if (!req) {
 844                 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
 845                 return 0;
 846         }
 847
 848         debug_cond(DEBUG_EP0 != 0,
 849                    "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
 850                    __func__, req, req->req.length, req->req.actual);
 851
 852         if (req->req.length - req->req.actual == ep0_fifo_size) {
 853                 /* Next write will end with the packet size, */
 854                 /* so we need Zero-length-packet */
 855                 need_zlp = 1;
 856         }
 857
 858         ret = write_fifo_ep0(ep, req);
 859
 860         if ((ret == 1) && !need_zlp) {
 861                 /* Last packet */
 862                 dev->ep0state = WAIT_FOR_COMPLETE;
 863                 debug_cond(DEBUG_EP0 != 0,
 864                            "%s: finished, waiting for status\n", __func__);
 865
 866         } else {
 867                 dev->ep0state = DATA_STATE_XMIT;
 868                 debug_cond(DEBUG_EP0 != 0,
 869                            "%s: not finished\n", __func__);
 870         }
 871
 872         return 1;
 873 }
 874
 875 static int dwc2_udc_get_status(struct dwc2_udc *dev,
 876                 struct usb_ctrlrequest *crq)
 877 {
 878         u8 ep_num = crq->wIndex & 0x7F;
 879         u16 g_status = 0;
 880         u32 ep_ctrl;
 881
 882         debug_cond(DEBUG_SETUP != 0,
 883                    "%s: *** USB_REQ_GET_STATUS\n", __func__);
 884         printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
 885         switch (crq->bRequestType & USB_RECIP_MASK) {
 886         case USB_RECIP_INTERFACE:
 887                 g_status = 0;
 888                 debug_cond(DEBUG_SETUP != 0,
 889                            "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
 890                            g_status);
 891                 break;
 892
 893         case USB_RECIP_DEVICE:
 894                 g_status = 0x1; /* Self powered */
 895                 debug_cond(DEBUG_SETUP != 0,
 896                            "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
 897                            g_status);
 898                 break;
 899
 900         case USB_RECIP_ENDPOINT:
 901                 if (crq->wLength > 2) {
 902                         debug_cond(DEBUG_SETUP != 0,
 903                                    "\tGET_STATUS:Not support EP or wLength\n");
 904                         return 1;
 905                 }
 906
 907                 g_status = dev->ep[ep_num].stopped;
 908                 debug_cond(DEBUG_SETUP != 0,
 909                            "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
 910                            g_status);
 911
 912                 break;
 913
 914         default:
 915                 return 1;
 916         }
 917
 918         memcpy(usb_ctrl, &g_status, sizeof(g_status));
 919
 920         flush_dcache_range((unsigned long) usb_ctrl,
 921                            (unsigned long) usb_ctrl +
 922                            ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
 923
 924         writel(usb_ctrl_dma_addr, &reg->in_endp[EP0_CON].diepdma);
 925         writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
 926                &reg->in_endp[EP0_CON].dieptsiz);
 927
 928         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
 929         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
 930                &reg->in_endp[EP0_CON].diepctl);
 931         dev->ep0state = WAIT_FOR_NULL_COMPLETE;
 932
 933         return 0;
 934 }
 935
 936 static void dwc2_udc_set_nak(struct dwc2_ep *ep)
 937 {
 938         u8              ep_num;
 939         u32             ep_ctrl = 0;
 940
 941         ep_num = ep_index(ep);
 942         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
 943
 944         if (ep_is_in(ep)) {
 945                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
 946                 ep_ctrl |= DEPCTL_SNAK;
 947                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
 948                 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
 949                         __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
 950         } else {
 951                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
 952                 ep_ctrl |= DEPCTL_SNAK;
 953                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
 954                 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
 955                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
 956         }
 957
 958         return;
 959 }
 960
 961
 962 static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep)
 963 {
 964         u8              ep_num;
 965         u32             ep_ctrl = 0;
 966
 967         ep_num = ep_index(ep);
 968         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
 969
 970         if (ep_is_in(ep)) {
 971                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
 972
 973                 /* set the disable and stall bits */
 974                 if (ep_ctrl & DEPCTL_EPENA)
 975                         ep_ctrl |= DEPCTL_EPDIS;
 976
 977                 ep_ctrl |= DEPCTL_STALL;
 978
 979                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
 980                 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
 981                       __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
 982
 983         } else {
 984                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
 985
 986                 /* set the stall bit */
 987                 ep_ctrl |= DEPCTL_STALL;
 988
 989                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
 990                 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
 991                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
 992         }
 993
 994         return;
 995 }
 996
 997 static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep)
 998 {
 999         u8              ep_num;
1000         u32             ep_ctrl = 0;
1001
1002         ep_num = ep_index(ep);
1003         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
1004
1005         if (ep_is_in(ep)) {
1006                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
1007
1008                 /* clear stall bit */
1009                 ep_ctrl &= ~DEPCTL_STALL;
1010
1011                 /*
1012                  * USB Spec 9.4.5: For endpoints using data toggle, regardless
1013                  * of whether an endpoint has the Halt feature set, a
1014                  * ClearFeature(ENDPOINT_HALT) request always results in the
1015                  * data toggle being reinitialized to DATA0.
1016                  */
1017                 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1018                     || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1019                         ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1020                 }
1021
1022                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
1023                 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1024                         __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
1025
1026         } else {
1027                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
1028
1029                 /* clear stall bit */
1030                 ep_ctrl &= ~DEPCTL_STALL;
1031
1032                 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1033                     || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1034                         ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1035                 }
1036
1037                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1038                 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1039                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
1040         }
1041
1042         return;
1043 }
1044
1045 static int dwc2_udc_set_halt(struct usb_ep *_ep, int value)
1046 {
1047         struct dwc2_ep  *ep;
1048         struct dwc2_udc *dev;
1049         unsigned long   flags = 0;
1050         u8              ep_num;
1051
1052         ep = container_of(_ep, struct dwc2_ep, ep);
1053         ep_num = ep_index(ep);
1054
1055         if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1056                      ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1057                 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1058                 return -EINVAL;
1059         }
1060
1061         /* Attempt to halt IN ep will fail if any transfer requests
1062          * are still queue */
1063         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1064                 debug("%s: %s queue not empty, req = %p\n",
1065                         __func__, ep->ep.name,
1066                         list_entry(ep->queue.next, struct dwc2_request, queue));
1067
1068                 return -EAGAIN;
1069         }
1070
1071         dev = ep->dev;
1072         debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1073
1074         spin_lock_irqsave(&dev->lock, flags);
1075
1076         if (value == 0) {
1077                 ep->stopped = 0;
1078                 dwc2_udc_ep_clear_stall(ep);
1079         } else {
1080                 if (ep_num == 0)
1081                         dev->ep0state = WAIT_FOR_SETUP;
1082
1083                 ep->stopped = 1;
1084                 dwc2_udc_ep_set_stall(ep);
1085         }
1086
1087         spin_unlock_irqrestore(&dev->lock, flags);
1088
1089         return 0;
1090 }
1091
1092 static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
1093 {
1094         u8 ep_num;
1095         u32 ep_ctrl = 0, daintmsk = 0;
1096
1097         ep_num = ep_index(ep);
1098
1099         /* Read DEPCTLn register */
1100         if (ep_is_in(ep)) {
1101                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
1102                 daintmsk = 1 << ep_num;
1103         } else {
1104                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
1105                 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1106         }
1107
1108         debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1109                 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1110
1111         /* If the EP is already active don't change the EP Control
1112          * register. */
1113         if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1114                 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1115                         (ep->bmAttributes << DEPCTL_TYPE_BIT);
1116                 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1117                         (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1118                 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1119
1120                 if (ep_is_in(ep)) {
1121                         writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
1122                         debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1123                               __func__, ep_num, ep_num,
1124                               readl(&reg->in_endp[ep_num].diepctl));
1125                 } else {
1126                         writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1127                         debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1128                               __func__, ep_num, ep_num,
1129                               readl(&reg->out_endp[ep_num].doepctl));
1130                 }
1131         }
1132
1133         /* Unmask EP Interrtupt */
1134         writel(readl(&reg->daintmsk)|daintmsk, &reg->daintmsk);
1135         debug("%s: DAINTMSK = 0x%x\n", __func__, readl(&reg->daintmsk));
1136
1137 }
1138
1139 static int dwc2_udc_clear_feature(struct usb_ep *_ep)
1140 {
1141         struct dwc2_udc *dev;
1142         struct dwc2_ep  *ep;
1143         u8              ep_num;
1144
1145         ep = container_of(_ep, struct dwc2_ep, ep);
1146         ep_num = ep_index(ep);
1147
1148         dev = ep->dev;
1149         debug_cond(DEBUG_SETUP != 0,
1150                    "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1151                    __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1152
1153         if (usb_ctrl->wLength != 0) {
1154                 debug_cond(DEBUG_SETUP != 0,
1155                            "\tCLEAR_FEATURE: wLength is not zero.....\n");
1156                 return 1;
1157         }
1158
1159         switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1160         case USB_RECIP_DEVICE:
1161                 switch (usb_ctrl->wValue) {
1162                 case USB_DEVICE_REMOTE_WAKEUP:
1163                         debug_cond(DEBUG_SETUP != 0,
1164                                    "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1165                         break;
1166
1167                 case USB_DEVICE_TEST_MODE:
1168                         debug_cond(DEBUG_SETUP != 0,
1169                                    "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1170                         /** @todo Add CLEAR_FEATURE for TEST modes. */
1171                         break;
1172                 }
1173
1174                 dwc2_udc_ep0_zlp(dev);
1175                 break;
1176
1177         case USB_RECIP_ENDPOINT:
1178                 debug_cond(DEBUG_SETUP != 0,
1179                            "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1180                            usb_ctrl->wValue);
1181
1182                 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1183                         if (ep_num == 0) {
1184                                 dwc2_udc_ep0_set_stall(ep);
1185                                 return 0;
1186                         }
1187
1188                         dwc2_udc_ep0_zlp(dev);
1189
1190                         dwc2_udc_ep_clear_stall(ep);
1191                         dwc2_udc_ep_activate(ep);
1192                         ep->stopped = 0;
1193
1194                         clear_feature_num = ep_num;
1195                         clear_feature_flag = 1;
1196                 }
1197                 break;
1198         }
1199
1200         return 0;
1201 }
1202
1203 static int dwc2_udc_set_feature(struct usb_ep *_ep)
1204 {
1205         struct dwc2_udc *dev;
1206         struct dwc2_ep  *ep;
1207         u8              ep_num;
1208
1209         ep = container_of(_ep, struct dwc2_ep, ep);
1210         ep_num = ep_index(ep);
1211         dev = ep->dev;
1212
1213         debug_cond(DEBUG_SETUP != 0,
1214                    "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1215                     __func__, ep_num);
1216
1217         if (usb_ctrl->wLength != 0) {
1218                 debug_cond(DEBUG_SETUP != 0,
1219                            "\tSET_FEATURE: wLength is not zero.....\n");
1220                 return 1;
1221         }
1222
1223         switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1224         case USB_RECIP_DEVICE:
1225                 switch (usb_ctrl->wValue) {
1226                 case USB_DEVICE_REMOTE_WAKEUP:
1227                         debug_cond(DEBUG_SETUP != 0,
1228                                    "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1229                         break;
1230                 case USB_DEVICE_B_HNP_ENABLE:
1231                         debug_cond(DEBUG_SETUP != 0,
1232                                    "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1233                         break;
1234
1235                 case USB_DEVICE_A_HNP_SUPPORT:
1236                         /* RH port supports HNP */
1237                         debug_cond(DEBUG_SETUP != 0,
1238                                    "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1239                         break;
1240
1241                 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1242                         /* other RH port does */
1243                         debug_cond(DEBUG_SETUP != 0,
1244                                    "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1245                         break;
1246                 }
1247
1248                 dwc2_udc_ep0_zlp(dev);
1249                 return 0;
1250
1251         case USB_RECIP_INTERFACE:
1252                 debug_cond(DEBUG_SETUP != 0,
1253                            "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1254                 break;
1255
1256         case USB_RECIP_ENDPOINT:
1257                 debug_cond(DEBUG_SETUP != 0,
1258                            "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1259                 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1260                         if (ep_num == 0) {
1261                                 dwc2_udc_ep0_set_stall(ep);
1262                                 return 0;
1263                         }
1264                         ep->stopped = 1;
1265                         dwc2_udc_ep_set_stall(ep);
1266                 }
1267
1268                 dwc2_udc_ep0_zlp(dev);
1269                 return 0;
1270         }
1271
1272         return 1;
1273 }
1274
1275 /*
1276  * WAIT_FOR_SETUP (OUT_PKT_RDY)
1277  */
1278 static void dwc2_ep0_setup(struct dwc2_udc *dev)
1279 {
1280         struct dwc2_ep *ep = &dev->ep[0];
1281         int i;
1282         u8 ep_num;
1283
1284         /* Nuke all previous transfers */
1285         nuke(ep, -EPROTO);
1286
1287         /* read control req from fifo (8 bytes) */
1288         dwc2_fifo_read(ep, usb_ctrl, 8);
1289
1290         debug_cond(DEBUG_SETUP != 0,
1291                    "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1292                    "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1293                    __func__, usb_ctrl->bRequestType,
1294                    (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1295                    usb_ctrl->bRequest,
1296                    usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1297
1298 #ifdef DEBUG
1299         {
1300                 int i, len = sizeof(*usb_ctrl);
1301                 char *p = (char *)usb_ctrl;
1302
1303                 printf("pkt = ");
1304                 for (i = 0; i < len; i++) {
1305                         printf("%02x", ((u8 *)p)[i]);
1306                         if ((i & 7) == 7)
1307                                 printf(" ");
1308                 }
1309                 printf("\n");
1310         }
1311 #endif
1312
1313         if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1314             usb_ctrl->wLength != 1) {
1315                 debug_cond(DEBUG_SETUP != 0,
1316                            "\t%s:GET_MAX_LUN_REQUEST:invalid",
1317                            __func__);
1318                 debug_cond(DEBUG_SETUP != 0,
1319                            "wLength = %d, setup returned\n",
1320                            usb_ctrl->wLength);
1321
1322                 dwc2_udc_ep0_set_stall(ep);
1323                 dev->ep0state = WAIT_FOR_SETUP;
1324
1325                 return;
1326         } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1327                  usb_ctrl->wLength != 0) {
1328                 /* Bulk-Only *mass storge reset of class-specific request */
1329                 debug_cond(DEBUG_SETUP != 0,
1330                            "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1331                            __func__, usb_ctrl->wLength);
1332
1333                 dwc2_udc_ep0_set_stall(ep);
1334                 dev->ep0state = WAIT_FOR_SETUP;
1335
1336                 return;
1337         }
1338
1339         /* Set direction of EP0 */
1340         if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1341                 ep->bEndpointAddress |= USB_DIR_IN;
1342         } else {
1343                 ep->bEndpointAddress &= ~USB_DIR_IN;
1344         }
1345         /* cope with automagic for some standard requests. */
1346         dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1347                 == USB_TYPE_STANDARD;
1348
1349         dev->req_pending = 1;
1350
1351         /* Handle some SETUP packets ourselves */
1352         if (dev->req_std) {
1353                 switch (usb_ctrl->bRequest) {
1354                 case USB_REQ_SET_ADDRESS:
1355                 debug_cond(DEBUG_SETUP != 0,
1356                            "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1357                            __func__, usb_ctrl->wValue);
1358                         if (usb_ctrl->bRequestType
1359                                 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1360                                 break;
1361
1362                         udc_set_address(dev, usb_ctrl->wValue);
1363                         return;
1364
1365                 case USB_REQ_SET_CONFIGURATION:
1366                         debug_cond(DEBUG_SETUP != 0,
1367                                    "=====================================\n");
1368                         debug_cond(DEBUG_SETUP != 0,
1369                                    "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1370                                    __func__, usb_ctrl->wValue);
1371
1372                         if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1373                                 reset_available = 1;
1374
1375                         break;
1376
1377                 case USB_REQ_GET_DESCRIPTOR:
1378                         debug_cond(DEBUG_SETUP != 0,
1379                                    "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1380                                    __func__);
1381                         break;
1382
1383                 case USB_REQ_SET_INTERFACE:
1384                         debug_cond(DEBUG_SETUP != 0,
1385                                    "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1386                                    __func__, usb_ctrl->wValue);
1387
1388                         if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1389                                 reset_available = 1;
1390
1391                         break;
1392
1393                 case USB_REQ_GET_CONFIGURATION:
1394                         debug_cond(DEBUG_SETUP != 0,
1395                                    "%s: *** USB_REQ_GET_CONFIGURATION\n",
1396                                    __func__);
1397                         break;
1398
1399                 case USB_REQ_GET_STATUS:
1400                         if (!dwc2_udc_get_status(dev, usb_ctrl))
1401                                 return;
1402
1403                         break;
1404
1405                 case USB_REQ_CLEAR_FEATURE:
1406                         ep_num = usb_ctrl->wIndex & 0x7f;
1407
1408                         if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep))
1409                                 return;
1410
1411                         break;
1412
1413                 case USB_REQ_SET_FEATURE:
1414                         ep_num = usb_ctrl->wIndex & 0x7f;
1415
1416                         if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep))
1417                                 return;
1418
1419                         break;
1420
1421                 default:
1422                         debug_cond(DEBUG_SETUP != 0,
1423                                    "%s: *** Default of usb_ctrl->bRequest=0x%x"
1424                                    "happened.\n", __func__, usb_ctrl->bRequest);
1425                         break;
1426                 }
1427         }
1428
1429
1430         if (likely(dev->driver)) {
1431                 /* device-2-host (IN) or no data setup command,
1432                  * process immediately */
1433                 debug_cond(DEBUG_SETUP != 0,
1434                            "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1435                             __func__);
1436
1437                 spin_unlock(&dev->lock);
1438                 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1439                 spin_lock(&dev->lock);
1440
1441                 if (i < 0) {
1442                         /* setup processing failed, force stall */
1443                         dwc2_udc_ep0_set_stall(ep);
1444                         dev->ep0state = WAIT_FOR_SETUP;
1445
1446                         debug_cond(DEBUG_SETUP != 0,
1447                                    "\tdev->driver->setup failed (%d),"
1448                                     " bRequest = %d\n",
1449                                 i, usb_ctrl->bRequest);
1450
1451
1452                 } else if (dev->req_pending) {
1453                         dev->req_pending = 0;
1454                         debug_cond(DEBUG_SETUP != 0,
1455                                    "\tdev->req_pending...\n");
1456                 }
1457
1458                 debug_cond(DEBUG_SETUP != 0,
1459                            "\tep0state = %s\n", state_names[dev->ep0state]);
1460
1461         }
1462 }
1463
1464 /*
1465  * handle ep0 interrupt
1466  */
1467 static void dwc2_handle_ep0(struct dwc2_udc *dev)
1468 {
1469         if (dev->ep0state == WAIT_FOR_SETUP) {
1470                 debug_cond(DEBUG_OUT_EP != 0,
1471                            "%s: WAIT_FOR_SETUP\n", __func__);
1472                 dwc2_ep0_setup(dev);
1473
1474         } else {
1475                 debug_cond(DEBUG_OUT_EP != 0,
1476                            "%s: strange state!!(state = %s)\n",
1477                         __func__, state_names[dev->ep0state]);
1478         }
1479 }
1480
1481 static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep)
1482 {
1483         debug_cond(DEBUG_EP0 != 0,
1484                    "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1485         if (ep_is_in(ep)) {
1486                 dev->ep0state = DATA_STATE_XMIT;
1487                 dwc2_ep0_write(dev);
1488
1489         } else {
1490                 dev->ep0state = DATA_STATE_RECV;
1491                 dwc2_ep0_read(dev);
1492         }
1493 }