1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
4 * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
6 * Copyright (C) 2009 for Samsung Electronics
8 * BSP Support for Samsung's UDC driver
10 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
12 * State machine bugfixes:
13 * Marek Szyprowski <m.szyprowski@samsung.com>
16 * Marek Szyprowski <m.szyprowski@samsung.com>
17 * Lukasz Majewski <l.majewski@samsumg.com>
20 static u8 clear_feature_num;
21 int clear_feature_flag;
23 /* Bulk-Only Mass Storage Reset (class-specific request) */
24 #define GET_MAX_LUN_REQUEST 0xFE
25 #define BOT_RESET_REQUEST 0xFF
27 static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev)
31 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
32 writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz);
34 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
35 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
36 ®->in_endp[EP0_CON].diepctl);
38 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
39 __func__, readl(®->in_endp[EP0_CON].diepctl));
40 dev->ep0state = WAIT_FOR_IN_COMPLETE;
43 static void dwc2_udc_pre_setup(void)
47 debug_cond(DEBUG_IN_EP,
48 "%s : Prepare Setup packets.\n", __func__);
50 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
51 ®->out_endp[EP0_CON].doeptsiz);
52 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
54 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
55 writel(ep_ctrl|DEPCTL_EPENA, ®->out_endp[EP0_CON].doepctl);
57 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
58 __func__, readl(®->in_endp[EP0_CON].diepctl));
59 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
60 __func__, readl(®->out_endp[EP0_CON].doepctl));
64 static inline void dwc2_ep0_complete_out(void)
68 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
69 __func__, readl(®->in_endp[EP0_CON].diepctl));
70 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
71 __func__, readl(®->out_endp[EP0_CON].doepctl));
73 debug_cond(DEBUG_IN_EP,
74 "%s : Prepare Complete Out packet.\n", __func__);
76 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
77 ®->out_endp[EP0_CON].doeptsiz);
78 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
80 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
81 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
82 ®->out_endp[EP0_CON].doepctl);
84 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
85 __func__, readl(®->in_endp[EP0_CON].diepctl));
86 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
87 __func__, readl(®->out_endp[EP0_CON].doepctl));
92 static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req)
96 u32 ep_num = ep_index(ep);
98 buf = req->req.buf + req->req.actual;
99 length = min_t(u32, req->req.length - req->req.actual,
100 ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket);
105 if (ep_num == EP0_CON || length == 0)
108 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
110 ctrl = readl(®->out_endp[ep_num].doepctl);
112 invalidate_dcache_range((unsigned long) ep->dma_buf,
113 (unsigned long) ep->dma_buf +
114 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
116 writel((unsigned long) ep->dma_buf, ®->out_endp[ep_num].doepdma);
117 writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
118 ®->out_endp[ep_num].doeptsiz);
119 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl);
121 debug_cond(DEBUG_OUT_EP != 0,
122 "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
123 "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
124 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
126 readl(®->out_endp[ep_num].doepdma),
127 readl(®->out_endp[ep_num].doeptsiz),
128 readl(®->out_endp[ep_num].doepctl),
129 buf, pktcnt, length);
134 static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req)
138 u32 ep_num = ep_index(ep);
140 buf = req->req.buf + req->req.actual;
141 length = req->req.length - req->req.actual;
143 if (ep_num == EP0_CON)
144 length = min(length, (u32)ep_maxpacket(ep));
149 flush_dcache_range((unsigned long) ep->dma_buf,
150 (unsigned long) ep->dma_buf +
151 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
156 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
158 /* Flush the endpoint's Tx FIFO */
159 writel(TX_FIFO_NUMBER(ep->fifo_num), ®->grstctl);
160 writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, ®->grstctl);
161 while (readl(®->grstctl) & TX_FIFO_FLUSH)
164 writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma);
165 writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
166 ®->in_endp[ep_num].dieptsiz);
168 ctrl = readl(®->in_endp[ep_num].diepctl);
170 /* Write the FIFO number to be used for this endpoint */
171 ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
172 ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
174 /* Clear reserved (Next EP) bits */
175 ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
177 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->in_endp[ep_num].diepctl);
179 debug_cond(DEBUG_IN_EP,
180 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
181 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
182 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
184 readl(®->in_endp[ep_num].diepdma),
185 readl(®->in_endp[ep_num].dieptsiz),
186 readl(®->in_endp[ep_num].diepctl),
187 buf, pktcnt, length);
192 static void complete_rx(struct dwc2_udc *dev, u8 ep_num)
194 struct dwc2_ep *ep = &dev->ep[ep_num];
195 struct dwc2_request *req = NULL;
196 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
198 if (list_empty(&ep->queue)) {
199 debug_cond(DEBUG_OUT_EP != 0,
200 "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
206 req = list_entry(ep->queue.next, struct dwc2_request, queue);
207 ep_tsr = readl(®->out_endp[ep_num].doeptsiz);
209 if (ep_num == EP0_CON)
210 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
212 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
214 xfer_size = ep->len - xfer_size;
219 * Please be careful with proper buffer allocation for USB request,
220 * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only
221 * with starting address, but also its size shall be a cache line
224 * This will prevent from corruption of data allocated immediatelly
225 * before or after the buffer.
227 * For armv7, the cache_v7.c provides proper code to emit "ERROR"
228 * message to warn users.
230 invalidate_dcache_range((unsigned long) ep->dma_buf,
231 (unsigned long) ep->dma_buf +
232 ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE));
234 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
235 is_short = !!(xfer_size % ep->ep.maxpacket);
237 debug_cond(DEBUG_OUT_EP != 0,
238 "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
239 "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
240 __func__, ep_num, req->req.actual, req->req.length,
241 is_short, ep_tsr, req->req.length - req->req.actual);
243 if (is_short || req->req.actual == req->req.length) {
244 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
245 debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
246 dwc2_udc_ep0_zlp(dev);
247 /* packet will be completed in complete_tx() */
248 dev->ep0state = WAIT_FOR_IN_COMPLETE;
252 if (!list_empty(&ep->queue)) {
253 req = list_entry(ep->queue.next,
254 struct dwc2_request, queue);
255 debug_cond(DEBUG_OUT_EP != 0,
256 "%s: Next Rx request start...\n",
265 static void complete_tx(struct dwc2_udc *dev, u8 ep_num)
267 struct dwc2_ep *ep = &dev->ep[ep_num];
268 struct dwc2_request *req;
269 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
272 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
273 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
274 dwc2_ep0_complete_out();
278 if (list_empty(&ep->queue)) {
279 debug_cond(DEBUG_IN_EP,
280 "%s: TX DMA done : NULL REQ on IN EP-%d\n",
286 req = list_entry(ep->queue.next, struct dwc2_request, queue);
288 ep_tsr = readl(®->in_endp[ep_num].dieptsiz);
291 is_short = (xfer_size < ep->ep.maxpacket);
292 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
294 debug_cond(DEBUG_IN_EP,
295 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
296 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
297 __func__, ep_num, req->req.actual, req->req.length,
298 is_short, ep_tsr, req->req.length - req->req.actual);
301 if (dev->ep0state == DATA_STATE_XMIT) {
302 debug_cond(DEBUG_IN_EP,
303 "%s: ep_num = %d, ep0stat =="
306 last = write_fifo_ep0(ep, req);
308 dev->ep0state = WAIT_FOR_COMPLETE;
309 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
310 debug_cond(DEBUG_IN_EP,
311 "%s: ep_num = %d, completing request\n",
314 dev->ep0state = WAIT_FOR_SETUP;
315 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
316 debug_cond(DEBUG_IN_EP,
317 "%s: ep_num = %d, completing request\n",
320 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
321 dwc2_ep0_complete_out();
323 debug_cond(DEBUG_IN_EP,
324 "%s: ep_num = %d, invalid ep state\n",
330 if (req->req.actual == req->req.length)
333 if (!list_empty(&ep->queue)) {
334 req = list_entry(ep->queue.next, struct dwc2_request, queue);
335 debug_cond(DEBUG_IN_EP,
336 "%s: Next Tx request start...\n", __func__);
341 static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num)
343 struct dwc2_ep *ep = &dev->ep[ep_num];
344 struct dwc2_request *req;
346 debug_cond(DEBUG_IN_EP,
347 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
349 if (!list_empty(&ep->queue)) {
350 req = list_entry(ep->queue.next, struct dwc2_request, queue);
351 debug_cond(DEBUG_IN_EP,
352 "%s: Next Tx request(0x%p) start...\n",
360 debug_cond(DEBUG_IN_EP,
361 "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
368 static void process_ep_in_intr(struct dwc2_udc *dev)
370 u32 ep_intr, ep_intr_status;
373 ep_intr = readl(®->daint);
374 debug_cond(DEBUG_IN_EP,
375 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
377 ep_intr &= DAINT_MASK;
380 if (ep_intr & DAINT_IN_EP_INT(1)) {
381 ep_intr_status = readl(®->in_endp[ep_num].diepint);
382 debug_cond(DEBUG_IN_EP,
383 "\tEP%d-IN : DIEPINT = 0x%x\n",
384 ep_num, ep_intr_status);
386 /* Interrupt Clear */
387 writel(ep_intr_status, ®->in_endp[ep_num].diepint);
389 if (ep_intr_status & TRANSFER_DONE) {
390 complete_tx(dev, ep_num);
394 WAIT_FOR_IN_COMPLETE)
395 dev->ep0state = WAIT_FOR_SETUP;
397 if (dev->ep0state == WAIT_FOR_SETUP)
398 dwc2_udc_pre_setup();
400 /* continue transfer after
401 set_clear_halt for DMA mode */
402 if (clear_feature_flag == 1) {
403 dwc2_udc_check_tx_queue(dev,
405 clear_feature_flag = 0;
415 static void process_ep_out_intr(struct dwc2_udc *dev)
417 u32 ep_intr, ep_intr_status;
420 ep_intr = readl(®->daint);
421 debug_cond(DEBUG_OUT_EP != 0,
422 "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
425 ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
429 ep_intr_status = readl(®->out_endp[ep_num].doepint);
430 debug_cond(DEBUG_OUT_EP != 0,
431 "\tEP%d-OUT : DOEPINT = 0x%x\n",
432 ep_num, ep_intr_status);
434 /* Interrupt Clear */
435 writel(ep_intr_status, ®->out_endp[ep_num].doepint);
438 if (ep_intr_status & TRANSFER_DONE) {
440 WAIT_FOR_OUT_COMPLETE)
441 complete_rx(dev, ep_num);
443 dev->ep0state = WAIT_FOR_SETUP;
444 dwc2_udc_pre_setup();
449 CTRL_OUT_EP_SETUP_PHASE_DONE) {
450 debug_cond(DEBUG_OUT_EP != 0,
451 "SETUP packet arrived\n");
452 dwc2_handle_ep0(dev);
455 if (ep_intr_status & TRANSFER_DONE)
456 complete_rx(dev, ep_num);
465 * usb client interrupt handler.
467 static int dwc2_udc_irq(int irq, void *_dev)
469 struct dwc2_udc *dev = _dev;
470 u32 intr_status, gotgint;
471 u32 usb_status, gintmsk;
472 unsigned long flags = 0;
474 spin_lock_irqsave(&dev->lock, flags);
476 intr_status = readl(®->gintsts);
477 gintmsk = readl(®->gintmsk);
479 debug_cond(DEBUG_ISR,
480 "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
481 "DAINT : 0x%x, DAINTMSK : 0x%x\n",
482 __func__, intr_status, state_names[dev->ep0state], gintmsk,
483 readl(®->daint), readl(®->daintmsk));
486 spin_unlock_irqrestore(&dev->lock, flags);
490 if (intr_status & INT_ENUMDONE) {
491 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
493 writel(INT_ENUMDONE, ®->gintsts);
494 usb_status = (readl(®->dsts) & 0x6);
496 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
497 debug_cond(DEBUG_ISR,
498 "\t\tFull Speed Detection\n");
499 set_max_pktsize(dev, USB_SPEED_FULL);
502 debug_cond(DEBUG_ISR,
503 "\t\tHigh Speed Detection : 0x%x\n",
505 set_max_pktsize(dev, USB_SPEED_HIGH);
509 if (intr_status & INT_EARLY_SUSPEND) {
510 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
511 writel(INT_EARLY_SUSPEND, ®->gintsts);
514 if (intr_status & INT_SUSPEND) {
515 usb_status = readl(®->dsts);
516 debug_cond(DEBUG_ISR,
517 "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
518 writel(INT_SUSPEND, ®->gintsts);
520 if (dev->gadget.speed != USB_SPEED_UNKNOWN
522 if (dev->driver->suspend)
523 dev->driver->suspend(&dev->gadget);
527 if (intr_status & INT_OTG) {
528 gotgint = readl(®->gotgint);
529 debug_cond(DEBUG_ISR,
530 "\tOTG interrupt: (GOTGINT):0x%x\n", gotgint);
532 if (gotgint & GOTGINT_SES_END_DET) {
533 debug_cond(DEBUG_ISR, "\t\tSession End Detected\n");
534 /* Let gadget detect disconnected state */
535 if (dev->driver->disconnect) {
536 spin_unlock_irqrestore(&dev->lock, flags);
537 dev->driver->disconnect(&dev->gadget);
538 spin_lock_irqsave(&dev->lock, flags);
541 writel(gotgint, ®->gotgint);
544 if (intr_status & INT_RESUME) {
545 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
546 writel(INT_RESUME, ®->gintsts);
548 if (dev->gadget.speed != USB_SPEED_UNKNOWN
550 && dev->driver->resume) {
552 dev->driver->resume(&dev->gadget);
556 if (intr_status & INT_RESET) {
557 usb_status = readl(®->gotgctl);
558 debug_cond(DEBUG_ISR,
559 "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
560 writel(INT_RESET, ®->gintsts);
562 if ((usb_status & 0xc0000) == (0x3 << 18)) {
563 if (reset_available) {
564 debug_cond(DEBUG_ISR,
565 "\t\tOTG core got reset (%d)!!\n",
568 dev->ep0state = WAIT_FOR_SETUP;
570 dwc2_udc_pre_setup();
576 debug_cond(DEBUG_ISR,
577 "\t\tRESET handling skipped\n");
581 if (intr_status & INT_IN_EP)
582 process_ep_in_intr(dev);
584 if (intr_status & INT_OUT_EP)
585 process_ep_out_intr(dev);
587 spin_unlock_irqrestore(&dev->lock, flags);
592 /** Queue one request
593 * Kickstart transfer if needed
595 static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req,
598 struct dwc2_request *req;
600 struct dwc2_udc *dev;
601 unsigned long flags = 0;
604 req = container_of(_req, struct dwc2_request, req);
605 if (unlikely(!_req || !_req->complete || !_req->buf
606 || !list_empty(&req->queue))) {
608 debug("%s: bad params\n", __func__);
612 ep = container_of(_ep, struct dwc2_ep, ep);
614 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
616 debug("%s: bad ep: %s, %d, %p\n", __func__,
617 ep->ep.name, !ep->desc, _ep);
621 ep_num = ep_index(ep);
623 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
625 debug("%s: bogus device state %p\n", __func__, dev->driver);
629 spin_lock_irqsave(&dev->lock, flags);
631 _req->status = -EINPROGRESS;
634 /* kickstart this i/o queue? */
635 debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
636 "Q empty = %d, stopped = %d\n",
637 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
638 _req, _req->length, _req->buf,
639 list_empty(&ep->queue), ep->stopped);
643 int i, len = _req->length;
648 for (i = 0; i < len; i++) {
649 printf("%02x", ((u8 *)_req->buf)[i]);
657 if (list_empty(&ep->queue) && !ep->stopped) {
661 list_add_tail(&req->queue, &ep->queue);
662 dwc2_ep0_kick(dev, ep);
665 } else if (ep_is_in(ep)) {
666 gintsts = readl(®->gintsts);
667 debug_cond(DEBUG_IN_EP,
668 "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n",
673 gintsts = readl(®->gintsts);
674 debug_cond(DEBUG_OUT_EP != 0,
675 "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n",
682 /* pio or dma irq handler advances the queue. */
683 if (likely(req != 0))
684 list_add_tail(&req->queue, &ep->queue);
686 spin_unlock_irqrestore(&dev->lock, flags);
691 /****************************************************************/
692 /* End Point 0 related functions */
693 /****************************************************************/
695 /* return: 0 = still running, 1 = completed, negative = errno */
696 static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req)
702 max = ep_maxpacket(ep);
704 debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
706 count = setdma_tx(ep, req);
708 /* last packet is usually short (or a zlp) */
709 if (likely(count != max))
712 if (likely(req->req.length != req->req.actual + count)
719 debug_cond(DEBUG_EP0 != 0,
720 "%s: wrote %s %d bytes%s %d left %p\n", __func__,
723 req->req.length - req->req.actual - count, req);
725 /* requests complete when all IN data is in the FIFO */
727 ep->dev->ep0state = WAIT_FOR_SETUP;
734 static int dwc2_fifo_read(struct dwc2_ep *ep, void *cp, int max)
736 invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
737 ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
739 debug_cond(DEBUG_EP0 != 0,
740 "%s: bytes=%d, ep_index=%d 0x%p\n", __func__,
741 max, ep_index(ep), cp);
747 * udc_set_address - set the USB address for this device
750 * Called from control endpoint function
751 * after it decodes a set address setup packet.
753 static void udc_set_address(struct dwc2_udc *dev, unsigned char address)
755 u32 ctrl = readl(®->dcfg);
756 writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg);
758 dwc2_udc_ep0_zlp(dev);
760 debug_cond(DEBUG_EP0 != 0,
761 "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
762 __func__, address, readl(®->dcfg));
764 dev->usb_address = address;
767 static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep)
769 struct dwc2_udc *dev;
773 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
775 /* set the disable and stall bits */
776 if (ep_ctrl & DEPCTL_EPENA)
777 ep_ctrl |= DEPCTL_EPDIS;
779 ep_ctrl |= DEPCTL_STALL;
781 writel(ep_ctrl, ®->in_endp[EP0_CON].diepctl);
783 debug_cond(DEBUG_EP0 != 0,
784 "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
785 __func__, ep_index(ep), ®->in_endp[EP0_CON].diepctl);
787 * The application can only set this bit, and the core clears it,
788 * when a SETUP token is received for this endpoint
790 dev->ep0state = WAIT_FOR_SETUP;
792 dwc2_udc_pre_setup();
795 static void dwc2_ep0_read(struct dwc2_udc *dev)
797 struct dwc2_request *req;
798 struct dwc2_ep *ep = &dev->ep[0];
800 if (!list_empty(&ep->queue)) {
801 req = list_entry(ep->queue.next, struct dwc2_request, queue);
804 debug("%s: ---> BUG\n", __func__);
809 debug_cond(DEBUG_EP0 != 0,
810 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
811 __func__, req, req->req.length, req->req.actual);
813 if (req->req.length == 0) {
814 /* zlp for Set_configuration, Set_interface,
815 * or Bulk-Only mass storge reset */
818 dwc2_udc_ep0_zlp(dev);
820 debug_cond(DEBUG_EP0 != 0,
821 "%s: req.length = 0, bRequest = %d\n",
822 __func__, usb_ctrl->bRequest);
832 static int dwc2_ep0_write(struct dwc2_udc *dev)
834 struct dwc2_request *req;
835 struct dwc2_ep *ep = &dev->ep[0];
836 int ret, need_zlp = 0;
838 if (list_empty(&ep->queue))
841 req = list_entry(ep->queue.next, struct dwc2_request, queue);
844 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
848 debug_cond(DEBUG_EP0 != 0,
849 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
850 __func__, req, req->req.length, req->req.actual);
852 if (req->req.length - req->req.actual == ep0_fifo_size) {
853 /* Next write will end with the packet size, */
854 /* so we need Zero-length-packet */
858 ret = write_fifo_ep0(ep, req);
860 if ((ret == 1) && !need_zlp) {
862 dev->ep0state = WAIT_FOR_COMPLETE;
863 debug_cond(DEBUG_EP0 != 0,
864 "%s: finished, waiting for status\n", __func__);
867 dev->ep0state = DATA_STATE_XMIT;
868 debug_cond(DEBUG_EP0 != 0,
869 "%s: not finished\n", __func__);
875 static int dwc2_udc_get_status(struct dwc2_udc *dev,
876 struct usb_ctrlrequest *crq)
878 u8 ep_num = crq->wIndex & 0x7F;
882 debug_cond(DEBUG_SETUP != 0,
883 "%s: *** USB_REQ_GET_STATUS\n", __func__);
884 printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
885 switch (crq->bRequestType & USB_RECIP_MASK) {
886 case USB_RECIP_INTERFACE:
888 debug_cond(DEBUG_SETUP != 0,
889 "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
893 case USB_RECIP_DEVICE:
894 g_status = 0x1; /* Self powered */
895 debug_cond(DEBUG_SETUP != 0,
896 "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
900 case USB_RECIP_ENDPOINT:
901 if (crq->wLength > 2) {
902 debug_cond(DEBUG_SETUP != 0,
903 "\tGET_STATUS:Not support EP or wLength\n");
907 g_status = dev->ep[ep_num].stopped;
908 debug_cond(DEBUG_SETUP != 0,
909 "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
918 memcpy(usb_ctrl, &g_status, sizeof(g_status));
920 flush_dcache_range((unsigned long) usb_ctrl,
921 (unsigned long) usb_ctrl +
922 ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
924 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
925 writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
926 ®->in_endp[EP0_CON].dieptsiz);
928 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
929 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
930 ®->in_endp[EP0_CON].diepctl);
931 dev->ep0state = WAIT_FOR_NULL_COMPLETE;
936 static void dwc2_udc_set_nak(struct dwc2_ep *ep)
941 ep_num = ep_index(ep);
942 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
945 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
946 ep_ctrl |= DEPCTL_SNAK;
947 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
948 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
949 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
951 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
952 ep_ctrl |= DEPCTL_SNAK;
953 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
954 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
955 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
962 static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep)
967 ep_num = ep_index(ep);
968 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
971 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
973 /* set the disable and stall bits */
974 if (ep_ctrl & DEPCTL_EPENA)
975 ep_ctrl |= DEPCTL_EPDIS;
977 ep_ctrl |= DEPCTL_STALL;
979 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
980 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
981 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
984 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
986 /* set the stall bit */
987 ep_ctrl |= DEPCTL_STALL;
989 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
990 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
991 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
997 static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep)
1002 ep_num = ep_index(ep);
1003 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
1006 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1008 /* clear stall bit */
1009 ep_ctrl &= ~DEPCTL_STALL;
1012 * USB Spec 9.4.5: For endpoints using data toggle, regardless
1013 * of whether an endpoint has the Halt feature set, a
1014 * ClearFeature(ENDPOINT_HALT) request always results in the
1015 * data toggle being reinitialized to DATA0.
1017 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1018 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1019 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1022 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1023 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1024 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
1027 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1029 /* clear stall bit */
1030 ep_ctrl &= ~DEPCTL_STALL;
1032 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1033 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1034 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1037 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1038 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1039 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
1045 static int dwc2_udc_set_halt(struct usb_ep *_ep, int value)
1048 struct dwc2_udc *dev;
1049 unsigned long flags = 0;
1052 ep = container_of(_ep, struct dwc2_ep, ep);
1053 ep_num = ep_index(ep);
1055 if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1056 ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1057 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1061 /* Attempt to halt IN ep will fail if any transfer requests
1062 * are still queue */
1063 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1064 debug("%s: %s queue not empty, req = %p\n",
1065 __func__, ep->ep.name,
1066 list_entry(ep->queue.next, struct dwc2_request, queue));
1072 debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1074 spin_lock_irqsave(&dev->lock, flags);
1078 dwc2_udc_ep_clear_stall(ep);
1081 dev->ep0state = WAIT_FOR_SETUP;
1084 dwc2_udc_ep_set_stall(ep);
1087 spin_unlock_irqrestore(&dev->lock, flags);
1092 static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
1095 u32 ep_ctrl = 0, daintmsk = 0;
1097 ep_num = ep_index(ep);
1099 /* Read DEPCTLn register */
1101 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1102 daintmsk = 1 << ep_num;
1104 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1105 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1108 debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1109 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1111 /* If the EP is already active don't change the EP Control
1113 if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1114 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1115 (ep->bmAttributes << DEPCTL_TYPE_BIT);
1116 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1117 (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1118 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1121 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1122 debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1123 __func__, ep_num, ep_num,
1124 readl(®->in_endp[ep_num].diepctl));
1126 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1127 debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1128 __func__, ep_num, ep_num,
1129 readl(®->out_endp[ep_num].doepctl));
1133 /* Unmask EP Interrtupt */
1134 writel(readl(®->daintmsk)|daintmsk, ®->daintmsk);
1135 debug("%s: DAINTMSK = 0x%x\n", __func__, readl(®->daintmsk));
1139 static int dwc2_udc_clear_feature(struct usb_ep *_ep)
1141 struct dwc2_udc *dev;
1145 ep = container_of(_ep, struct dwc2_ep, ep);
1146 ep_num = ep_index(ep);
1149 debug_cond(DEBUG_SETUP != 0,
1150 "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1151 __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1153 if (usb_ctrl->wLength != 0) {
1154 debug_cond(DEBUG_SETUP != 0,
1155 "\tCLEAR_FEATURE: wLength is not zero.....\n");
1159 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1160 case USB_RECIP_DEVICE:
1161 switch (usb_ctrl->wValue) {
1162 case USB_DEVICE_REMOTE_WAKEUP:
1163 debug_cond(DEBUG_SETUP != 0,
1164 "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1167 case USB_DEVICE_TEST_MODE:
1168 debug_cond(DEBUG_SETUP != 0,
1169 "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1170 /** @todo Add CLEAR_FEATURE for TEST modes. */
1174 dwc2_udc_ep0_zlp(dev);
1177 case USB_RECIP_ENDPOINT:
1178 debug_cond(DEBUG_SETUP != 0,
1179 "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1182 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1184 dwc2_udc_ep0_set_stall(ep);
1188 dwc2_udc_ep0_zlp(dev);
1190 dwc2_udc_ep_clear_stall(ep);
1191 dwc2_udc_ep_activate(ep);
1194 clear_feature_num = ep_num;
1195 clear_feature_flag = 1;
1203 static int dwc2_udc_set_feature(struct usb_ep *_ep)
1205 struct dwc2_udc *dev;
1209 ep = container_of(_ep, struct dwc2_ep, ep);
1210 ep_num = ep_index(ep);
1213 debug_cond(DEBUG_SETUP != 0,
1214 "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1217 if (usb_ctrl->wLength != 0) {
1218 debug_cond(DEBUG_SETUP != 0,
1219 "\tSET_FEATURE: wLength is not zero.....\n");
1223 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1224 case USB_RECIP_DEVICE:
1225 switch (usb_ctrl->wValue) {
1226 case USB_DEVICE_REMOTE_WAKEUP:
1227 debug_cond(DEBUG_SETUP != 0,
1228 "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1230 case USB_DEVICE_B_HNP_ENABLE:
1231 debug_cond(DEBUG_SETUP != 0,
1232 "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1235 case USB_DEVICE_A_HNP_SUPPORT:
1236 /* RH port supports HNP */
1237 debug_cond(DEBUG_SETUP != 0,
1238 "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1241 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1242 /* other RH port does */
1243 debug_cond(DEBUG_SETUP != 0,
1244 "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1248 dwc2_udc_ep0_zlp(dev);
1251 case USB_RECIP_INTERFACE:
1252 debug_cond(DEBUG_SETUP != 0,
1253 "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1256 case USB_RECIP_ENDPOINT:
1257 debug_cond(DEBUG_SETUP != 0,
1258 "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1259 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1261 dwc2_udc_ep0_set_stall(ep);
1265 dwc2_udc_ep_set_stall(ep);
1268 dwc2_udc_ep0_zlp(dev);
1276 * WAIT_FOR_SETUP (OUT_PKT_RDY)
1278 static void dwc2_ep0_setup(struct dwc2_udc *dev)
1280 struct dwc2_ep *ep = &dev->ep[0];
1284 /* Nuke all previous transfers */
1287 /* read control req from fifo (8 bytes) */
1288 dwc2_fifo_read(ep, usb_ctrl, 8);
1290 debug_cond(DEBUG_SETUP != 0,
1291 "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1292 "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1293 __func__, usb_ctrl->bRequestType,
1294 (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1296 usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1300 int i, len = sizeof(*usb_ctrl);
1301 char *p = (char *)usb_ctrl;
1304 for (i = 0; i < len; i++) {
1305 printf("%02x", ((u8 *)p)[i]);
1313 if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1314 usb_ctrl->wLength != 1) {
1315 debug_cond(DEBUG_SETUP != 0,
1316 "\t%s:GET_MAX_LUN_REQUEST:invalid",
1318 debug_cond(DEBUG_SETUP != 0,
1319 "wLength = %d, setup returned\n",
1322 dwc2_udc_ep0_set_stall(ep);
1323 dev->ep0state = WAIT_FOR_SETUP;
1326 } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1327 usb_ctrl->wLength != 0) {
1328 /* Bulk-Only *mass storge reset of class-specific request */
1329 debug_cond(DEBUG_SETUP != 0,
1330 "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1331 __func__, usb_ctrl->wLength);
1333 dwc2_udc_ep0_set_stall(ep);
1334 dev->ep0state = WAIT_FOR_SETUP;
1339 /* Set direction of EP0 */
1340 if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1341 ep->bEndpointAddress |= USB_DIR_IN;
1343 ep->bEndpointAddress &= ~USB_DIR_IN;
1345 /* cope with automagic for some standard requests. */
1346 dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1347 == USB_TYPE_STANDARD;
1349 dev->req_pending = 1;
1351 /* Handle some SETUP packets ourselves */
1353 switch (usb_ctrl->bRequest) {
1354 case USB_REQ_SET_ADDRESS:
1355 debug_cond(DEBUG_SETUP != 0,
1356 "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1357 __func__, usb_ctrl->wValue);
1358 if (usb_ctrl->bRequestType
1359 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1362 udc_set_address(dev, usb_ctrl->wValue);
1365 case USB_REQ_SET_CONFIGURATION:
1366 debug_cond(DEBUG_SETUP != 0,
1367 "=====================================\n");
1368 debug_cond(DEBUG_SETUP != 0,
1369 "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1370 __func__, usb_ctrl->wValue);
1372 if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1373 reset_available = 1;
1377 case USB_REQ_GET_DESCRIPTOR:
1378 debug_cond(DEBUG_SETUP != 0,
1379 "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1383 case USB_REQ_SET_INTERFACE:
1384 debug_cond(DEBUG_SETUP != 0,
1385 "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1386 __func__, usb_ctrl->wValue);
1388 if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1389 reset_available = 1;
1393 case USB_REQ_GET_CONFIGURATION:
1394 debug_cond(DEBUG_SETUP != 0,
1395 "%s: *** USB_REQ_GET_CONFIGURATION\n",
1399 case USB_REQ_GET_STATUS:
1400 if (!dwc2_udc_get_status(dev, usb_ctrl))
1405 case USB_REQ_CLEAR_FEATURE:
1406 ep_num = usb_ctrl->wIndex & 0x7f;
1408 if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep))
1413 case USB_REQ_SET_FEATURE:
1414 ep_num = usb_ctrl->wIndex & 0x7f;
1416 if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep))
1422 debug_cond(DEBUG_SETUP != 0,
1423 "%s: *** Default of usb_ctrl->bRequest=0x%x"
1424 "happened.\n", __func__, usb_ctrl->bRequest);
1430 if (likely(dev->driver)) {
1431 /* device-2-host (IN) or no data setup command,
1432 * process immediately */
1433 debug_cond(DEBUG_SETUP != 0,
1434 "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1437 spin_unlock(&dev->lock);
1438 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1439 spin_lock(&dev->lock);
1442 /* setup processing failed, force stall */
1443 dwc2_udc_ep0_set_stall(ep);
1444 dev->ep0state = WAIT_FOR_SETUP;
1446 debug_cond(DEBUG_SETUP != 0,
1447 "\tdev->driver->setup failed (%d),"
1449 i, usb_ctrl->bRequest);
1452 } else if (dev->req_pending) {
1453 dev->req_pending = 0;
1454 debug_cond(DEBUG_SETUP != 0,
1455 "\tdev->req_pending...\n");
1458 debug_cond(DEBUG_SETUP != 0,
1459 "\tep0state = %s\n", state_names[dev->ep0state]);
1465 * handle ep0 interrupt
1467 static void dwc2_handle_ep0(struct dwc2_udc *dev)
1469 if (dev->ep0state == WAIT_FOR_SETUP) {
1470 debug_cond(DEBUG_OUT_EP != 0,
1471 "%s: WAIT_FOR_SETUP\n", __func__);
1472 dwc2_ep0_setup(dev);
1475 debug_cond(DEBUG_OUT_EP != 0,
1476 "%s: strange state!!(state = %s)\n",
1477 __func__, state_names[dev->ep0state]);
1481 static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep)
1483 debug_cond(DEBUG_EP0 != 0,
1484 "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1486 dev->ep0state = DATA_STATE_XMIT;
1487 dwc2_ep0_write(dev);
1490 dev->ep0state = DATA_STATE_RECV;