2 * drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
3 * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
5 * Copyright (C) 2009 for Samsung Electronics
7 * BSP Support for Samsung's UDC driver
9 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
11 * State machine bugfixes:
12 * Marek Szyprowski <m.szyprowski@samsung.com>
15 * Marek Szyprowski <m.szyprowski@samsung.com>
16 * Lukasz Majewski <l.majewski@samsumg.com>
18 * SPDX-License-Identifier: GPL-2.0+
21 static u8 clear_feature_num;
22 int clear_feature_flag;
24 /* Bulk-Only Mass Storage Reset (class-specific request) */
25 #define GET_MAX_LUN_REQUEST 0xFE
26 #define BOT_RESET_REQUEST 0xFF
28 static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev)
32 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
33 writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz);
35 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
36 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
37 ®->in_endp[EP0_CON].diepctl);
39 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
40 __func__, readl(®->in_endp[EP0_CON].diepctl));
41 dev->ep0state = WAIT_FOR_IN_COMPLETE;
44 static void dwc2_udc_pre_setup(void)
48 debug_cond(DEBUG_IN_EP,
49 "%s : Prepare Setup packets.\n", __func__);
51 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
52 ®->out_endp[EP0_CON].doeptsiz);
53 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
55 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
56 writel(ep_ctrl|DEPCTL_EPENA, ®->out_endp[EP0_CON].doepctl);
58 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
59 __func__, readl(®->in_endp[EP0_CON].diepctl));
60 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
61 __func__, readl(®->out_endp[EP0_CON].doepctl));
65 static inline void dwc2_ep0_complete_out(void)
69 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
70 __func__, readl(®->in_endp[EP0_CON].diepctl));
71 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
72 __func__, readl(®->out_endp[EP0_CON].doepctl));
74 debug_cond(DEBUG_IN_EP,
75 "%s : Prepare Complete Out packet.\n", __func__);
77 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
78 ®->out_endp[EP0_CON].doeptsiz);
79 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
81 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
82 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
83 ®->out_endp[EP0_CON].doepctl);
85 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
86 __func__, readl(®->in_endp[EP0_CON].diepctl));
87 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
88 __func__, readl(®->out_endp[EP0_CON].doepctl));
93 static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req)
97 u32 ep_num = ep_index(ep);
99 buf = req->req.buf + req->req.actual;
100 length = min_t(u32, req->req.length - req->req.actual,
101 ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket);
106 if (ep_num == EP0_CON || length == 0)
109 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
111 ctrl = readl(®->out_endp[ep_num].doepctl);
113 invalidate_dcache_range((unsigned long) ep->dma_buf,
114 (unsigned long) ep->dma_buf +
115 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
117 writel((unsigned int) ep->dma_buf, ®->out_endp[ep_num].doepdma);
118 writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
119 ®->out_endp[ep_num].doeptsiz);
120 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl);
122 debug_cond(DEBUG_OUT_EP != 0,
123 "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
124 "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
125 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
127 readl(®->out_endp[ep_num].doepdma),
128 readl(®->out_endp[ep_num].doeptsiz),
129 readl(®->out_endp[ep_num].doepctl),
130 buf, pktcnt, length);
135 static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req)
139 u32 ep_num = ep_index(ep);
141 buf = req->req.buf + req->req.actual;
142 length = req->req.length - req->req.actual;
144 if (ep_num == EP0_CON)
145 length = min(length, (u32)ep_maxpacket(ep));
150 flush_dcache_range((unsigned long) ep->dma_buf,
151 (unsigned long) ep->dma_buf +
152 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
157 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
159 /* Flush the endpoint's Tx FIFO */
160 writel(TX_FIFO_NUMBER(ep->fifo_num), ®->grstctl);
161 writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, ®->grstctl);
162 while (readl(®->grstctl) & TX_FIFO_FLUSH)
165 writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma);
166 writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
167 ®->in_endp[ep_num].dieptsiz);
169 ctrl = readl(®->in_endp[ep_num].diepctl);
171 /* Write the FIFO number to be used for this endpoint */
172 ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
173 ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
175 /* Clear reserved (Next EP) bits */
176 ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
178 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->in_endp[ep_num].diepctl);
180 debug_cond(DEBUG_IN_EP,
181 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
182 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
183 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
185 readl(®->in_endp[ep_num].diepdma),
186 readl(®->in_endp[ep_num].dieptsiz),
187 readl(®->in_endp[ep_num].diepctl),
188 buf, pktcnt, length);
193 static void complete_rx(struct dwc2_udc *dev, u8 ep_num)
195 struct dwc2_ep *ep = &dev->ep[ep_num];
196 struct dwc2_request *req = NULL;
197 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
199 if (list_empty(&ep->queue)) {
200 debug_cond(DEBUG_OUT_EP != 0,
201 "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
207 req = list_entry(ep->queue.next, struct dwc2_request, queue);
208 ep_tsr = readl(®->out_endp[ep_num].doeptsiz);
210 if (ep_num == EP0_CON)
211 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
213 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
215 xfer_size = ep->len - xfer_size;
220 * Please be careful with proper buffer allocation for USB request,
221 * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only
222 * with starting address, but also its size shall be a cache line
225 * This will prevent from corruption of data allocated immediatelly
226 * before or after the buffer.
228 * For armv7, the cache_v7.c provides proper code to emit "ERROR"
229 * message to warn users.
231 invalidate_dcache_range((unsigned long) ep->dma_buf,
232 (unsigned long) ep->dma_buf +
233 ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE));
235 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
236 is_short = !!(xfer_size % ep->ep.maxpacket);
238 debug_cond(DEBUG_OUT_EP != 0,
239 "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
240 "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
241 __func__, ep_num, req->req.actual, req->req.length,
242 is_short, ep_tsr, req->req.length - req->req.actual);
244 if (is_short || req->req.actual == req->req.length) {
245 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
246 debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
247 dwc2_udc_ep0_zlp(dev);
248 /* packet will be completed in complete_tx() */
249 dev->ep0state = WAIT_FOR_IN_COMPLETE;
253 if (!list_empty(&ep->queue)) {
254 req = list_entry(ep->queue.next,
255 struct dwc2_request, queue);
256 debug_cond(DEBUG_OUT_EP != 0,
257 "%s: Next Rx request start...\n",
266 static void complete_tx(struct dwc2_udc *dev, u8 ep_num)
268 struct dwc2_ep *ep = &dev->ep[ep_num];
269 struct dwc2_request *req;
270 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
273 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
274 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
275 dwc2_ep0_complete_out();
279 if (list_empty(&ep->queue)) {
280 debug_cond(DEBUG_IN_EP,
281 "%s: TX DMA done : NULL REQ on IN EP-%d\n",
287 req = list_entry(ep->queue.next, struct dwc2_request, queue);
289 ep_tsr = readl(®->in_endp[ep_num].dieptsiz);
292 is_short = (xfer_size < ep->ep.maxpacket);
293 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
295 debug_cond(DEBUG_IN_EP,
296 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
297 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
298 __func__, ep_num, req->req.actual, req->req.length,
299 is_short, ep_tsr, req->req.length - req->req.actual);
302 if (dev->ep0state == DATA_STATE_XMIT) {
303 debug_cond(DEBUG_IN_EP,
304 "%s: ep_num = %d, ep0stat =="
307 last = write_fifo_ep0(ep, req);
309 dev->ep0state = WAIT_FOR_COMPLETE;
310 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
311 debug_cond(DEBUG_IN_EP,
312 "%s: ep_num = %d, completing request\n",
315 dev->ep0state = WAIT_FOR_SETUP;
316 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
317 debug_cond(DEBUG_IN_EP,
318 "%s: ep_num = %d, completing request\n",
321 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
322 dwc2_ep0_complete_out();
324 debug_cond(DEBUG_IN_EP,
325 "%s: ep_num = %d, invalid ep state\n",
331 if (req->req.actual == req->req.length)
334 if (!list_empty(&ep->queue)) {
335 req = list_entry(ep->queue.next, struct dwc2_request, queue);
336 debug_cond(DEBUG_IN_EP,
337 "%s: Next Tx request start...\n", __func__);
342 static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num)
344 struct dwc2_ep *ep = &dev->ep[ep_num];
345 struct dwc2_request *req;
347 debug_cond(DEBUG_IN_EP,
348 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
350 if (!list_empty(&ep->queue)) {
351 req = list_entry(ep->queue.next, struct dwc2_request, queue);
352 debug_cond(DEBUG_IN_EP,
353 "%s: Next Tx request(0x%p) start...\n",
361 debug_cond(DEBUG_IN_EP,
362 "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
369 static void process_ep_in_intr(struct dwc2_udc *dev)
371 u32 ep_intr, ep_intr_status;
374 ep_intr = readl(®->daint);
375 debug_cond(DEBUG_IN_EP,
376 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
378 ep_intr &= DAINT_MASK;
381 if (ep_intr & DAINT_IN_EP_INT(1)) {
382 ep_intr_status = readl(®->in_endp[ep_num].diepint);
383 debug_cond(DEBUG_IN_EP,
384 "\tEP%d-IN : DIEPINT = 0x%x\n",
385 ep_num, ep_intr_status);
387 /* Interrupt Clear */
388 writel(ep_intr_status, ®->in_endp[ep_num].diepint);
390 if (ep_intr_status & TRANSFER_DONE) {
391 complete_tx(dev, ep_num);
395 WAIT_FOR_IN_COMPLETE)
396 dev->ep0state = WAIT_FOR_SETUP;
398 if (dev->ep0state == WAIT_FOR_SETUP)
399 dwc2_udc_pre_setup();
401 /* continue transfer after
402 set_clear_halt for DMA mode */
403 if (clear_feature_flag == 1) {
404 dwc2_udc_check_tx_queue(dev,
406 clear_feature_flag = 0;
416 static void process_ep_out_intr(struct dwc2_udc *dev)
418 u32 ep_intr, ep_intr_status;
421 ep_intr = readl(®->daint);
422 debug_cond(DEBUG_OUT_EP != 0,
423 "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
426 ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
430 ep_intr_status = readl(®->out_endp[ep_num].doepint);
431 debug_cond(DEBUG_OUT_EP != 0,
432 "\tEP%d-OUT : DOEPINT = 0x%x\n",
433 ep_num, ep_intr_status);
435 /* Interrupt Clear */
436 writel(ep_intr_status, ®->out_endp[ep_num].doepint);
439 if (ep_intr_status & TRANSFER_DONE) {
441 WAIT_FOR_OUT_COMPLETE)
442 complete_rx(dev, ep_num);
444 dev->ep0state = WAIT_FOR_SETUP;
445 dwc2_udc_pre_setup();
450 CTRL_OUT_EP_SETUP_PHASE_DONE) {
451 debug_cond(DEBUG_OUT_EP != 0,
452 "SETUP packet arrived\n");
453 dwc2_handle_ep0(dev);
456 if (ep_intr_status & TRANSFER_DONE)
457 complete_rx(dev, ep_num);
466 * usb client interrupt handler.
468 static int dwc2_udc_irq(int irq, void *_dev)
470 struct dwc2_udc *dev = _dev;
472 u32 usb_status, gintmsk;
473 unsigned long flags = 0;
475 spin_lock_irqsave(&dev->lock, flags);
477 intr_status = readl(®->gintsts);
478 gintmsk = readl(®->gintmsk);
480 debug_cond(DEBUG_ISR,
481 "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
482 "DAINT : 0x%x, DAINTMSK : 0x%x\n",
483 __func__, intr_status, state_names[dev->ep0state], gintmsk,
484 readl(®->daint), readl(®->daintmsk));
487 spin_unlock_irqrestore(&dev->lock, flags);
491 if (intr_status & INT_ENUMDONE) {
492 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
494 writel(INT_ENUMDONE, ®->gintsts);
495 usb_status = (readl(®->dsts) & 0x6);
497 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
498 debug_cond(DEBUG_ISR,
499 "\t\tFull Speed Detection\n");
500 set_max_pktsize(dev, USB_SPEED_FULL);
503 debug_cond(DEBUG_ISR,
504 "\t\tHigh Speed Detection : 0x%x\n",
506 set_max_pktsize(dev, USB_SPEED_HIGH);
510 if (intr_status & INT_EARLY_SUSPEND) {
511 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
512 writel(INT_EARLY_SUSPEND, ®->gintsts);
515 if (intr_status & INT_SUSPEND) {
516 usb_status = readl(®->dsts);
517 debug_cond(DEBUG_ISR,
518 "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
519 writel(INT_SUSPEND, ®->gintsts);
521 if (dev->gadget.speed != USB_SPEED_UNKNOWN
523 if (dev->driver->suspend)
524 dev->driver->suspend(&dev->gadget);
526 /* HACK to let gadget detect disconnected state */
527 if (dev->driver->disconnect) {
528 spin_unlock_irqrestore(&dev->lock, flags);
529 dev->driver->disconnect(&dev->gadget);
530 spin_lock_irqsave(&dev->lock, flags);
535 if (intr_status & INT_RESUME) {
536 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
537 writel(INT_RESUME, ®->gintsts);
539 if (dev->gadget.speed != USB_SPEED_UNKNOWN
541 && dev->driver->resume) {
543 dev->driver->resume(&dev->gadget);
547 if (intr_status & INT_RESET) {
548 usb_status = readl(®->gotgctl);
549 debug_cond(DEBUG_ISR,
550 "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
551 writel(INT_RESET, ®->gintsts);
553 if ((usb_status & 0xc0000) == (0x3 << 18)) {
554 if (reset_available) {
555 debug_cond(DEBUG_ISR,
556 "\t\tOTG core got reset (%d)!!\n",
559 dev->ep0state = WAIT_FOR_SETUP;
561 dwc2_udc_pre_setup();
567 debug_cond(DEBUG_ISR,
568 "\t\tRESET handling skipped\n");
572 if (intr_status & INT_IN_EP)
573 process_ep_in_intr(dev);
575 if (intr_status & INT_OUT_EP)
576 process_ep_out_intr(dev);
578 spin_unlock_irqrestore(&dev->lock, flags);
583 /** Queue one request
584 * Kickstart transfer if needed
586 static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req,
589 struct dwc2_request *req;
591 struct dwc2_udc *dev;
592 unsigned long flags = 0;
595 req = container_of(_req, struct dwc2_request, req);
596 if (unlikely(!_req || !_req->complete || !_req->buf
597 || !list_empty(&req->queue))) {
599 debug("%s: bad params\n", __func__);
603 ep = container_of(_ep, struct dwc2_ep, ep);
605 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
607 debug("%s: bad ep: %s, %d, %p\n", __func__,
608 ep->ep.name, !ep->desc, _ep);
612 ep_num = ep_index(ep);
614 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
616 debug("%s: bogus device state %p\n", __func__, dev->driver);
620 spin_lock_irqsave(&dev->lock, flags);
622 _req->status = -EINPROGRESS;
625 /* kickstart this i/o queue? */
626 debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
627 "Q empty = %d, stopped = %d\n",
628 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
629 _req, _req->length, _req->buf,
630 list_empty(&ep->queue), ep->stopped);
634 int i, len = _req->length;
639 for (i = 0; i < len; i++) {
640 printf("%02x", ((u8 *)_req->buf)[i]);
648 if (list_empty(&ep->queue) && !ep->stopped) {
652 list_add_tail(&req->queue, &ep->queue);
653 dwc2_ep0_kick(dev, ep);
656 } else if (ep_is_in(ep)) {
657 gintsts = readl(®->gintsts);
658 debug_cond(DEBUG_IN_EP,
659 "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n",
664 gintsts = readl(®->gintsts);
665 debug_cond(DEBUG_OUT_EP != 0,
666 "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n",
673 /* pio or dma irq handler advances the queue. */
674 if (likely(req != 0))
675 list_add_tail(&req->queue, &ep->queue);
677 spin_unlock_irqrestore(&dev->lock, flags);
682 /****************************************************************/
683 /* End Point 0 related functions */
684 /****************************************************************/
686 /* return: 0 = still running, 1 = completed, negative = errno */
687 static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req)
693 max = ep_maxpacket(ep);
695 debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
697 count = setdma_tx(ep, req);
699 /* last packet is usually short (or a zlp) */
700 if (likely(count != max))
703 if (likely(req->req.length != req->req.actual + count)
710 debug_cond(DEBUG_EP0 != 0,
711 "%s: wrote %s %d bytes%s %d left %p\n", __func__,
714 req->req.length - req->req.actual - count, req);
716 /* requests complete when all IN data is in the FIFO */
718 ep->dev->ep0state = WAIT_FOR_SETUP;
725 static int dwc2_fifo_read(struct dwc2_ep *ep, u32 *cp, int max)
727 invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
728 ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
730 debug_cond(DEBUG_EP0 != 0,
731 "%s: bytes=%d, ep_index=%d 0x%p\n", __func__,
732 max, ep_index(ep), cp);
738 * udc_set_address - set the USB address for this device
741 * Called from control endpoint function
742 * after it decodes a set address setup packet.
744 static void udc_set_address(struct dwc2_udc *dev, unsigned char address)
746 u32 ctrl = readl(®->dcfg);
747 writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg);
749 dwc2_udc_ep0_zlp(dev);
751 debug_cond(DEBUG_EP0 != 0,
752 "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
753 __func__, address, readl(®->dcfg));
755 dev->usb_address = address;
758 static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep)
760 struct dwc2_udc *dev;
764 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
766 /* set the disable and stall bits */
767 if (ep_ctrl & DEPCTL_EPENA)
768 ep_ctrl |= DEPCTL_EPDIS;
770 ep_ctrl |= DEPCTL_STALL;
772 writel(ep_ctrl, ®->in_endp[EP0_CON].diepctl);
774 debug_cond(DEBUG_EP0 != 0,
775 "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
776 __func__, ep_index(ep), ®->in_endp[EP0_CON].diepctl);
778 * The application can only set this bit, and the core clears it,
779 * when a SETUP token is received for this endpoint
781 dev->ep0state = WAIT_FOR_SETUP;
783 dwc2_udc_pre_setup();
786 static void dwc2_ep0_read(struct dwc2_udc *dev)
788 struct dwc2_request *req;
789 struct dwc2_ep *ep = &dev->ep[0];
791 if (!list_empty(&ep->queue)) {
792 req = list_entry(ep->queue.next, struct dwc2_request, queue);
795 debug("%s: ---> BUG\n", __func__);
800 debug_cond(DEBUG_EP0 != 0,
801 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
802 __func__, req, req->req.length, req->req.actual);
804 if (req->req.length == 0) {
805 /* zlp for Set_configuration, Set_interface,
806 * or Bulk-Only mass storge reset */
809 dwc2_udc_ep0_zlp(dev);
811 debug_cond(DEBUG_EP0 != 0,
812 "%s: req.length = 0, bRequest = %d\n",
813 __func__, usb_ctrl->bRequest);
823 static int dwc2_ep0_write(struct dwc2_udc *dev)
825 struct dwc2_request *req;
826 struct dwc2_ep *ep = &dev->ep[0];
827 int ret, need_zlp = 0;
829 if (list_empty(&ep->queue))
832 req = list_entry(ep->queue.next, struct dwc2_request, queue);
835 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
839 debug_cond(DEBUG_EP0 != 0,
840 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
841 __func__, req, req->req.length, req->req.actual);
843 if (req->req.length - req->req.actual == ep0_fifo_size) {
844 /* Next write will end with the packet size, */
845 /* so we need Zero-length-packet */
849 ret = write_fifo_ep0(ep, req);
851 if ((ret == 1) && !need_zlp) {
853 dev->ep0state = WAIT_FOR_COMPLETE;
854 debug_cond(DEBUG_EP0 != 0,
855 "%s: finished, waiting for status\n", __func__);
858 dev->ep0state = DATA_STATE_XMIT;
859 debug_cond(DEBUG_EP0 != 0,
860 "%s: not finished\n", __func__);
866 static int dwc2_udc_get_status(struct dwc2_udc *dev,
867 struct usb_ctrlrequest *crq)
869 u8 ep_num = crq->wIndex & 0x7F;
873 debug_cond(DEBUG_SETUP != 0,
874 "%s: *** USB_REQ_GET_STATUS\n", __func__);
875 printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
876 switch (crq->bRequestType & USB_RECIP_MASK) {
877 case USB_RECIP_INTERFACE:
879 debug_cond(DEBUG_SETUP != 0,
880 "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
884 case USB_RECIP_DEVICE:
885 g_status = 0x1; /* Self powered */
886 debug_cond(DEBUG_SETUP != 0,
887 "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
891 case USB_RECIP_ENDPOINT:
892 if (crq->wLength > 2) {
893 debug_cond(DEBUG_SETUP != 0,
894 "\tGET_STATUS:Not support EP or wLength\n");
898 g_status = dev->ep[ep_num].stopped;
899 debug_cond(DEBUG_SETUP != 0,
900 "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
909 memcpy(usb_ctrl, &g_status, sizeof(g_status));
911 flush_dcache_range((unsigned long) usb_ctrl,
912 (unsigned long) usb_ctrl +
913 ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
915 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
916 writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
917 ®->in_endp[EP0_CON].dieptsiz);
919 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
920 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
921 ®->in_endp[EP0_CON].diepctl);
922 dev->ep0state = WAIT_FOR_NULL_COMPLETE;
927 static void dwc2_udc_set_nak(struct dwc2_ep *ep)
932 ep_num = ep_index(ep);
933 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
936 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
937 ep_ctrl |= DEPCTL_SNAK;
938 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
939 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
940 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
942 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
943 ep_ctrl |= DEPCTL_SNAK;
944 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
945 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
946 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
953 static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep)
958 ep_num = ep_index(ep);
959 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
962 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
964 /* set the disable and stall bits */
965 if (ep_ctrl & DEPCTL_EPENA)
966 ep_ctrl |= DEPCTL_EPDIS;
968 ep_ctrl |= DEPCTL_STALL;
970 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
971 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
972 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
975 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
977 /* set the stall bit */
978 ep_ctrl |= DEPCTL_STALL;
980 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
981 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
982 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
988 static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep)
993 ep_num = ep_index(ep);
994 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
997 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
999 /* clear stall bit */
1000 ep_ctrl &= ~DEPCTL_STALL;
1003 * USB Spec 9.4.5: For endpoints using data toggle, regardless
1004 * of whether an endpoint has the Halt feature set, a
1005 * ClearFeature(ENDPOINT_HALT) request always results in the
1006 * data toggle being reinitialized to DATA0.
1008 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1009 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1010 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1013 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1014 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1015 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
1018 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1020 /* clear stall bit */
1021 ep_ctrl &= ~DEPCTL_STALL;
1023 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1024 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1025 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1028 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1029 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1030 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
1036 static int dwc2_udc_set_halt(struct usb_ep *_ep, int value)
1039 struct dwc2_udc *dev;
1040 unsigned long flags = 0;
1043 ep = container_of(_ep, struct dwc2_ep, ep);
1044 ep_num = ep_index(ep);
1046 if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1047 ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1048 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1052 /* Attempt to halt IN ep will fail if any transfer requests
1053 * are still queue */
1054 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1055 debug("%s: %s queue not empty, req = %p\n",
1056 __func__, ep->ep.name,
1057 list_entry(ep->queue.next, struct dwc2_request, queue));
1063 debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1065 spin_lock_irqsave(&dev->lock, flags);
1069 dwc2_udc_ep_clear_stall(ep);
1072 dev->ep0state = WAIT_FOR_SETUP;
1075 dwc2_udc_ep_set_stall(ep);
1078 spin_unlock_irqrestore(&dev->lock, flags);
1083 static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
1086 u32 ep_ctrl = 0, daintmsk = 0;
1088 ep_num = ep_index(ep);
1090 /* Read DEPCTLn register */
1092 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1093 daintmsk = 1 << ep_num;
1095 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1096 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1099 debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1100 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1102 /* If the EP is already active don't change the EP Control
1104 if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1105 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1106 (ep->bmAttributes << DEPCTL_TYPE_BIT);
1107 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1108 (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1109 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1112 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1113 debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1114 __func__, ep_num, ep_num,
1115 readl(®->in_endp[ep_num].diepctl));
1117 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1118 debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1119 __func__, ep_num, ep_num,
1120 readl(®->out_endp[ep_num].doepctl));
1124 /* Unmask EP Interrtupt */
1125 writel(readl(®->daintmsk)|daintmsk, ®->daintmsk);
1126 debug("%s: DAINTMSK = 0x%x\n", __func__, readl(®->daintmsk));
1130 static int dwc2_udc_clear_feature(struct usb_ep *_ep)
1132 struct dwc2_udc *dev;
1136 ep = container_of(_ep, struct dwc2_ep, ep);
1137 ep_num = ep_index(ep);
1140 debug_cond(DEBUG_SETUP != 0,
1141 "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1142 __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1144 if (usb_ctrl->wLength != 0) {
1145 debug_cond(DEBUG_SETUP != 0,
1146 "\tCLEAR_FEATURE: wLength is not zero.....\n");
1150 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1151 case USB_RECIP_DEVICE:
1152 switch (usb_ctrl->wValue) {
1153 case USB_DEVICE_REMOTE_WAKEUP:
1154 debug_cond(DEBUG_SETUP != 0,
1155 "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1158 case USB_DEVICE_TEST_MODE:
1159 debug_cond(DEBUG_SETUP != 0,
1160 "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1161 /** @todo Add CLEAR_FEATURE for TEST modes. */
1165 dwc2_udc_ep0_zlp(dev);
1168 case USB_RECIP_ENDPOINT:
1169 debug_cond(DEBUG_SETUP != 0,
1170 "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1173 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1175 dwc2_udc_ep0_set_stall(ep);
1179 dwc2_udc_ep0_zlp(dev);
1181 dwc2_udc_ep_clear_stall(ep);
1182 dwc2_udc_ep_activate(ep);
1185 clear_feature_num = ep_num;
1186 clear_feature_flag = 1;
1194 static int dwc2_udc_set_feature(struct usb_ep *_ep)
1196 struct dwc2_udc *dev;
1200 ep = container_of(_ep, struct dwc2_ep, ep);
1201 ep_num = ep_index(ep);
1204 debug_cond(DEBUG_SETUP != 0,
1205 "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1208 if (usb_ctrl->wLength != 0) {
1209 debug_cond(DEBUG_SETUP != 0,
1210 "\tSET_FEATURE: wLength is not zero.....\n");
1214 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1215 case USB_RECIP_DEVICE:
1216 switch (usb_ctrl->wValue) {
1217 case USB_DEVICE_REMOTE_WAKEUP:
1218 debug_cond(DEBUG_SETUP != 0,
1219 "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1221 case USB_DEVICE_B_HNP_ENABLE:
1222 debug_cond(DEBUG_SETUP != 0,
1223 "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1226 case USB_DEVICE_A_HNP_SUPPORT:
1227 /* RH port supports HNP */
1228 debug_cond(DEBUG_SETUP != 0,
1229 "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1232 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1233 /* other RH port does */
1234 debug_cond(DEBUG_SETUP != 0,
1235 "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1239 dwc2_udc_ep0_zlp(dev);
1242 case USB_RECIP_INTERFACE:
1243 debug_cond(DEBUG_SETUP != 0,
1244 "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1247 case USB_RECIP_ENDPOINT:
1248 debug_cond(DEBUG_SETUP != 0,
1249 "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1250 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1252 dwc2_udc_ep0_set_stall(ep);
1256 dwc2_udc_ep_set_stall(ep);
1259 dwc2_udc_ep0_zlp(dev);
1267 * WAIT_FOR_SETUP (OUT_PKT_RDY)
1269 static void dwc2_ep0_setup(struct dwc2_udc *dev)
1271 struct dwc2_ep *ep = &dev->ep[0];
1275 /* Nuke all previous transfers */
1278 /* read control req from fifo (8 bytes) */
1279 dwc2_fifo_read(ep, (u32 *)usb_ctrl, 8);
1281 debug_cond(DEBUG_SETUP != 0,
1282 "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1283 "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1284 __func__, usb_ctrl->bRequestType,
1285 (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1287 usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1291 int i, len = sizeof(*usb_ctrl);
1292 char *p = (char *)usb_ctrl;
1295 for (i = 0; i < len; i++) {
1296 printf("%02x", ((u8 *)p)[i]);
1304 if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1305 usb_ctrl->wLength != 1) {
1306 debug_cond(DEBUG_SETUP != 0,
1307 "\t%s:GET_MAX_LUN_REQUEST:invalid",
1309 debug_cond(DEBUG_SETUP != 0,
1310 "wLength = %d, setup returned\n",
1313 dwc2_udc_ep0_set_stall(ep);
1314 dev->ep0state = WAIT_FOR_SETUP;
1317 } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1318 usb_ctrl->wLength != 0) {
1319 /* Bulk-Only *mass storge reset of class-specific request */
1320 debug_cond(DEBUG_SETUP != 0,
1321 "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1322 __func__, usb_ctrl->wLength);
1324 dwc2_udc_ep0_set_stall(ep);
1325 dev->ep0state = WAIT_FOR_SETUP;
1330 /* Set direction of EP0 */
1331 if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1332 ep->bEndpointAddress |= USB_DIR_IN;
1334 ep->bEndpointAddress &= ~USB_DIR_IN;
1336 /* cope with automagic for some standard requests. */
1337 dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1338 == USB_TYPE_STANDARD;
1340 dev->req_pending = 1;
1342 /* Handle some SETUP packets ourselves */
1344 switch (usb_ctrl->bRequest) {
1345 case USB_REQ_SET_ADDRESS:
1346 debug_cond(DEBUG_SETUP != 0,
1347 "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1348 __func__, usb_ctrl->wValue);
1349 if (usb_ctrl->bRequestType
1350 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1353 udc_set_address(dev, usb_ctrl->wValue);
1356 case USB_REQ_SET_CONFIGURATION:
1357 debug_cond(DEBUG_SETUP != 0,
1358 "=====================================\n");
1359 debug_cond(DEBUG_SETUP != 0,
1360 "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1361 __func__, usb_ctrl->wValue);
1363 if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1364 reset_available = 1;
1368 case USB_REQ_GET_DESCRIPTOR:
1369 debug_cond(DEBUG_SETUP != 0,
1370 "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1374 case USB_REQ_SET_INTERFACE:
1375 debug_cond(DEBUG_SETUP != 0,
1376 "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1377 __func__, usb_ctrl->wValue);
1379 if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1380 reset_available = 1;
1384 case USB_REQ_GET_CONFIGURATION:
1385 debug_cond(DEBUG_SETUP != 0,
1386 "%s: *** USB_REQ_GET_CONFIGURATION\n",
1390 case USB_REQ_GET_STATUS:
1391 if (!dwc2_udc_get_status(dev, usb_ctrl))
1396 case USB_REQ_CLEAR_FEATURE:
1397 ep_num = usb_ctrl->wIndex & 0x7f;
1399 if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep))
1404 case USB_REQ_SET_FEATURE:
1405 ep_num = usb_ctrl->wIndex & 0x7f;
1407 if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep))
1413 debug_cond(DEBUG_SETUP != 0,
1414 "%s: *** Default of usb_ctrl->bRequest=0x%x"
1415 "happened.\n", __func__, usb_ctrl->bRequest);
1421 if (likely(dev->driver)) {
1422 /* device-2-host (IN) or no data setup command,
1423 * process immediately */
1424 debug_cond(DEBUG_SETUP != 0,
1425 "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1428 spin_unlock(&dev->lock);
1429 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1430 spin_lock(&dev->lock);
1433 /* setup processing failed, force stall */
1434 dwc2_udc_ep0_set_stall(ep);
1435 dev->ep0state = WAIT_FOR_SETUP;
1437 debug_cond(DEBUG_SETUP != 0,
1438 "\tdev->driver->setup failed (%d),"
1440 i, usb_ctrl->bRequest);
1443 } else if (dev->req_pending) {
1444 dev->req_pending = 0;
1445 debug_cond(DEBUG_SETUP != 0,
1446 "\tdev->req_pending...\n");
1449 debug_cond(DEBUG_SETUP != 0,
1450 "\tep0state = %s\n", state_names[dev->ep0state]);
1456 * handle ep0 interrupt
1458 static void dwc2_handle_ep0(struct dwc2_udc *dev)
1460 if (dev->ep0state == WAIT_FOR_SETUP) {
1461 debug_cond(DEBUG_OUT_EP != 0,
1462 "%s: WAIT_FOR_SETUP\n", __func__);
1463 dwc2_ep0_setup(dev);
1466 debug_cond(DEBUG_OUT_EP != 0,
1467 "%s: strange state!!(state = %s)\n",
1468 __func__, state_names[dev->ep0state]);
1472 static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep)
1474 debug_cond(DEBUG_EP0 != 0,
1475 "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1477 dev->ep0state = DATA_STATE_XMIT;
1478 dwc2_ep0_write(dev);
1481 dev->ep0state = DATA_STATE_RECV;