1 // SPDX-License-Identifier: GPL-2.0+
3 * Based on drivers/usb/gadget/omap1510_udc.c
4 * TI OMAP1510 USB bus interface driver
7 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
15 #include <usbdevice.h>
17 #include <usb/designware_udc.h>
19 #include <asm/arch/hardware.h>
21 #define UDC_INIT_MDELAY 80 /* Device settle delay */
23 /* Some kind of debugging output... */
24 #ifndef DEBUG_DWUSBTTY
26 #define UDCDBGA(fmt, args...)
28 #define UDCDBG(str) serial_printf(str "\n")
29 #define UDCDBGA(fmt, args...) serial_printf(fmt "\n", ##args)
32 static struct urb *ep0_urb;
33 static struct usb_device_instance *udc_device;
35 static struct plug_regs *const plug_regs_p =
36 (struct plug_regs * const)CONFIG_SYS_PLUG_BASE;
37 static struct udc_regs *const udc_regs_p =
38 (struct udc_regs * const)CONFIG_SYS_USBD_BASE;
39 static struct udc_endp_regs *const outep_regs_p =
40 &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->out_regs[0];
41 static struct udc_endp_regs *const inep_regs_p =
42 &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->in_regs[0];
45 * udc_state_transition - Write the next packet to TxFIFO.
46 * @initial: Initial state.
47 * @final: Final state.
49 * Helper function to implement device state changes. The device states and
50 * the events that transition between them are:
55 * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET
61 * DEVICE_RESET DEVICE_POWER_INTERRUPTION
67 * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET
73 * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED
78 * udc_state_transition transitions up (in the direction from STATE_ATTACHED
79 * to STATE_CONFIGURED) from the specified initial state to the specified final
80 * state, passing through each intermediate state on the way. If the initial
81 * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then
82 * no state transitions will take place.
84 * udc_state_transition also transitions down (in the direction from
85 * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the
86 * specified final state, passing through each intermediate state on the way.
87 * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final
88 * state, then no state transitions will take place.
90 * This function must only be called with interrupts disabled.
92 static void udc_state_transition(usb_device_state_t initial,
93 usb_device_state_t final)
95 if (initial < final) {
98 usbd_device_event_irq(udc_device,
99 DEVICE_HUB_CONFIGURED, 0);
100 if (final == STATE_POWERED)
103 usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
104 if (final == STATE_DEFAULT)
107 usbd_device_event_irq(udc_device,
108 DEVICE_ADDRESS_ASSIGNED, 0);
109 if (final == STATE_ADDRESSED)
111 case STATE_ADDRESSED:
112 usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0);
113 case STATE_CONFIGURED:
118 } else if (initial > final) {
120 case STATE_CONFIGURED:
121 usbd_device_event_irq(udc_device,
122 DEVICE_DE_CONFIGURED, 0);
123 if (final == STATE_ADDRESSED)
125 case STATE_ADDRESSED:
126 usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
127 if (final == STATE_DEFAULT)
130 usbd_device_event_irq(udc_device,
131 DEVICE_POWER_INTERRUPTION, 0);
132 if (final == STATE_POWERED)
135 usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0);
145 static void udc_stall_ep(u32 ep_num)
147 writel(readl(&inep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL,
148 &inep_regs_p[ep_num].endp_cntl);
150 writel(readl(&outep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL,
151 &outep_regs_p[ep_num].endp_cntl);
154 static void *get_fifo(int ep_num, int in)
156 u32 *fifo_ptr = (u32 *)CONFIG_SYS_FIFO_BASE;
160 fifo_ptr += readl(&inep_regs_p[1].endp_bsorfn);
161 /* break intentionally left out */
164 fifo_ptr += readl(&inep_regs_p[0].endp_bsorfn);
165 /* break intentionally left out */
171 readl(&outep_regs_p[2].endp_maxpacksize) >> 16;
172 /* break intentionally left out */
178 fifo_ptr += readl(&outep_regs_p[0].endp_maxpacksize) >> 16;
179 /* break intentionally left out */
182 return (void *)fifo_ptr;
185 static int usbgetpckfromfifo(int epNum, u8 *bufp, u32 len)
187 u8 *fifo_ptr = (u8 *)get_fifo(epNum, 0);
193 if (readl(&udc_regs_p->dev_stat) & DEV_STAT_RXFIFO_EMPTY)
196 nw = len / sizeof(u32);
197 nb = len % sizeof(u32);
199 /* use tmp buf if bufp is not word aligned */
201 wrdp = (u32 *)&tmp[0];
205 for (i = 0; i < nw; i++) {
206 writel(readl(fifo_ptr), wrdp);
211 for (i = 0; i < nb; i++) {
212 writeb(readb(fifo_ptr), bytp);
216 readl(&outep_regs_p[epNum].write_done);
218 /* copy back tmp buffer to bufp if bufp is not word aligned */
220 memcpy(bufp, tmp, len);
225 static void usbputpcktofifo(int epNum, u8 *bufp, u32 len)
230 u8 *fifo_ptr = get_fifo(epNum, 1);
232 nw = len / sizeof(int);
233 nb = len % sizeof(int);
235 for (i = 0; i < nw; i++) {
236 writel(*wrdp, fifo_ptr);
241 for (i = 0; i < nb; i++) {
242 writeb(*bytp, fifo_ptr);
249 * dw_write_noniso_tx_fifo - Write the next packet to TxFIFO.
250 * @endpoint: Endpoint pointer.
252 * If the endpoint has an active tx_urb, then the next packet of data from the
253 * URB is written to the tx FIFO. The total amount of data in the urb is given
254 * by urb->actual_length. The maximum amount of data that can be sent in any
255 * one packet is given by endpoint->tx_packetSize. The number of data bytes
256 * from this URB that have already been transmitted is given by endpoint->sent.
257 * endpoint->last is updated by this routine with the number of data bytes
258 * transmitted in this packet.
261 static void dw_write_noniso_tx_fifo(struct usb_endpoint_instance
264 struct urb *urb = endpoint->tx_urb;
270 UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d",
271 urb->buffer, urb->buffer_length, urb->actual_length);
273 last = min_t(u32, urb->actual_length - endpoint->sent,
274 endpoint->tx_packetSize);
277 u8 *cp = urb->buffer + endpoint->sent;
280 * This ensures that USBD packet fifo is accessed
281 * - through word aligned pointer or
282 * - through non word aligned pointer but only
283 * with a max length to make the next packet
287 align = ((ulong)cp % sizeof(int));
289 last = min(last, sizeof(int) - align);
291 UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d",
292 endpoint->sent, endpoint->tx_packetSize, last);
294 usbputpcktofifo(endpoint->endpoint_address &
295 USB_ENDPOINT_NUMBER_MASK, cp, last);
297 endpoint->last = last;
302 * Handle SETUP USB interrupt.
303 * This function implements TRM Figure 14-14.
305 static void dw_udc_setup(struct usb_endpoint_instance *endpoint)
307 u8 *datap = (u8 *)&ep0_urb->device_request;
308 int ep_addr = endpoint->endpoint_address;
310 UDCDBG("-> Entering device setup");
311 usbgetpckfromfifo(ep_addr, datap, 8);
313 /* Try to process setup packet */
314 if (ep0_recv_setup(ep0_urb)) {
315 /* Not a setup packet, stall next EP0 transaction */
317 UDCDBG("can't parse setup packet, still waiting for setup");
321 /* Check direction */
322 if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK)
323 == USB_REQ_HOST2DEVICE) {
324 UDCDBG("control write on EP0");
325 if (le16_to_cpu(ep0_urb->device_request.wLength)) {
326 /* Stall this request */
327 UDCDBG("Stalling unsupported EP0 control write data "
333 UDCDBG("control read on EP0");
335 * The ep0_recv_setup function has already placed our response
336 * packet data in ep0_urb->buffer and the packet length in
337 * ep0_urb->actual_length.
339 endpoint->tx_urb = ep0_urb;
342 * Write packet data to the FIFO. dw_write_noniso_tx_fifo
343 * will update endpoint->last with the number of bytes written
346 dw_write_noniso_tx_fifo(endpoint);
348 writel(0x0, &inep_regs_p[ep_addr].write_done);
351 udc_unset_nak(endpoint->endpoint_address);
353 UDCDBG("<- Leaving device setup");
357 * Handle endpoint 0 RX interrupt
359 static void dw_udc_ep0_rx(struct usb_endpoint_instance *endpoint)
365 /* Check direction */
366 if ((ep0_urb->device_request.bmRequestType
367 & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) {
369 * This rx interrupt must be for a control write data
372 * We don't support control write data stages.
373 * We should never end up here.
376 UDCDBG("Stalling unexpected EP0 control write "
377 "data stage packet");
381 * This rx interrupt must be for a control read status
384 UDCDBG("ACK on EP0 control read status stage packet");
385 u32 len = (readl(&outep_regs_p[0].endp_status) >> 11) & 0xfff;
386 usbgetpckfromfifo(0, dummy, len);
391 * Handle endpoint 0 TX interrupt
393 static void dw_udc_ep0_tx(struct usb_endpoint_instance *endpoint)
395 struct usb_device_request *request = &ep0_urb->device_request;
400 /* Check direction */
401 if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) ==
402 USB_REQ_HOST2DEVICE) {
404 * This tx interrupt must be for a control write status
407 UDCDBG("ACK on EP0 control write status stage packet");
410 * This tx interrupt must be for a control read data
413 int wLength = le16_to_cpu(request->wLength);
416 * Update our count of bytes sent so far in this
419 endpoint->sent += endpoint->last;
422 * We are finished with this transfer if we have sent
423 * all of the bytes in our tx urb (urb->actual_length)
424 * unless we need a zero-length terminating packet. We
425 * need a zero-length terminating packet if we returned
426 * fewer bytes than were requested (wLength) by the host,
427 * and the number of bytes we returned is an exact
428 * multiple of the packet size endpoint->tx_packetSize.
430 if ((endpoint->sent == ep0_urb->actual_length) &&
431 ((ep0_urb->actual_length == wLength) ||
432 (endpoint->last != endpoint->tx_packetSize))) {
433 /* Done with control read data stage. */
434 UDCDBG("control read data stage complete");
437 * We still have another packet of data to send
438 * in this control read data stage or else we
439 * need a zero-length terminating packet.
441 UDCDBG("ACK control read data stage packet");
442 dw_write_noniso_tx_fifo(endpoint);
444 ep_addr = endpoint->endpoint_address;
445 writel(0x0, &inep_regs_p[ep_addr].write_done);
450 static struct usb_endpoint_instance *dw_find_ep(int ep)
454 for (i = 0; i < udc_device->bus->max_endpoints; i++) {
455 if ((udc_device->bus->endpoint_array[i].endpoint_address &
456 USB_ENDPOINT_NUMBER_MASK) == ep)
457 return &udc_device->bus->endpoint_array[i];
463 * Handle RX transaction on non-ISO endpoint.
464 * The ep argument is a physical endpoint number for a non-ISO IN endpoint
465 * in the range 1 to 15.
467 static void dw_udc_epn_rx(int ep)
471 struct usb_endpoint_instance *endpoint = dw_find_ep(ep);
474 urb = endpoint->rcv_urb;
477 u8 *cp = urb->buffer + urb->actual_length;
479 nbytes = (readl(&outep_regs_p[ep].endp_status) >> 11) &
481 usbgetpckfromfifo(ep, cp, nbytes);
482 usbd_rcv_complete(endpoint, nbytes, 0);
488 * Handle TX transaction on non-ISO endpoint.
489 * The ep argument is a physical endpoint number for a non-ISO IN endpoint
490 * in the range 16 to 30.
492 static void dw_udc_epn_tx(int ep)
494 struct usb_endpoint_instance *endpoint = dw_find_ep(ep);
500 * We need to transmit a terminating zero-length packet now if
501 * we have sent all of the data in this URB and the transfer
502 * size was an exact multiple of the packet size.
504 if (endpoint->tx_urb &&
505 (endpoint->last == endpoint->tx_packetSize) &&
506 (endpoint->tx_urb->actual_length - endpoint->sent -
507 endpoint->last == 0)) {
508 /* handle zero length packet here */
509 writel(0x0, &inep_regs_p[ep].write_done);
513 if (endpoint->tx_urb && endpoint->tx_urb->actual_length) {
514 /* retire the data that was just sent */
515 usbd_tx_complete(endpoint);
517 * Check to see if we have more data ready to transmit
520 if (endpoint->tx_urb && endpoint->tx_urb->actual_length) {
521 /* write data to FIFO */
522 dw_write_noniso_tx_fifo(endpoint);
523 writel(0x0, &inep_regs_p[ep].write_done);
525 } else if (endpoint->tx_urb
526 && (endpoint->tx_urb->actual_length == 0)) {
527 /* udc_set_nak(ep); */
533 * Start of public functions.
536 /* Called to start packet transmission. */
537 int udc_endpoint_write(struct usb_endpoint_instance *endpoint)
539 udc_unset_nak(endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK);
543 /* Start to initialize h/w stuff */
553 readl(&plug_regs_p->plug_pending);
555 for (i = 0; i < UDC_INIT_MDELAY; i++)
558 plug_st = readl(&plug_regs_p->plug_state);
559 writel(plug_st | PLUG_STATUS_EN, &plug_regs_p->plug_state);
561 writel(~0x0, &udc_regs_p->endp_int);
562 writel(~0x0, &udc_regs_p->dev_int_mask);
563 writel(~0x0, &udc_regs_p->endp_int_mask);
565 #ifndef CONFIG_USBD_HS
566 writel(DEV_CONF_FS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW |
567 DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf);
569 writel(DEV_CONF_HS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW |
570 DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf);
573 writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl);
575 /* Clear all interrupts pending */
576 writel(DEV_INT_MSK, &udc_regs_p->dev_int);
581 int is_usbd_high_speed(void)
583 return (readl(&udc_regs_p->dev_stat) & DEV_STAT_ENUM) ? 0 : 1;
587 * udc_setup_ep - setup endpoint
588 * Associate a physical endpoint with endpoint_instance
590 void udc_setup_ep(struct usb_device_instance *device,
591 u32 ep, struct usb_endpoint_instance *endpoint)
593 UDCDBGA("setting up endpoint addr %x", endpoint->endpoint_address);
602 if ((ep != 0) && (udc_device->device_state < STATE_ADDRESSED))
605 tt = env_get("usbtty");
609 ep_addr = endpoint->endpoint_address;
610 ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
612 if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
614 packet_size = endpoint->tx_packetSize;
615 buffer_size = packet_size * 2;
616 attributes = endpoint->tx_attributes;
619 packet_size = endpoint->rcv_packetSize;
620 buffer_size = packet_size * 2;
621 attributes = endpoint->rcv_attributes;
624 switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) {
625 case USB_ENDPOINT_XFER_CONTROL:
626 ep_type = ENDP_EPTYPE_CNTL;
628 case USB_ENDPOINT_XFER_BULK:
630 ep_type = ENDP_EPTYPE_BULK;
632 case USB_ENDPOINT_XFER_INT:
633 ep_type = ENDP_EPTYPE_INT;
635 case USB_ENDPOINT_XFER_ISOC:
636 ep_type = ENDP_EPTYPE_ISO;
640 struct udc_endp_regs *out_p = &outep_regs_p[ep_num];
641 struct udc_endp_regs *in_p = &inep_regs_p[ep_num];
644 /* Setup endpoint 0 */
645 buffer_size = packet_size;
647 writel(readl(&in_p->endp_cntl) | ENDP_CNTL_CNAK,
650 writel(readl(&out_p->endp_cntl) | ENDP_CNTL_CNAK,
653 writel(ENDP_CNTL_CONTROL | ENDP_CNTL_FLUSH, &in_p->endp_cntl);
655 writel(buffer_size / sizeof(int), &in_p->endp_bsorfn);
657 writel(packet_size, &in_p->endp_maxpacksize);
659 writel(ENDP_CNTL_CONTROL | ENDP_CNTL_RRDY, &out_p->endp_cntl);
661 writel(packet_size | ((buffer_size / sizeof(int)) << 16),
662 &out_p->endp_maxpacksize);
664 } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
665 /* Setup the IN endpoint */
666 writel(0x0, &in_p->endp_status);
667 writel((ep_type << 4) | ENDP_CNTL_RRDY, &in_p->endp_cntl);
668 writel(buffer_size / sizeof(int), &in_p->endp_bsorfn);
669 writel(packet_size, &in_p->endp_maxpacksize);
671 if (!strcmp(tt, "cdc_acm")) {
672 if (ep_type == ENDP_EPTYPE_INT) {
673 /* Conf no. 1 Interface no. 0 */
674 writel((packet_size << 19) |
675 ENDP_EPDIR_IN | (1 << 7) |
676 (0 << 11) | (ep_type << 5) | ep_num,
677 &udc_regs_p->udc_endp_reg[ep_num]);
679 /* Conf no. 1 Interface no. 1 */
680 writel((packet_size << 19) |
681 ENDP_EPDIR_IN | (1 << 7) |
682 (1 << 11) | (ep_type << 5) | ep_num,
683 &udc_regs_p->udc_endp_reg[ep_num]);
686 /* Conf no. 1 Interface no. 0 */
687 writel((packet_size << 19) |
688 ENDP_EPDIR_IN | (1 << 7) |
689 (0 << 11) | (ep_type << 5) | ep_num,
690 &udc_regs_p->udc_endp_reg[ep_num]);
694 /* Setup the OUT endpoint */
695 writel(0x0, &out_p->endp_status);
696 writel((ep_type << 4) | ENDP_CNTL_RRDY, &out_p->endp_cntl);
697 writel(packet_size | ((buffer_size / sizeof(int)) << 16),
698 &out_p->endp_maxpacksize);
700 if (!strcmp(tt, "cdc_acm")) {
701 writel((packet_size << 19) |
702 ENDP_EPDIR_OUT | (1 << 7) |
703 (1 << 11) | (ep_type << 5) | ep_num,
704 &udc_regs_p->udc_endp_reg[ep_num]);
706 writel((packet_size << 19) |
707 ENDP_EPDIR_OUT | (1 << 7) |
708 (0 << 11) | (ep_type << 5) | ep_num,
709 &udc_regs_p->udc_endp_reg[ep_num]);
714 endp_intmask = readl(&udc_regs_p->endp_int_mask);
715 endp_intmask &= ~((1 << ep_num) | 0x10000 << ep_num);
716 writel(endp_intmask, &udc_regs_p->endp_int_mask);
719 /* Turn on the USB connection by enabling the pullup resistor */
720 void udc_connect(void)
722 u32 plug_st, dev_cntl;
724 dev_cntl = readl(&udc_regs_p->dev_cntl);
725 dev_cntl |= DEV_CNTL_SOFTDISCONNECT;
726 writel(dev_cntl, &udc_regs_p->dev_cntl);
730 dev_cntl = readl(&udc_regs_p->dev_cntl);
731 dev_cntl &= ~DEV_CNTL_SOFTDISCONNECT;
732 writel(dev_cntl, &udc_regs_p->dev_cntl);
734 plug_st = readl(&plug_regs_p->plug_state);
735 plug_st &= ~(PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE);
736 writel(plug_st, &plug_regs_p->plug_state);
739 /* Turn off the USB connection by disabling the pullup resistor */
740 void udc_disconnect(void)
744 writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl);
746 plug_st = readl(&plug_regs_p->plug_state);
747 plug_st |= (PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE);
748 writel(plug_st, &plug_regs_p->plug_state);
751 /* Switch on the UDC */
752 void udc_enable(struct usb_device_instance *device)
754 UDCDBGA("enable device %p, status %d", device, device->status);
756 /* Save the device structure pointer */
762 usbd_alloc_urb(udc_device, udc_device->bus->endpoint_array);
764 serial_printf("udc_enable: ep0_urb already allocated %p\n",
768 writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask);
772 * udc_startup - allow udc code to do any additional startup
774 void udc_startup_events(struct usb_device_instance *device)
776 /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */
777 usbd_device_event_irq(device, DEVICE_INIT, 0);
780 * The DEVICE_CREATE event puts the USB device in the state
783 usbd_device_event_irq(device, DEVICE_CREATE, 0);
786 * Some USB controller driver implementations signal
787 * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here.
788 * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED,
789 * and DEVICE_RESET causes a transition to the state STATE_DEFAULT.
790 * The DW USB client controller has the capability to detect when the
791 * USB cable is connected to a powered USB bus, so we will defer the
792 * DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later.
799 * Plug detection interrupt handling
801 static void dw_udc_plug_irq(void)
803 if (readl(&plug_regs_p->plug_state) & PLUG_STATUS_ATTACHED) {
806 * Turn off PHY reset bit (PLUG detect).
807 * Switch PHY opmode to normal operation (PLUG detect).
810 writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask);
812 UDCDBG("device attached and powered");
813 udc_state_transition(udc_device->device_state, STATE_POWERED);
815 writel(~0x0, &udc_regs_p->dev_int_mask);
817 UDCDBG("device detached or unpowered");
818 udc_state_transition(udc_device->device_state, STATE_ATTACHED);
823 * Device interrupt handling
825 static void dw_udc_dev_irq(void)
827 if (readl(&udc_regs_p->dev_int) & DEV_INT_USBRESET) {
828 writel(~0x0, &udc_regs_p->endp_int_mask);
830 writel(readl(&inep_regs_p[0].endp_cntl) | ENDP_CNTL_FLUSH,
831 &inep_regs_p[0].endp_cntl);
833 writel(DEV_INT_USBRESET, &udc_regs_p->dev_int);
836 * This endpoint0 specific register can be programmed only
837 * after the phy clock is initialized
839 writel((EP0_MAX_PACKET_SIZE << 19) | ENDP_EPTYPE_CNTL,
840 &udc_regs_p->udc_endp_reg[0]);
842 UDCDBG("device reset in progess");
843 udc_state_transition(udc_device->device_state, STATE_DEFAULT);
846 /* Device Enumeration completed */
847 if (readl(&udc_regs_p->dev_int) & DEV_INT_ENUM) {
848 writel(DEV_INT_ENUM, &udc_regs_p->dev_int);
850 /* Endpoint interrupt enabled for Ctrl IN & Ctrl OUT */
851 writel(readl(&udc_regs_p->endp_int_mask) & ~0x10001,
852 &udc_regs_p->endp_int_mask);
854 UDCDBG("default -> addressed");
855 udc_state_transition(udc_device->device_state, STATE_ADDRESSED);
858 /* The USB will be in SUSPEND in 3 ms */
859 if (readl(&udc_regs_p->dev_int) & DEV_INT_INACTIVE) {
860 writel(DEV_INT_INACTIVE, &udc_regs_p->dev_int);
862 UDCDBG("entering inactive state");
863 /* usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); */
866 /* SetConfiguration command received */
867 if (readl(&udc_regs_p->dev_int) & DEV_INT_SETCFG) {
868 writel(DEV_INT_SETCFG, &udc_regs_p->dev_int);
870 UDCDBG("entering configured state");
871 udc_state_transition(udc_device->device_state,
875 /* SetInterface command received */
876 if (readl(&udc_regs_p->dev_int) & DEV_INT_SETINTF)
877 writel(DEV_INT_SETINTF, &udc_regs_p->dev_int);
879 /* USB Suspend detected on cable */
880 if (readl(&udc_regs_p->dev_int) & DEV_INT_SUSPUSB) {
881 writel(DEV_INT_SUSPUSB, &udc_regs_p->dev_int);
883 UDCDBG("entering suspended state");
884 usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0);
887 /* USB Start-Of-Frame detected on cable */
888 if (readl(&udc_regs_p->dev_int) & DEV_INT_SOF)
889 writel(DEV_INT_SOF, &udc_regs_p->dev_int);
893 * Endpoint interrupt handling
895 static void dw_udc_endpoint_irq(void)
897 while (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLOUT) {
899 writel(ENDP0_INT_CTRLOUT, &udc_regs_p->endp_int);
901 if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK)
902 == ENDP_STATUS_OUT_SETUP) {
903 dw_udc_setup(udc_device->bus->endpoint_array + 0);
904 writel(ENDP_STATUS_OUT_SETUP,
905 &outep_regs_p[0].endp_status);
907 } else if ((readl(&outep_regs_p[0].endp_status) &
908 ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) {
909 dw_udc_ep0_rx(udc_device->bus->endpoint_array + 0);
910 writel(ENDP_STATUS_OUT_DATA,
911 &outep_regs_p[0].endp_status);
913 } else if ((readl(&outep_regs_p[0].endp_status) &
914 ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) {
918 writel(0x0, &outep_regs_p[0].endp_status);
921 if (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLIN) {
922 dw_udc_ep0_tx(udc_device->bus->endpoint_array + 0);
924 writel(ENDP_STATUS_IN, &inep_regs_p[0].endp_status);
925 writel(ENDP0_INT_CTRLIN, &udc_regs_p->endp_int);
928 if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK) {
930 u32 ep_int = readl(&udc_regs_p->endp_int) &
931 ENDP_INT_NONISOOUT_MSK;
934 while (0x0 == (ep_int & 0x1)) {
939 writel((1 << 16) << epnum, &udc_regs_p->endp_int);
941 if ((readl(&outep_regs_p[epnum].endp_status) &
942 ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) {
944 dw_udc_epn_rx(epnum);
945 writel(ENDP_STATUS_OUT_DATA,
946 &outep_regs_p[epnum].endp_status);
947 } else if ((readl(&outep_regs_p[epnum].endp_status) &
948 ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) {
949 writel(0x0, &outep_regs_p[epnum].endp_status);
953 if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOIN_MSK) {
955 u32 ep_int = readl(&udc_regs_p->endp_int) &
956 ENDP_INT_NONISOIN_MSK;
958 while (0x0 == (ep_int & 0x1)) {
963 if (readl(&inep_regs_p[epnum].endp_status) & ENDP_STATUS_IN) {
964 writel(ENDP_STATUS_IN,
965 &outep_regs_p[epnum].endp_status);
966 dw_udc_epn_tx(epnum);
968 writel(ENDP_STATUS_IN,
969 &outep_regs_p[epnum].endp_status);
972 writel((1 << epnum), &udc_regs_p->endp_int);
982 * Loop while we have interrupts.
983 * If we don't do this, the input chain
984 * polling delay is likely to miss
987 while (readl(&plug_regs_p->plug_pending))
990 while (readl(&udc_regs_p->dev_int))
993 if (readl(&udc_regs_p->endp_int))
994 dw_udc_endpoint_irq();
998 void udc_set_nak(int epid)
1000 writel(readl(&inep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK,
1001 &inep_regs_p[epid].endp_cntl);
1003 writel(readl(&outep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK,
1004 &outep_regs_p[epid].endp_cntl);
1007 void udc_unset_nak(int epid)
1011 val = readl(&inep_regs_p[epid].endp_cntl);
1012 val &= ~ENDP_CNTL_SNAK;
1013 val |= ENDP_CNTL_CNAK;
1014 writel(val, &inep_regs_p[epid].endp_cntl);
1016 val = readl(&outep_regs_p[epid].endp_cntl);
1017 val &= ~ENDP_CNTL_SNAK;
1018 val |= ENDP_CNTL_CNAK;
1019 writel(val, &outep_regs_p[epid].endp_cntl);