1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Broadcom Corporation.
9 #include <asm/arch/sysmap.h>
10 #include <asm/kona-common/clk.h>
12 #include "dwc2_udc_otg_priv.h"
13 #include "bcm_udc_otg.h"
15 void otg_phy_init(struct dwc2_udc *dev)
17 /* turn on the USB OTG clocks */
18 clk_usb_otg_enable((void *)HSOTG_BASE_ADDR);
20 /* set Phy to driving mode */
21 wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
22 HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
26 /* clear Soft Disconnect */
27 wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
28 HSOTG_DCTL_SFTDISCON_MASK);
30 /* invoke Reset (active low) */
31 wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
32 HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
34 /* Reset needs to be asserted for 2ms */
38 wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
39 HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK,
40 HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
43 void otg_phy_off(struct dwc2_udc *dev)
46 wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
47 HSOTG_DCTL_SFTDISCON_MASK,
48 HSOTG_DCTL_SFTDISCON_MASK);
50 /* set Phy to non-driving (reset) mode */
51 wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
52 HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK,
53 HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);