2 * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
12 #include <usb/lin_gadget_compat.h>
13 #include <linux/mii.h>
14 #include <linux/bitops.h>
15 #include "usb_ether.h"
19 static int curr_eth_dev; /* index for name of next device detected */
22 unsigned short vendor;
23 unsigned short product;
26 struct r8152_version {
28 unsigned short version;
32 static const struct r8152_dongle const r8152_dongles[] = {
58 static const struct r8152_version const r8152_versions[] = {
59 { 0x4c00, RTL_VER_01, 0 },
60 { 0x4c10, RTL_VER_02, 0 },
61 { 0x5c00, RTL_VER_03, 1 },
62 { 0x5c10, RTL_VER_04, 1 },
63 { 0x5c20, RTL_VER_05, 1 },
64 { 0x5c30, RTL_VER_06, 1 },
65 { 0x4800, RTL_VER_07, 0 },
69 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
71 return usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
72 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
73 value, index, data, size, 500);
77 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
79 return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
80 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
81 value, index, data, size, 500);
84 int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
91 /* both size and index must be 4 bytes align */
92 if ((size & 3) || !size || (index & 3) || !data)
95 if (index + size > 0xffff)
99 txsize = min(size, burst_size);
100 ret = get_registers(tp, index, type, txsize, data);
112 int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
113 u16 size, void *data, u16 type)
116 u16 byteen_start, byteen_end, byte_en_to_hw;
117 u16 burst_size = 512;
120 /* both size and index must be 4 bytes align */
121 if ((size & 3) || !size || (index & 3) || !data)
124 if (index + size > 0xffff)
127 byteen_start = byteen & BYTE_EN_START_MASK;
128 byteen_end = byteen & BYTE_EN_END_MASK;
130 byte_en_to_hw = byteen_start | (byteen_start << 4);
131 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
143 txsize = min(size, burst_size);
145 ret = set_registers(tp, index,
146 type | BYTE_EN_DWORD,
156 byte_en_to_hw = byteen_end | (byteen_end >> 4);
157 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
165 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
167 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
170 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
172 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
175 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
177 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
180 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
182 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
185 u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
189 generic_ocp_read(tp, index, sizeof(data), &data, type);
191 return __le32_to_cpu(data);
194 void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
196 __le32 tmp = __cpu_to_le32(data);
198 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
201 u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
205 u8 shift = index & 2;
209 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
211 data = __le32_to_cpu(tmp);
212 data >>= (shift * 8);
218 void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
222 u16 byen = BYTE_EN_WORD;
223 u8 shift = index & 2;
229 mask <<= (shift * 8);
230 data <<= (shift * 8);
234 tmp = __cpu_to_le32(data);
236 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
239 u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
243 u8 shift = index & 3;
247 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
249 data = __le32_to_cpu(tmp);
250 data >>= (shift * 8);
256 void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
260 u16 byen = BYTE_EN_BYTE;
261 u8 shift = index & 3;
267 mask <<= (shift * 8);
268 data <<= (shift * 8);
272 tmp = __cpu_to_le32(data);
274 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
277 u16 ocp_reg_read(struct r8152 *tp, u16 addr)
279 u16 ocp_base, ocp_index;
281 ocp_base = addr & 0xf000;
282 if (ocp_base != tp->ocp_base) {
283 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
284 tp->ocp_base = ocp_base;
287 ocp_index = (addr & 0x0fff) | 0xb000;
288 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
291 void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
293 u16 ocp_base, ocp_index;
295 ocp_base = addr & 0xf000;
296 if (ocp_base != tp->ocp_base) {
297 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
298 tp->ocp_base = ocp_base;
301 ocp_index = (addr & 0x0fff) | 0xb000;
302 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
305 static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
307 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
310 static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
312 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
315 void sram_write(struct r8152 *tp, u16 addr, u16 data)
317 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
318 ocp_reg_write(tp, OCP_SRAM_DATA, data);
321 int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
322 const u32 mask, bool set, unsigned int timeout)
328 val = ocp_reg_read(tp, index);
330 val = ocp_read_dword(tp, type, index);
335 if ((val & mask) == mask)
341 debug("%s: Timeout (index=%04x mask=%08x timeout=%d)\n",
342 __func__, index, mask, timeout);
347 static void r8152b_reset_packet_filter(struct r8152 *tp)
351 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
352 ocp_data &= ~FMC_FCR_MCU_EN;
353 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
354 ocp_data |= FMC_FCR_MCU_EN;
355 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
358 static void rtl8152_wait_fifo_empty(struct r8152 *tp)
362 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
363 PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT);
365 debug("Timeout waiting for FIFO empty\n");
367 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0,
368 TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT);
370 debug("Timeout waiting for TX empty\n");
373 static void rtl8152_nic_reset(struct r8152 *tp)
378 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL);
379 ocp_data |= BIST_CTRL_SW_RESET;
380 ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data);
382 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL,
383 BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT);
385 debug("Timeout waiting for NIC reset\n");
388 static u8 rtl8152_get_speed(struct r8152 *tp)
390 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
393 static void rtl_set_eee_plus(struct r8152 *tp)
397 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
398 ocp_data &= ~EEEP_CR_EEEP_TX;
399 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
402 static void rxdy_gated_en(struct r8152 *tp, bool enable)
406 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
408 ocp_data |= RXDY_GATED_EN;
410 ocp_data &= ~RXDY_GATED_EN;
411 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
414 static void rtl8152_set_rx_mode(struct r8152 *tp)
422 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
424 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
425 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
426 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
429 static int rtl_enable(struct r8152 *tp)
433 r8152b_reset_packet_filter(tp);
435 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
436 ocp_data |= PLA_CR_RE | PLA_CR_TE;
437 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
439 rxdy_gated_en(tp, false);
441 rtl8152_set_rx_mode(tp);
446 static int rtl8152_enable(struct r8152 *tp)
448 rtl_set_eee_plus(tp);
450 return rtl_enable(tp);
453 static void r8153_set_rx_early_timeout(struct r8152 *tp)
455 u32 ocp_data = tp->coalesce / 8;
457 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
460 static void r8153_set_rx_early_size(struct r8152 *tp)
462 u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS) / 4;
464 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
467 static int rtl8153_enable(struct r8152 *tp)
469 rtl_set_eee_plus(tp);
470 r8153_set_rx_early_timeout(tp);
471 r8153_set_rx_early_size(tp);
473 return rtl_enable(tp);
476 static void rtl_disable(struct r8152 *tp)
480 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
481 ocp_data &= ~RCR_ACPT_ALL;
482 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
484 rxdy_gated_en(tp, true);
486 rtl8152_wait_fifo_empty(tp);
487 rtl8152_nic_reset(tp);
490 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
494 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
496 ocp_data |= POWER_CUT;
498 ocp_data &= ~POWER_CUT;
499 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
501 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
502 ocp_data &= ~RESUME_INDICATE;
503 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
506 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
510 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
512 ocp_data |= CPCR_RX_VLAN;
514 ocp_data &= ~CPCR_RX_VLAN;
515 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
518 static void r8153_u1u2en(struct r8152 *tp, bool enable)
523 memset(u1u2, 0xff, sizeof(u1u2));
525 memset(u1u2, 0x00, sizeof(u1u2));
527 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
530 static void r8153_u2p3en(struct r8152 *tp, bool enable)
534 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
535 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
536 ocp_data |= U2P3_ENABLE;
538 ocp_data &= ~U2P3_ENABLE;
539 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
542 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
546 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
548 ocp_data |= PWR_EN | PHASE2_EN;
550 ocp_data &= ~(PWR_EN | PHASE2_EN);
551 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
553 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
554 ocp_data &= ~PCUT_STATUS;
555 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
558 static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr)
561 unsigned char enetaddr[8] = {0};
563 ret = pla_ocp_read(tp, PLA_IDR, 8, enetaddr);
567 memcpy(macaddr, enetaddr, ETH_ALEN);
571 static void r8152b_disable_aldps(struct r8152 *tp)
573 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
577 static void r8152b_enable_aldps(struct r8152 *tp)
579 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
580 LINKENA | DIS_SDSAVE);
583 static void rtl8152_disable(struct r8152 *tp)
585 r8152b_disable_aldps(tp);
587 r8152b_enable_aldps(tp);
590 static void r8152b_hw_phy_cfg(struct r8152 *tp)
594 data = r8152_mdio_read(tp, MII_BMCR);
595 if (data & BMCR_PDOWN) {
597 r8152_mdio_write(tp, MII_BMCR, data);
603 static void rtl8152_reinit_ll(struct r8152 *tp)
608 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
609 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
611 debug("Timeout waiting for link list ready\n");
613 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
614 ocp_data |= RE_INIT_LL;
615 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
617 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
618 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
620 debug("Timeout waiting for link list ready\n");
623 static void r8152b_exit_oob(struct r8152 *tp)
627 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
628 ocp_data &= ~RCR_ACPT_ALL;
629 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
631 rxdy_gated_en(tp, true);
632 r8152b_hw_phy_cfg(tp);
634 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
635 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
637 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
638 ocp_data &= ~NOW_IS_OOB;
639 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
641 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
642 ocp_data &= ~MCU_BORW_EN;
643 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
645 rtl8152_reinit_ll(tp);
646 rtl8152_nic_reset(tp);
648 /* rx share fifo credit full threshold */
649 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
651 if (tp->udev->speed == USB_SPEED_FULL ||
652 tp->udev->speed == USB_SPEED_LOW) {
653 /* rx share fifo credit near full threshold */
654 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
656 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
659 /* rx share fifo credit near full threshold */
660 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
662 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
666 /* TX share fifo free credit full threshold */
667 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
669 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
670 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
671 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
672 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
674 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
676 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
677 ocp_data |= TCR0_AUTO_FIFO;
678 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
681 static void r8152b_enter_oob(struct r8152 *tp)
685 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
686 ocp_data &= ~NOW_IS_OOB;
687 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
689 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
690 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
691 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
695 rtl8152_reinit_ll(tp);
697 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
699 rtl_rx_vlan_en(tp, false);
701 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
702 ocp_data |= ALDPS_PROXY_MODE;
703 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
705 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
706 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
707 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
709 rxdy_gated_en(tp, false);
711 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
712 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
713 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
716 static void r8153_hw_phy_cfg(struct r8152 *tp)
721 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
722 tp->version == RTL_VER_05)
723 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
725 data = r8152_mdio_read(tp, MII_BMCR);
726 if (data & BMCR_PDOWN) {
728 r8152_mdio_write(tp, MII_BMCR, data);
733 if (tp->version == RTL_VER_03) {
734 data = ocp_reg_read(tp, OCP_EEE_CFG);
735 data &= ~CTAP_SHORT_EN;
736 ocp_reg_write(tp, OCP_EEE_CFG, data);
739 data = ocp_reg_read(tp, OCP_POWER_CFG);
740 data |= EEE_CLKDIV_EN;
741 ocp_reg_write(tp, OCP_POWER_CFG, data);
743 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
744 data |= EN_10M_BGOFF;
745 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
746 data = ocp_reg_read(tp, OCP_POWER_CFG);
747 data |= EN_10M_PLLOFF;
748 ocp_reg_write(tp, OCP_POWER_CFG, data);
749 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
751 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
752 ocp_data |= PFM_PWM_SWITCH;
753 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
755 /* Enable LPF corner auto tune */
756 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
758 /* Adjust 10M Amplitude */
759 sram_write(tp, SRAM_10M_AMP1, 0x00af);
760 sram_write(tp, SRAM_10M_AMP2, 0x0208);
763 static void r8153_first_init(struct r8152 *tp)
767 rxdy_gated_en(tp, true);
769 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
770 ocp_data &= ~RCR_ACPT_ALL;
771 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
773 r8153_hw_phy_cfg(tp);
775 rtl8152_nic_reset(tp);
777 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
778 ocp_data &= ~NOW_IS_OOB;
779 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
781 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
782 ocp_data &= ~MCU_BORW_EN;
783 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
785 rtl8152_reinit_ll(tp);
787 rtl_rx_vlan_en(tp, false);
789 ocp_data = RTL8153_RMS;
790 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
791 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
793 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
794 ocp_data |= TCR0_AUTO_FIFO;
795 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
797 rtl8152_nic_reset(tp);
799 /* rx share fifo credit full threshold */
800 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
801 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
802 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
803 /* TX share fifo free credit full threshold */
804 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
807 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
809 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
810 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
813 static void r8153_enter_oob(struct r8152 *tp)
817 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
818 ocp_data &= ~NOW_IS_OOB;
819 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
823 rtl8152_reinit_ll(tp);
825 ocp_data = RTL8153_RMS;
826 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
828 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
829 ocp_data &= ~TEREDO_WAKE_MASK;
830 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
832 rtl_rx_vlan_en(tp, false);
834 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
835 ocp_data |= ALDPS_PROXY_MODE;
836 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
838 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
839 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
840 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
842 rxdy_gated_en(tp, false);
844 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
845 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
846 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
849 static void r8153_disable_aldps(struct r8152 *tp)
853 data = ocp_reg_read(tp, OCP_POWER_CFG);
855 ocp_reg_write(tp, OCP_POWER_CFG, data);
859 static void rtl8153_disable(struct r8152 *tp)
861 r8153_disable_aldps(tp);
865 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
867 u16 bmcr, anar, gbcr;
869 anar = r8152_mdio_read(tp, MII_ADVERTISE);
870 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
871 ADVERTISE_100HALF | ADVERTISE_100FULL);
872 if (tp->supports_gmii) {
873 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
874 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
879 if (autoneg == AUTONEG_DISABLE) {
880 if (speed == SPEED_10) {
882 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
883 } else if (speed == SPEED_100) {
884 bmcr = BMCR_SPEED100;
885 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
886 } else if (speed == SPEED_1000 && tp->supports_gmii) {
887 bmcr = BMCR_SPEED1000;
888 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
893 if (duplex == DUPLEX_FULL)
894 bmcr |= BMCR_FULLDPLX;
896 if (speed == SPEED_10) {
897 if (duplex == DUPLEX_FULL)
898 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
900 anar |= ADVERTISE_10HALF;
901 } else if (speed == SPEED_100) {
902 if (duplex == DUPLEX_FULL) {
903 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
904 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
906 anar |= ADVERTISE_10HALF;
907 anar |= ADVERTISE_100HALF;
909 } else if (speed == SPEED_1000 && tp->supports_gmii) {
910 if (duplex == DUPLEX_FULL) {
911 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
912 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
913 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
915 anar |= ADVERTISE_10HALF;
916 anar |= ADVERTISE_100HALF;
917 gbcr |= ADVERTISE_1000HALF;
923 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
926 if (tp->supports_gmii)
927 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
929 r8152_mdio_write(tp, MII_ADVERTISE, anar);
930 r8152_mdio_write(tp, MII_BMCR, bmcr);
935 static void rtl8152_up(struct r8152 *tp)
937 r8152b_disable_aldps(tp);
939 r8152b_enable_aldps(tp);
942 static void rtl8152_down(struct r8152 *tp)
944 r8152_power_cut_en(tp, false);
945 r8152b_disable_aldps(tp);
946 r8152b_enter_oob(tp);
947 r8152b_enable_aldps(tp);
950 static void rtl8153_up(struct r8152 *tp)
952 r8153_u1u2en(tp, false);
953 r8153_disable_aldps(tp);
954 r8153_first_init(tp);
955 r8153_u2p3en(tp, false);
958 static void rtl8153_down(struct r8152 *tp)
960 r8153_u1u2en(tp, false);
961 r8153_u2p3en(tp, false);
962 r8153_power_cut_en(tp, false);
963 r8153_disable_aldps(tp);
967 static void r8152b_get_version(struct r8152 *tp)
973 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
974 tcr = (u16)(ocp_data & VERSION_MASK);
976 for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) {
977 if (tcr == r8152_versions[i].tcr) {
978 /* Found a supported version */
979 tp->version = r8152_versions[i].version;
980 tp->supports_gmii = r8152_versions[i].gmii;
985 if (tp->version == RTL_VER_UNKNOWN)
986 debug("r8152 Unknown tcr version 0x%04x\n", tcr);
989 static void r8152b_enable_fc(struct r8152 *tp)
992 anar = r8152_mdio_read(tp, MII_ADVERTISE);
993 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
994 r8152_mdio_write(tp, MII_ADVERTISE, anar);
997 static void rtl_tally_reset(struct r8152 *tp)
1001 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
1002 ocp_data |= TALLY_RESET;
1003 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
1006 static void r8152b_init(struct r8152 *tp)
1010 r8152b_disable_aldps(tp);
1012 if (tp->version == RTL_VER_01) {
1013 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1014 ocp_data &= ~LED_MODE_MASK;
1015 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1018 r8152_power_cut_en(tp, false);
1020 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1021 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
1022 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1023 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
1024 ocp_data &= ~MCU_CLK_RATIO_MASK;
1025 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
1026 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
1027 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
1028 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
1029 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
1031 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER);
1032 ocp_data |= BIT(15);
1033 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1034 ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8);
1035 ocp_data &= ~BIT(15);
1036 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1038 r8152b_enable_fc(tp);
1039 rtl_tally_reset(tp);
1041 /* enable rx aggregation */
1042 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
1044 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
1045 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1048 static void r8153_init(struct r8152 *tp)
1053 r8153_disable_aldps(tp);
1054 r8153_u1u2en(tp, false);
1056 r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
1057 AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
1059 for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
1060 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
1061 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
1067 r8153_u2p3en(tp, false);
1069 if (tp->version == RTL_VER_04) {
1070 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
1071 ocp_data &= ~pwd_dn_scale_mask;
1072 ocp_data |= pwd_dn_scale(96);
1073 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
1075 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
1076 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
1077 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
1078 } else if (tp->version == RTL_VER_05) {
1079 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
1080 ocp_data &= ~ECM_ALDPS;
1081 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
1083 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1084 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1085 ocp_data &= ~DYNAMIC_BURST;
1087 ocp_data |= DYNAMIC_BURST;
1088 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1089 } else if (tp->version == RTL_VER_06) {
1090 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1091 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1092 ocp_data &= ~DYNAMIC_BURST;
1094 ocp_data |= DYNAMIC_BURST;
1095 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1098 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
1099 ocp_data |= EP4_FULL_FC;
1100 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
1102 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
1103 ocp_data &= ~TIMER11_EN;
1104 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
1106 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1107 ocp_data &= ~LED_MODE_MASK;
1108 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1110 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
1111 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
1112 ocp_data |= LPM_TIMER_500MS;
1114 ocp_data |= LPM_TIMER_500US;
1115 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
1117 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
1118 ocp_data &= ~SEN_VAL_MASK;
1119 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
1120 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
1122 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
1124 r8153_power_cut_en(tp, false);
1126 r8152b_enable_fc(tp);
1127 rtl_tally_reset(tp);
1130 static void rtl8152_unload(struct r8152 *tp)
1132 if (tp->version != RTL_VER_01)
1133 r8152_power_cut_en(tp, true);
1136 static void rtl8153_unload(struct r8152 *tp)
1138 r8153_power_cut_en(tp, false);
1141 static int rtl_ops_init(struct r8152 *tp)
1143 struct rtl_ops *ops = &tp->rtl_ops;
1146 switch (tp->version) {
1150 ops->init = r8152b_init;
1151 ops->enable = rtl8152_enable;
1152 ops->disable = rtl8152_disable;
1153 ops->up = rtl8152_up;
1154 ops->down = rtl8152_down;
1155 ops->unload = rtl8152_unload;
1162 ops->init = r8153_init;
1163 ops->enable = rtl8153_enable;
1164 ops->disable = rtl8153_disable;
1165 ops->up = rtl8153_up;
1166 ops->down = rtl8153_down;
1167 ops->unload = rtl8153_unload;
1172 printf("r8152 Unknown Device\n");
1179 static int r8152_init(struct eth_device *eth, bd_t *bd)
1181 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1182 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1188 debug("** %s()\n", __func__);
1191 speed = rtl8152_get_speed(tp);
1193 link_detected = speed & LINK_STATUS;
1194 if (!link_detected) {
1196 printf("Waiting for Ethernet connection... ");
1197 mdelay(TIMEOUT_RESOLUTION);
1198 timeout += TIMEOUT_RESOLUTION;
1200 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
1201 if (link_detected) {
1202 tp->rtl_ops.enable(tp);
1207 printf("unable to connect.\n");
1213 static int r8152_send(struct eth_device *eth, void *packet, int length)
1215 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1217 u32 opts1, opts2 = 0;
1222 unsigned char msg[PKTSIZE + sizeof(struct tx_desc)];
1223 struct tx_desc *tx_desc = (struct tx_desc *)msg;
1225 debug("** %s(), len %d\n", __func__, length);
1227 opts1 = length | TX_FS | TX_LS;
1229 tx_desc->opts2 = cpu_to_le32(opts2);
1230 tx_desc->opts1 = cpu_to_le32(opts1);
1232 memcpy(msg + sizeof(struct tx_desc), (void *)packet, length);
1234 err = usb_bulk_msg(dev->pusb_dev,
1235 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
1237 length + sizeof(struct tx_desc),
1239 USB_BULK_SEND_TIMEOUT);
1240 debug("Tx: len = %zu, actual = %u, err = %d\n",
1241 length + sizeof(struct tx_desc), actual_len, err);
1246 static int r8152_recv(struct eth_device *eth)
1248 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1250 static unsigned char recv_buf[RTL8152_AGG_BUF_SZ];
1251 unsigned char *pkt_ptr;
1256 u32 bytes_process = 0;
1257 struct rx_desc *rx_desc;
1259 debug("** %s()\n", __func__);
1261 err = usb_bulk_msg(dev->pusb_dev,
1262 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
1266 USB_BULK_RECV_TIMEOUT);
1267 debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ,
1270 debug("Rx: failed to receive\n");
1273 if (actual_len > RTL8152_AGG_BUF_SZ) {
1274 debug("Rx: received too many bytes %d\n", actual_len);
1278 while (bytes_process < actual_len) {
1279 rx_desc = (struct rx_desc *)(recv_buf + bytes_process);
1280 pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process;
1282 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1283 packet_len -= CRC_SIZE;
1285 net_process_received_packet(pkt_ptr, packet_len);
1288 (packet_len + sizeof(struct rx_desc) + CRC_SIZE);
1290 if (bytes_process % 8)
1291 bytes_process = bytes_process + 8 - (bytes_process % 8);
1297 static void r8152_halt(struct eth_device *eth)
1299 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1300 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1302 debug("** %s()\n", __func__);
1304 tp->rtl_ops.disable(tp);
1307 static int r8152_write_hwaddr(struct eth_device *eth)
1309 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1310 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1312 unsigned char enetaddr[8] = {0};
1314 memcpy(enetaddr, eth->enetaddr, ETH_ALEN);
1316 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1317 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
1318 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1320 debug("MAC %pM\n", eth->enetaddr);
1324 void r8152_eth_before_probe(void)
1329 /* Probe to see if a new device is actually an realtek device */
1330 int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
1331 struct ueth_data *ss)
1333 struct usb_interface *iface;
1334 struct usb_interface_descriptor *iface_desc;
1335 int ep_in_found = 0, ep_out_found = 0;
1340 /* let's examine the device now */
1341 iface = &dev->config.if_desc[ifnum];
1342 iface_desc = &dev->config.if_desc[ifnum].desc;
1344 for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) {
1345 if (dev->descriptor.idVendor == r8152_dongles[i].vendor &&
1346 dev->descriptor.idProduct == r8152_dongles[i].product)
1347 /* Found a supported dongle */
1351 if (i == ARRAY_SIZE(r8152_dongles))
1354 memset(ss, 0, sizeof(struct ueth_data));
1356 /* At this point, we know we've got a live one */
1357 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
1358 dev->descriptor.idVendor, dev->descriptor.idProduct);
1360 /* Initialize the ueth_data structure with some useful info */
1363 ss->subclass = iface_desc->bInterfaceSubClass;
1364 ss->protocol = iface_desc->bInterfaceProtocol;
1366 /* alloc driver private */
1367 ss->dev_priv = calloc(1, sizeof(struct r8152));
1373 * We are expecting a minimum of 3 endpoints - in, out (bulk), and
1374 * int. We will ignore any others.
1376 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
1377 /* is it an BULK endpoint? */
1378 if ((iface->ep_desc[i].bmAttributes &
1379 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
1380 u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
1381 if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
1382 ss->ep_in = ep_addr &
1383 USB_ENDPOINT_NUMBER_MASK;
1386 if (!ep_out_found) {
1387 ss->ep_out = ep_addr &
1388 USB_ENDPOINT_NUMBER_MASK;
1394 /* is it an interrupt endpoint? */
1395 if ((iface->ep_desc[i].bmAttributes &
1396 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
1397 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
1398 USB_ENDPOINT_NUMBER_MASK;
1399 ss->irqinterval = iface->ep_desc[i].bInterval;
1403 debug("Endpoints In %d Out %d Int %d\n",
1404 ss->ep_in, ss->ep_out, ss->ep_int);
1406 /* Do some basic sanity checks, and bail if we find a problem */
1407 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
1408 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
1409 debug("Problems with device\n");
1413 dev->privptr = (void *)ss;
1419 r8152b_get_version(tp);
1421 if (rtl_ops_init(tp))
1424 tp->rtl_ops.init(tp);
1427 rtl8152_set_speed(tp, AUTONEG_ENABLE,
1428 tp->supports_gmii ? SPEED_1000 : SPEED_100,
1434 int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
1435 struct eth_device *eth)
1438 debug("%s: missing parameter.\n", __func__);
1442 sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++);
1443 eth->init = r8152_init;
1444 eth->send = r8152_send;
1445 eth->recv = r8152_recv;
1446 eth->halt = r8152_halt;
1447 eth->write_hwaddr = r8152_write_hwaddr;
1450 /* Get the MAC address */
1451 if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0)
1454 debug("MAC %pM\n", eth->enetaddr);