drivers/usb/eth/r8152.c

   1 /*
   2  * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  *
   6   */
   7
   8 #include <common.h>
   9 #include <errno.h>
  10 #include <malloc.h>
  11 #include <usb.h>
  12 #include <usb/lin_gadget_compat.h>
  13 #include <linux/mii.h>
  14 #include <linux/bitops.h>
  15 #include "usb_ether.h"
  16 #include "r8152.h"
  17
  18 /* local vars */
  19 static int curr_eth_dev; /* index for name of next device detected */
  20
  21 struct r8152_dongle {
  22         unsigned short vendor;
  23         unsigned short product;
  24 };
  25
  26 struct r8152_version {
  27         unsigned short tcr;
  28         unsigned short version;
  29         bool           gmii;
  30 };
  31
  32 static const struct r8152_dongle const r8152_dongles[] = {
  33         /* Realtek */
  34         { 0x0bda, 0x8050 },
  35         { 0x0bda, 0x8152 },
  36         { 0x0bda, 0x8153 },
  37
  38         /* Samsung */
  39         { 0x04e8, 0xa101 },
  40
  41         /* Lenovo */
  42         { 0x17ef, 0x304f },
  43         { 0x17ef, 0x3052 },
  44         { 0x17ef, 0x3054 },
  45         { 0x17ef, 0x3057 },
  46         { 0x17ef, 0x7205 },
  47         { 0x17ef, 0x720a },
  48         { 0x17ef, 0x720b },
  49         { 0x17ef, 0x720c },
  50
  51         /* TP-LINK */
  52         { 0x2357, 0x0601 },
  53
  54         /* Nvidia */
  55         { 0x0955, 0x09ff },
  56 };
  57
  58 static const struct r8152_version const r8152_versions[] = {
  59         { 0x4c00, RTL_VER_01, 0 },
  60         { 0x4c10, RTL_VER_02, 0 },
  61         { 0x5c00, RTL_VER_03, 1 },
  62         { 0x5c10, RTL_VER_04, 1 },
  63         { 0x5c20, RTL_VER_05, 1 },
  64         { 0x5c30, RTL_VER_06, 1 },
  65         { 0x4800, RTL_VER_07, 0 },
  66 };
  67
  68 static
  69 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  70 {
  71         return usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  72                                RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  73                                value, index, data, size, 500);
  74 }
  75
  76 static
  77 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  78 {
  79         return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  80                                RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  81                                value, index, data, size, 500);
  82 }
  83
  84 int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  85                      void *data, u16 type)
  86 {
  87         u16 burst_size = 64;
  88         int ret;
  89         int txsize;
  90
  91         /* both size and index must be 4 bytes align */
  92         if ((size & 3) || !size || (index & 3) || !data)
  93                 return -EINVAL;
  94
  95         if (index + size > 0xffff)
  96                 return -EINVAL;
  97
  98         while (size) {
  99                 txsize = min(size, burst_size);
 100                 ret = get_registers(tp, index, type, txsize, data);
 101                 if (ret < 0)
 102                         break;
 103
 104                 index += txsize;
 105                 data += txsize;
 106                 size -= txsize;
 107         }
 108
 109         return ret;
 110 }
 111
 112 int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
 113                       u16 size, void *data, u16 type)
 114 {
 115         int ret;
 116         u16 byteen_start, byteen_end, byte_en_to_hw;
 117         u16 burst_size = 512;
 118         int txsize;
 119
 120         /* both size and index must be 4 bytes align */
 121         if ((size & 3) || !size || (index & 3) || !data)
 122                 return -EINVAL;
 123
 124         if (index + size > 0xffff)
 125                 return -EINVAL;
 126
 127         byteen_start = byteen & BYTE_EN_START_MASK;
 128         byteen_end = byteen & BYTE_EN_END_MASK;
 129
 130         byte_en_to_hw = byteen_start | (byteen_start << 4);
 131         ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
 132         if (ret < 0)
 133                 return ret;
 134
 135         index += 4;
 136         data += 4;
 137         size -= 4;
 138
 139         if (size) {
 140                 size -= 4;
 141
 142                 while (size) {
 143                         txsize = min(size, burst_size);
 144
 145                         ret = set_registers(tp, index,
 146                                             type | BYTE_EN_DWORD,
 147                                             txsize, data);
 148                         if (ret < 0)
 149                                 return ret;
 150
 151                         index += txsize;
 152                         data += txsize;
 153                         size -= txsize;
 154                 }
 155
 156                 byte_en_to_hw = byteen_end | (byteen_end >> 4);
 157                 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
 158                 if (ret < 0)
 159                         return ret;
 160         }
 161
 162         return ret;
 163 }
 164
 165 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
 166 {
 167         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
 168 }
 169
 170 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
 171 {
 172         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
 173 }
 174
 175 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
 176 {
 177         return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
 178 }
 179
 180 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
 181 {
 182         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
 183 }
 184
 185 u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
 186 {
 187         __le32 data;
 188
 189         generic_ocp_read(tp, index, sizeof(data), &data, type);
 190
 191         return __le32_to_cpu(data);
 192 }
 193
 194 void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
 195 {
 196         __le32 tmp = __cpu_to_le32(data);
 197
 198         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
 199 }
 200
 201 u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
 202 {
 203         u32 data;
 204         __le32 tmp;
 205         u8 shift = index & 2;
 206
 207         index &= ~3;
 208
 209         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
 210
 211         data = __le32_to_cpu(tmp);
 212         data >>= (shift * 8);
 213         data &= 0xffff;
 214
 215         return data;
 216 }
 217
 218 void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
 219 {
 220         u32 mask = 0xffff;
 221         __le32 tmp;
 222         u16 byen = BYTE_EN_WORD;
 223         u8 shift = index & 2;
 224
 225         data &= mask;
 226
 227         if (index & 2) {
 228                 byen <<= shift;
 229                 mask <<= (shift * 8);
 230                 data <<= (shift * 8);
 231                 index &= ~3;
 232         }
 233
 234         tmp = __cpu_to_le32(data);
 235
 236         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
 237 }
 238
 239 u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
 240 {
 241         u32 data;
 242         __le32 tmp;
 243         u8 shift = index & 3;
 244
 245         index &= ~3;
 246
 247         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
 248
 249         data = __le32_to_cpu(tmp);
 250         data >>= (shift * 8);
 251         data &= 0xff;
 252
 253         return data;
 254 }
 255
 256 void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
 257 {
 258         u32 mask = 0xff;
 259         __le32 tmp;
 260         u16 byen = BYTE_EN_BYTE;
 261         u8 shift = index & 3;
 262
 263         data &= mask;
 264
 265         if (index & 3) {
 266                 byen <<= shift;
 267                 mask <<= (shift * 8);
 268                 data <<= (shift * 8);
 269                 index &= ~3;
 270         }
 271
 272         tmp = __cpu_to_le32(data);
 273
 274         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
 275 }
 276
 277 u16 ocp_reg_read(struct r8152 *tp, u16 addr)
 278 {
 279         u16 ocp_base, ocp_index;
 280
 281         ocp_base = addr & 0xf000;
 282         if (ocp_base != tp->ocp_base) {
 283                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
 284                 tp->ocp_base = ocp_base;
 285         }
 286
 287         ocp_index = (addr & 0x0fff) | 0xb000;
 288         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
 289 }
 290
 291 void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
 292 {
 293         u16 ocp_base, ocp_index;
 294
 295         ocp_base = addr & 0xf000;
 296         if (ocp_base != tp->ocp_base) {
 297                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
 298                 tp->ocp_base = ocp_base;
 299         }
 300
 301         ocp_index = (addr & 0x0fff) | 0xb000;
 302         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
 303 }
 304
 305 static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
 306 {
 307         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
 308 }
 309
 310 static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
 311 {
 312         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
 313 }
 314
 315 void sram_write(struct r8152 *tp, u16 addr, u16 data)
 316 {
 317         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
 318         ocp_reg_write(tp, OCP_SRAM_DATA, data);
 319 }
 320
 321 int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
 322                        const u32 mask, bool set, unsigned int timeout)
 323 {
 324         u32 val;
 325
 326         while (--timeout) {
 327                 if (ocp_reg)
 328                         val = ocp_reg_read(tp, index);
 329                 else
 330                         val = ocp_read_dword(tp, type, index);
 331
 332                 if (!set)
 333                         val = ~val;
 334
 335                 if ((val & mask) == mask)
 336                         return 0;
 337
 338                 mdelay(1);
 339         }
 340
 341         debug("%s: Timeout (index=%04x mask=%08x timeout=%d)\n",
 342               __func__, index, mask, timeout);
 343
 344         return -ETIMEDOUT;
 345 }
 346
 347 static void r8152b_reset_packet_filter(struct r8152 *tp)
 348 {
 349         u32 ocp_data;
 350
 351         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
 352         ocp_data &= ~FMC_FCR_MCU_EN;
 353         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
 354         ocp_data |= FMC_FCR_MCU_EN;
 355         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
 356 }
 357
 358 static void rtl8152_wait_fifo_empty(struct r8152 *tp)
 359 {
 360         int ret;
 361
 362         ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
 363                                  PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT);
 364         if (ret)
 365                 debug("Timeout waiting for FIFO empty\n");
 366
 367         ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0,
 368                                  TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT);
 369         if (ret)
 370                 debug("Timeout waiting for TX empty\n");
 371 }
 372
 373 static void rtl8152_nic_reset(struct r8152 *tp)
 374 {
 375         int ret;
 376         u32 ocp_data;
 377
 378         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL);
 379         ocp_data |= BIST_CTRL_SW_RESET;
 380         ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data);
 381
 382         ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL,
 383                                  BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT);
 384         if (ret)
 385                 debug("Timeout waiting for NIC reset\n");
 386 }
 387
 388 static u8 rtl8152_get_speed(struct r8152 *tp)
 389 {
 390         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
 391 }
 392
 393 static void rtl_set_eee_plus(struct r8152 *tp)
 394 {
 395         u32 ocp_data;
 396
 397         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
 398         ocp_data &= ~EEEP_CR_EEEP_TX;
 399         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
 400 }
 401
 402 static void rxdy_gated_en(struct r8152 *tp, bool enable)
 403 {
 404         u32 ocp_data;
 405
 406         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
 407         if (enable)
 408                 ocp_data |= RXDY_GATED_EN;
 409         else
 410                 ocp_data &= ~RXDY_GATED_EN;
 411         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
 412 }
 413
 414 static void rtl8152_set_rx_mode(struct r8152 *tp)
 415 {
 416         u32 ocp_data;
 417         __le32 tmp[2];
 418
 419         tmp[0] = 0xffffffff;
 420         tmp[1] = 0xffffffff;
 421
 422         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
 423
 424         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
 425         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
 426         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 427 }
 428
 429 static int rtl_enable(struct r8152 *tp)
 430 {
 431         u32 ocp_data;
 432
 433         r8152b_reset_packet_filter(tp);
 434
 435         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
 436         ocp_data |= PLA_CR_RE | PLA_CR_TE;
 437         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
 438
 439         rxdy_gated_en(tp, false);
 440
 441         rtl8152_set_rx_mode(tp);
 442
 443         return 0;
 444 }
 445
 446 static int rtl8152_enable(struct r8152 *tp)
 447 {
 448         rtl_set_eee_plus(tp);
 449
 450         return rtl_enable(tp);
 451 }
 452
 453 static void r8153_set_rx_early_timeout(struct r8152 *tp)
 454 {
 455         u32 ocp_data = tp->coalesce / 8;
 456
 457         ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
 458 }
 459
 460 static void r8153_set_rx_early_size(struct r8152 *tp)
 461 {
 462         u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS) / 4;
 463
 464         ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
 465 }
 466
 467 static int rtl8153_enable(struct r8152 *tp)
 468 {
 469         rtl_set_eee_plus(tp);
 470         r8153_set_rx_early_timeout(tp);
 471         r8153_set_rx_early_size(tp);
 472
 473         return rtl_enable(tp);
 474 }
 475
 476 static void rtl_disable(struct r8152 *tp)
 477 {
 478         u32 ocp_data;
 479
 480         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
 481         ocp_data &= ~RCR_ACPT_ALL;
 482         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 483
 484         rxdy_gated_en(tp, true);
 485
 486         rtl8152_wait_fifo_empty(tp);
 487         rtl8152_nic_reset(tp);
 488 }
 489
 490 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
 491 {
 492         u32 ocp_data;
 493
 494         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
 495         if (enable)
 496                 ocp_data |= POWER_CUT;
 497         else
 498                 ocp_data &= ~POWER_CUT;
 499         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
 500
 501         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
 502         ocp_data &= ~RESUME_INDICATE;
 503         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
 504 }
 505
 506 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
 507 {
 508         u32 ocp_data;
 509
 510         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
 511         if (enable)
 512                 ocp_data |= CPCR_RX_VLAN;
 513         else
 514                 ocp_data &= ~CPCR_RX_VLAN;
 515         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
 516 }
 517
 518 static void r8153_u1u2en(struct r8152 *tp, bool enable)
 519 {
 520         u8 u1u2[8];
 521
 522         if (enable)
 523                 memset(u1u2, 0xff, sizeof(u1u2));
 524         else
 525                 memset(u1u2, 0x00, sizeof(u1u2));
 526
 527         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
 528 }
 529
 530 static void r8153_u2p3en(struct r8152 *tp, bool enable)
 531 {
 532         u32 ocp_data;
 533
 534         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
 535         if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
 536                 ocp_data |= U2P3_ENABLE;
 537         else
 538                 ocp_data &= ~U2P3_ENABLE;
 539         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
 540 }
 541
 542 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
 543 {
 544         u32 ocp_data;
 545
 546         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
 547         if (enable)
 548                 ocp_data |= PWR_EN | PHASE2_EN;
 549         else
 550                 ocp_data &= ~(PWR_EN | PHASE2_EN);
 551         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
 552
 553         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
 554         ocp_data &= ~PCUT_STATUS;
 555         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
 556 }
 557
 558 static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr)
 559 {
 560         int ret;
 561         unsigned char enetaddr[8] = {0};
 562
 563         ret = pla_ocp_read(tp, PLA_IDR, 8, enetaddr);
 564         if (ret < 0)
 565                 return ret;
 566
 567         memcpy(macaddr, enetaddr, ETH_ALEN);
 568         return 0;
 569 }
 570
 571 static void r8152b_disable_aldps(struct r8152 *tp)
 572 {
 573         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
 574         mdelay(20);
 575 }
 576
 577 static void r8152b_enable_aldps(struct r8152 *tp)
 578 {
 579         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
 580                 LINKENA | DIS_SDSAVE);
 581 }
 582
 583 static void rtl8152_disable(struct r8152 *tp)
 584 {
 585         r8152b_disable_aldps(tp);
 586         rtl_disable(tp);
 587         r8152b_enable_aldps(tp);
 588 }
 589
 590 static void r8152b_hw_phy_cfg(struct r8152 *tp)
 591 {
 592         u16 data;
 593
 594         data = r8152_mdio_read(tp, MII_BMCR);
 595         if (data & BMCR_PDOWN) {
 596                 data &= ~BMCR_PDOWN;
 597                 r8152_mdio_write(tp, MII_BMCR, data);
 598         }
 599
 600         r8152b_firmware(tp);
 601 }
 602
 603 static void rtl8152_reinit_ll(struct r8152 *tp)
 604 {
 605         u32 ocp_data;
 606         int ret;
 607
 608         ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
 609                                  PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
 610         if (ret)
 611                 debug("Timeout waiting for link list ready\n");
 612
 613         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
 614         ocp_data |= RE_INIT_LL;
 615         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
 616
 617         ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
 618                                  PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
 619         if (ret)
 620                 debug("Timeout waiting for link list ready\n");
 621 }
 622
 623 static void r8152b_exit_oob(struct r8152 *tp)
 624 {
 625         u32 ocp_data;
 626
 627         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
 628         ocp_data &= ~RCR_ACPT_ALL;
 629         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 630
 631         rxdy_gated_en(tp, true);
 632         r8152b_hw_phy_cfg(tp);
 633
 634         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
 635         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
 636
 637         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 638         ocp_data &= ~NOW_IS_OOB;
 639         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
 640
 641         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
 642         ocp_data &= ~MCU_BORW_EN;
 643         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
 644
 645         rtl8152_reinit_ll(tp);
 646         rtl8152_nic_reset(tp);
 647
 648         /* rx share fifo credit full threshold */
 649         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
 650
 651         if (tp->udev->speed == USB_SPEED_FULL ||
 652             tp->udev->speed == USB_SPEED_LOW) {
 653                 /* rx share fifo credit near full threshold */
 654                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
 655                                 RXFIFO_THR2_FULL);
 656                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
 657                                 RXFIFO_THR3_FULL);
 658         } else {
 659                 /* rx share fifo credit near full threshold */
 660                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
 661                                 RXFIFO_THR2_HIGH);
 662                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
 663                                 RXFIFO_THR3_HIGH);
 664         }
 665
 666         /* TX share fifo free credit full threshold */
 667         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
 668
 669         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
 670         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
 671         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
 672                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
 673
 674         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
 675
 676         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
 677         ocp_data |= TCR0_AUTO_FIFO;
 678         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
 679 }
 680
 681 static void r8152b_enter_oob(struct r8152 *tp)
 682 {
 683         u32 ocp_data;
 684
 685         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 686         ocp_data &= ~NOW_IS_OOB;
 687         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
 688
 689         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
 690         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
 691         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
 692
 693         rtl_disable(tp);
 694
 695         rtl8152_reinit_ll(tp);
 696
 697         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
 698
 699         rtl_rx_vlan_en(tp, false);
 700
 701         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
 702         ocp_data |= ALDPS_PROXY_MODE;
 703         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
 704
 705         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 706         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
 707         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
 708
 709         rxdy_gated_en(tp, false);
 710
 711         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
 712         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
 713         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 714 }
 715
 716 static void r8153_hw_phy_cfg(struct r8152 *tp)
 717 {
 718         u32 ocp_data;
 719         u16 data;
 720
 721         if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
 722             tp->version == RTL_VER_05)
 723                 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
 724
 725         data = r8152_mdio_read(tp, MII_BMCR);
 726         if (data & BMCR_PDOWN) {
 727                 data &= ~BMCR_PDOWN;
 728                 r8152_mdio_write(tp, MII_BMCR, data);
 729         }
 730
 731         r8153_firmware(tp);
 732
 733         if (tp->version == RTL_VER_03) {
 734                 data = ocp_reg_read(tp, OCP_EEE_CFG);
 735                 data &= ~CTAP_SHORT_EN;
 736                 ocp_reg_write(tp, OCP_EEE_CFG, data);
 737         }
 738
 739         data = ocp_reg_read(tp, OCP_POWER_CFG);
 740         data |= EEE_CLKDIV_EN;
 741         ocp_reg_write(tp, OCP_POWER_CFG, data);
 742
 743         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
 744         data |= EN_10M_BGOFF;
 745         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
 746         data = ocp_reg_read(tp, OCP_POWER_CFG);
 747         data |= EN_10M_PLLOFF;
 748         ocp_reg_write(tp, OCP_POWER_CFG, data);
 749         sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
 750
 751         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
 752         ocp_data |= PFM_PWM_SWITCH;
 753         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
 754
 755         /* Enable LPF corner auto tune */
 756         sram_write(tp, SRAM_LPF_CFG, 0xf70f);
 757
 758         /* Adjust 10M Amplitude */
 759         sram_write(tp, SRAM_10M_AMP1, 0x00af);
 760         sram_write(tp, SRAM_10M_AMP2, 0x0208);
 761 }
 762
 763 static void r8153_first_init(struct r8152 *tp)
 764 {
 765         u32 ocp_data;
 766
 767         rxdy_gated_en(tp, true);
 768
 769         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
 770         ocp_data &= ~RCR_ACPT_ALL;
 771         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 772
 773         r8153_hw_phy_cfg(tp);
 774
 775         rtl8152_nic_reset(tp);
 776
 777         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 778         ocp_data &= ~NOW_IS_OOB;
 779         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
 780
 781         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
 782         ocp_data &= ~MCU_BORW_EN;
 783         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
 784
 785         rtl8152_reinit_ll(tp);
 786
 787         rtl_rx_vlan_en(tp, false);
 788
 789         ocp_data = RTL8153_RMS;
 790         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
 791         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
 792
 793         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
 794         ocp_data |= TCR0_AUTO_FIFO;
 795         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
 796
 797         rtl8152_nic_reset(tp);
 798
 799         /* rx share fifo credit full threshold */
 800         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
 801         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
 802         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
 803         /* TX share fifo free credit full threshold */
 804         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
 805
 806         /* rx aggregation */
 807         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
 808
 809         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
 810         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
 811 }
 812
 813 static void r8153_enter_oob(struct r8152 *tp)
 814 {
 815         u32 ocp_data;
 816
 817         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 818         ocp_data &= ~NOW_IS_OOB;
 819         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
 820
 821         rtl_disable(tp);
 822
 823         rtl8152_reinit_ll(tp);
 824
 825         ocp_data = RTL8153_RMS;
 826         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
 827
 828         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
 829         ocp_data &= ~TEREDO_WAKE_MASK;
 830         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
 831
 832         rtl_rx_vlan_en(tp, false);
 833
 834         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
 835         ocp_data |= ALDPS_PROXY_MODE;
 836         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
 837
 838         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 839         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
 840         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
 841
 842         rxdy_gated_en(tp, false);
 843
 844         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
 845         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
 846         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 847 }
 848
 849 static void r8153_disable_aldps(struct r8152 *tp)
 850 {
 851         u16 data;
 852
 853         data = ocp_reg_read(tp, OCP_POWER_CFG);
 854         data &= ~EN_ALDPS;
 855         ocp_reg_write(tp, OCP_POWER_CFG, data);
 856         mdelay(20);
 857 }
 858
 859 static void rtl8153_disable(struct r8152 *tp)
 860 {
 861         r8153_disable_aldps(tp);
 862         rtl_disable(tp);
 863 }
 864
 865 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
 866 {
 867         u16 bmcr, anar, gbcr;
 868
 869         anar = r8152_mdio_read(tp, MII_ADVERTISE);
 870         anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
 871                   ADVERTISE_100HALF | ADVERTISE_100FULL);
 872         if (tp->supports_gmii) {
 873                 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
 874                 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 875         } else {
 876                 gbcr = 0;
 877         }
 878
 879         if (autoneg == AUTONEG_DISABLE) {
 880                 if (speed == SPEED_10) {
 881                         bmcr = 0;
 882                         anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 883                 } else if (speed == SPEED_100) {
 884                         bmcr = BMCR_SPEED100;
 885                         anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 886                 } else if (speed == SPEED_1000 && tp->supports_gmii) {
 887                         bmcr = BMCR_SPEED1000;
 888                         gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 889                 } else {
 890                         return -EINVAL;
 891                 }
 892
 893                 if (duplex == DUPLEX_FULL)
 894                         bmcr |= BMCR_FULLDPLX;
 895         } else {
 896                 if (speed == SPEED_10) {
 897                         if (duplex == DUPLEX_FULL)
 898                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 899                         else
 900                                 anar |= ADVERTISE_10HALF;
 901                 } else if (speed == SPEED_100) {
 902                         if (duplex == DUPLEX_FULL) {
 903                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 904                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 905                         } else {
 906                                 anar |= ADVERTISE_10HALF;
 907                                 anar |= ADVERTISE_100HALF;
 908                         }
 909                 } else if (speed == SPEED_1000 && tp->supports_gmii) {
 910                         if (duplex == DUPLEX_FULL) {
 911                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 912                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 913                                 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 914                         } else {
 915                                 anar |= ADVERTISE_10HALF;
 916                                 anar |= ADVERTISE_100HALF;
 917                                 gbcr |= ADVERTISE_1000HALF;
 918                         }
 919                 } else {
 920                         return -EINVAL;
 921                 }
 922
 923                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
 924         }
 925
 926         if (tp->supports_gmii)
 927                 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
 928
 929         r8152_mdio_write(tp, MII_ADVERTISE, anar);
 930         r8152_mdio_write(tp, MII_BMCR, bmcr);
 931
 932         return 0;
 933 }
 934
 935 static void rtl8152_up(struct r8152 *tp)
 936 {
 937         r8152b_disable_aldps(tp);
 938         r8152b_exit_oob(tp);
 939         r8152b_enable_aldps(tp);
 940 }
 941
 942 static void rtl8152_down(struct r8152 *tp)
 943 {
 944         r8152_power_cut_en(tp, false);
 945         r8152b_disable_aldps(tp);
 946         r8152b_enter_oob(tp);
 947         r8152b_enable_aldps(tp);
 948 }
 949
 950 static void rtl8153_up(struct r8152 *tp)
 951 {
 952         r8153_u1u2en(tp, false);
 953         r8153_disable_aldps(tp);
 954         r8153_first_init(tp);
 955         r8153_u2p3en(tp, false);
 956 }
 957
 958 static void rtl8153_down(struct r8152 *tp)
 959 {
 960         r8153_u1u2en(tp, false);
 961         r8153_u2p3en(tp, false);
 962         r8153_power_cut_en(tp, false);
 963         r8153_disable_aldps(tp);
 964         r8153_enter_oob(tp);
 965 }
 966
 967 static void r8152b_get_version(struct r8152 *tp)
 968 {
 969         u32 ocp_data;
 970         u16 tcr;
 971         int i;
 972
 973         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
 974         tcr = (u16)(ocp_data & VERSION_MASK);
 975
 976         for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) {
 977                 if (tcr == r8152_versions[i].tcr) {
 978                         /* Found a supported version */
 979                         tp->version = r8152_versions[i].version;
 980                         tp->supports_gmii = r8152_versions[i].gmii;
 981                         break;
 982                 }
 983         }
 984
 985         if (tp->version == RTL_VER_UNKNOWN)
 986                 debug("r8152 Unknown tcr version 0x%04x\n", tcr);
 987 }
 988
 989 static void r8152b_enable_fc(struct r8152 *tp)
 990 {
 991         u16 anar;
 992         anar = r8152_mdio_read(tp, MII_ADVERTISE);
 993         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 994         r8152_mdio_write(tp, MII_ADVERTISE, anar);
 995 }
 996
 997 static void rtl_tally_reset(struct r8152 *tp)
 998 {
 999         u32 ocp_data;
1000
1001         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
1002         ocp_data |= TALLY_RESET;
1003         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
1004 }
1005
1006 static void r8152b_init(struct r8152 *tp)
1007 {
1008         u32 ocp_data;
1009
1010         r8152b_disable_aldps(tp);
1011
1012         if (tp->version == RTL_VER_01) {
1013                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1014                 ocp_data &= ~LED_MODE_MASK;
1015                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1016         }
1017
1018         r8152_power_cut_en(tp, false);
1019
1020         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1021         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
1022         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1023         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
1024         ocp_data &= ~MCU_CLK_RATIO_MASK;
1025         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
1026         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
1027         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
1028                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
1029         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
1030
1031         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER);
1032         ocp_data |= BIT(15);
1033         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1034         ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8);
1035         ocp_data &= ~BIT(15);
1036         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1037
1038         r8152b_enable_fc(tp);
1039         rtl_tally_reset(tp);
1040
1041         /* enable rx aggregation */
1042         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
1043
1044         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
1045         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1046 }
1047
1048 static void r8153_init(struct r8152 *tp)
1049 {
1050         int i;
1051         u32 ocp_data;
1052
1053         r8153_disable_aldps(tp);
1054         r8153_u1u2en(tp, false);
1055
1056         r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
1057                            AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
1058
1059         for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
1060                 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
1061                 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
1062                         break;
1063
1064                 mdelay(1);
1065         }
1066
1067         r8153_u2p3en(tp, false);
1068
1069         if (tp->version == RTL_VER_04) {
1070                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
1071                 ocp_data &= ~pwd_dn_scale_mask;
1072                 ocp_data |= pwd_dn_scale(96);
1073                 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
1074
1075                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
1076                 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
1077                 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
1078         } else if (tp->version == RTL_VER_05) {
1079                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
1080                 ocp_data &= ~ECM_ALDPS;
1081                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
1082
1083                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1084                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1085                         ocp_data &= ~DYNAMIC_BURST;
1086                 else
1087                         ocp_data |= DYNAMIC_BURST;
1088                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1089         } else if (tp->version == RTL_VER_06) {
1090                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1091                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1092                         ocp_data &= ~DYNAMIC_BURST;
1093                 else
1094                         ocp_data |= DYNAMIC_BURST;
1095                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1096         }
1097
1098         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
1099         ocp_data |= EP4_FULL_FC;
1100         ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
1101
1102         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
1103         ocp_data &= ~TIMER11_EN;
1104         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
1105
1106         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1107         ocp_data &= ~LED_MODE_MASK;
1108         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1109
1110         ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
1111         if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
1112                 ocp_data |= LPM_TIMER_500MS;
1113         else
1114                 ocp_data |= LPM_TIMER_500US;
1115         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
1116
1117         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
1118         ocp_data &= ~SEN_VAL_MASK;
1119         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
1120         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
1121
1122         ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
1123
1124         r8153_power_cut_en(tp, false);
1125
1126         r8152b_enable_fc(tp);
1127         rtl_tally_reset(tp);
1128 }
1129
1130 static void rtl8152_unload(struct r8152 *tp)
1131 {
1132         if (tp->version != RTL_VER_01)
1133                 r8152_power_cut_en(tp, true);
1134 }
1135
1136 static void rtl8153_unload(struct r8152 *tp)
1137 {
1138         r8153_power_cut_en(tp, false);
1139 }
1140
1141 static int rtl_ops_init(struct r8152 *tp)
1142 {
1143         struct rtl_ops *ops = &tp->rtl_ops;
1144         int ret = 0;
1145
1146         switch (tp->version) {
1147         case RTL_VER_01:
1148         case RTL_VER_02:
1149         case RTL_VER_07:
1150                 ops->init               = r8152b_init;
1151                 ops->enable             = rtl8152_enable;
1152                 ops->disable            = rtl8152_disable;
1153                 ops->up                 = rtl8152_up;
1154                 ops->down               = rtl8152_down;
1155                 ops->unload             = rtl8152_unload;
1156                 break;
1157
1158         case RTL_VER_03:
1159         case RTL_VER_04:
1160         case RTL_VER_05:
1161         case RTL_VER_06:
1162                 ops->init               = r8153_init;
1163                 ops->enable             = rtl8153_enable;
1164                 ops->disable            = rtl8153_disable;
1165                 ops->up                 = rtl8153_up;
1166                 ops->down               = rtl8153_down;
1167                 ops->unload             = rtl8153_unload;
1168                 break;
1169
1170         default:
1171                 ret = -ENODEV;
1172                 printf("r8152 Unknown Device\n");
1173                 break;
1174         }
1175
1176         return ret;
1177 }
1178
1179 static int r8152_init(struct eth_device *eth, bd_t *bd)
1180 {
1181         struct ueth_data *dev = (struct ueth_data *)eth->priv;
1182         struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1183
1184         u8 speed;
1185         int timeout = 0;
1186         int link_detected;
1187
1188         debug("** %s()\n", __func__);
1189
1190         do {
1191                 speed = rtl8152_get_speed(tp);
1192
1193                 link_detected = speed & LINK_STATUS;
1194                 if (!link_detected) {
1195                         if (timeout == 0)
1196                                 printf("Waiting for Ethernet connection... ");
1197                         mdelay(TIMEOUT_RESOLUTION);
1198                         timeout += TIMEOUT_RESOLUTION;
1199                 }
1200         } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
1201         if (link_detected) {
1202                 tp->rtl_ops.enable(tp);
1203
1204                 if (timeout != 0)
1205                         printf("done.\n");
1206         } else {
1207                 printf("unable to connect.\n");
1208         }
1209
1210         return 0;
1211 }
1212
1213 static int r8152_send(struct eth_device *eth, void *packet, int length)
1214 {
1215         struct ueth_data *dev = (struct ueth_data *)eth->priv;
1216
1217         u32 opts1, opts2 = 0;
1218
1219         int err;
1220
1221         int actual_len;
1222         unsigned char msg[PKTSIZE + sizeof(struct tx_desc)];
1223         struct tx_desc *tx_desc = (struct tx_desc *)msg;
1224
1225         debug("** %s(), len %d\n", __func__, length);
1226
1227         opts1 = length | TX_FS | TX_LS;
1228
1229         tx_desc->opts2 = cpu_to_le32(opts2);
1230         tx_desc->opts1 = cpu_to_le32(opts1);
1231
1232         memcpy(msg + sizeof(struct tx_desc), (void *)packet, length);
1233
1234         err = usb_bulk_msg(dev->pusb_dev,
1235                                 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
1236                                 (void *)msg,
1237                                 length + sizeof(struct tx_desc),
1238                                 &actual_len,
1239                                 USB_BULK_SEND_TIMEOUT);
1240         debug("Tx: len = %zu, actual = %u, err = %d\n",
1241               length + sizeof(struct tx_desc), actual_len, err);
1242
1243         return err;
1244 }
1245
1246 static int r8152_recv(struct eth_device *eth)
1247 {
1248         struct ueth_data *dev = (struct ueth_data *)eth->priv;
1249
1250         static unsigned char  recv_buf[RTL8152_AGG_BUF_SZ];
1251         unsigned char *pkt_ptr;
1252         int err;
1253         int actual_len;
1254         u16 packet_len;
1255
1256         u32 bytes_process = 0;
1257         struct rx_desc *rx_desc;
1258
1259         debug("** %s()\n", __func__);
1260
1261         err = usb_bulk_msg(dev->pusb_dev,
1262                                 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
1263                                 (void *)recv_buf,
1264                                 RTL8152_AGG_BUF_SZ,
1265                                 &actual_len,
1266                                 USB_BULK_RECV_TIMEOUT);
1267         debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ,
1268               actual_len, err);
1269         if (err != 0) {
1270                 debug("Rx: failed to receive\n");
1271                 return -1;
1272         }
1273         if (actual_len > RTL8152_AGG_BUF_SZ) {
1274                 debug("Rx: received too many bytes %d\n", actual_len);
1275                 return -1;
1276         }
1277
1278         while (bytes_process < actual_len) {
1279                 rx_desc = (struct rx_desc *)(recv_buf + bytes_process);
1280                 pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process;
1281
1282                 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1283                 packet_len -= CRC_SIZE;
1284
1285                 net_process_received_packet(pkt_ptr, packet_len);
1286
1287                 bytes_process +=
1288                         (packet_len + sizeof(struct rx_desc) + CRC_SIZE);
1289
1290                 if (bytes_process % 8)
1291                         bytes_process = bytes_process + 8 - (bytes_process % 8);
1292         }
1293
1294         return 0;
1295 }
1296
1297 static void r8152_halt(struct eth_device *eth)
1298 {
1299         struct ueth_data *dev = (struct ueth_data *)eth->priv;
1300         struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1301
1302         debug("** %s()\n", __func__);
1303
1304         tp->rtl_ops.disable(tp);
1305 }
1306
1307 static int r8152_write_hwaddr(struct eth_device *eth)
1308 {
1309         struct ueth_data *dev = (struct ueth_data *)eth->priv;
1310         struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1311
1312         unsigned char enetaddr[8] = {0};
1313
1314         memcpy(enetaddr, eth->enetaddr, ETH_ALEN);
1315
1316         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1317         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
1318         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1319
1320         debug("MAC %pM\n", eth->enetaddr);
1321         return 0;
1322 }
1323
1324 void r8152_eth_before_probe(void)
1325 {
1326         curr_eth_dev = 0;
1327 }
1328
1329 /* Probe to see if a new device is actually an realtek device */
1330 int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
1331                       struct ueth_data *ss)
1332 {
1333         struct usb_interface *iface;
1334         struct usb_interface_descriptor *iface_desc;
1335         int ep_in_found = 0, ep_out_found = 0;
1336         int i;
1337
1338         struct r8152 *tp;
1339
1340         /* let's examine the device now */
1341         iface = &dev->config.if_desc[ifnum];
1342         iface_desc = &dev->config.if_desc[ifnum].desc;
1343
1344         for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) {
1345                 if (dev->descriptor.idVendor == r8152_dongles[i].vendor &&
1346                     dev->descriptor.idProduct == r8152_dongles[i].product)
1347                         /* Found a supported dongle */
1348                         break;
1349         }
1350
1351         if (i == ARRAY_SIZE(r8152_dongles))
1352                 return 0;
1353
1354         memset(ss, 0, sizeof(struct ueth_data));
1355
1356         /* At this point, we know we've got a live one */
1357         debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
1358               dev->descriptor.idVendor, dev->descriptor.idProduct);
1359
1360         /* Initialize the ueth_data structure with some useful info */
1361         ss->ifnum = ifnum;
1362         ss->pusb_dev = dev;
1363         ss->subclass = iface_desc->bInterfaceSubClass;
1364         ss->protocol = iface_desc->bInterfaceProtocol;
1365
1366         /* alloc driver private */
1367         ss->dev_priv = calloc(1, sizeof(struct r8152));
1368
1369         if (!ss->dev_priv)
1370                 return 0;
1371
1372         /*
1373          * We are expecting a minimum of 3 endpoints - in, out (bulk), and
1374          * int. We will ignore any others.
1375          */
1376         for (i = 0; i < iface_desc->bNumEndpoints; i++) {
1377                 /* is it an BULK endpoint? */
1378                 if ((iface->ep_desc[i].bmAttributes &
1379                      USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
1380                         u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
1381                         if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
1382                                 ss->ep_in = ep_addr &
1383                                         USB_ENDPOINT_NUMBER_MASK;
1384                                 ep_in_found = 1;
1385                         } else {
1386                                 if (!ep_out_found) {
1387                                         ss->ep_out = ep_addr &
1388                                                 USB_ENDPOINT_NUMBER_MASK;
1389                                         ep_out_found = 1;
1390                                 }
1391                         }
1392                 }
1393
1394                 /* is it an interrupt endpoint? */
1395                 if ((iface->ep_desc[i].bmAttributes &
1396                     USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
1397                         ss->ep_int = iface->ep_desc[i].bEndpointAddress &
1398                                 USB_ENDPOINT_NUMBER_MASK;
1399                         ss->irqinterval = iface->ep_desc[i].bInterval;
1400                 }
1401         }
1402
1403         debug("Endpoints In %d Out %d Int %d\n",
1404               ss->ep_in, ss->ep_out, ss->ep_int);
1405
1406         /* Do some basic sanity checks, and bail if we find a problem */
1407         if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
1408             !ss->ep_in || !ss->ep_out || !ss->ep_int) {
1409                 debug("Problems with device\n");
1410                 return 0;
1411         }
1412
1413         dev->privptr = (void *)ss;
1414
1415         tp = ss->dev_priv;
1416         tp->udev = dev;
1417         tp->intf = iface;
1418
1419         r8152b_get_version(tp);
1420
1421         if (rtl_ops_init(tp))
1422                 return 0;
1423
1424         tp->rtl_ops.init(tp);
1425         tp->rtl_ops.up(tp);
1426
1427         rtl8152_set_speed(tp, AUTONEG_ENABLE,
1428                           tp->supports_gmii ? SPEED_1000 : SPEED_100,
1429                           DUPLEX_FULL);
1430
1431         return 1;
1432 }
1433
1434 int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
1435                                 struct eth_device *eth)
1436 {
1437         if (!eth) {
1438                 debug("%s: missing parameter.\n", __func__);
1439                 return 0;
1440         }
1441
1442         sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++);
1443         eth->init = r8152_init;
1444         eth->send = r8152_send;
1445         eth->recv = r8152_recv;
1446         eth->halt = r8152_halt;
1447         eth->write_hwaddr = r8152_write_hwaddr;
1448         eth->priv = ss;
1449
1450         /* Get the MAC address */
1451         if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0)
1452                 return 0;
1453
1454         debug("MAC %pM\n", eth->enetaddr);
1455         return 1;
1456 }