drivers/usb/dwc3/gadget.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   4  *
   5  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  *
  10  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/gadget.c) and ported
  11  * to uboot.
  12  *
  13  * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier
  14  */
  15
  16 #include <common.h>
  17 #include <cpu_func.h>
  18 #include <malloc.h>
  19 #include <dm/device_compat.h>
  20 #include <dm/devres.h>
  21 #include <linux/bug.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/list.h>
  24
  25 #include <linux/usb/ch9.h>
  26 #include <linux/usb/gadget.h>
  27
  28 #include "core.h"
  29 #include "gadget.h"
  30 #include "io.h"
  31
  32 #include "linux-compat.h"
  33
  34 /**
  35  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  36  * @dwc: pointer to our context structure
  37  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  38  *
  39  * Caller should take care of locking. This function will
  40  * return 0 on success or -EINVAL if wrong Test Selector
  41  * is passed
  42  */
  43 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  44 {
  45         u32             reg;
  46
  47         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  48         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  49
  50         switch (mode) {
  51         case TEST_J:
  52         case TEST_K:
  53         case TEST_SE0_NAK:
  54         case TEST_PACKET:
  55         case TEST_FORCE_EN:
  56                 reg |= mode << 1;
  57                 break;
  58         default:
  59                 return -EINVAL;
  60         }
  61
  62         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  63
  64         return 0;
  65 }
  66
  67 /**
  68  * dwc3_gadget_get_link_state - Gets current state of USB Link
  69  * @dwc: pointer to our context structure
  70  *
  71  * Caller should take care of locking. This function will
  72  * return the link state on success (>= 0) or -ETIMEDOUT.
  73  */
  74 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  75 {
  76         u32             reg;
  77
  78         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  79
  80         return DWC3_DSTS_USBLNKST(reg);
  81 }
  82
  83 /**
  84  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  85  * @dwc: pointer to our context structure
  86  * @state: the state to put link into
  87  *
  88  * Caller should take care of locking. This function will
  89  * return 0 on success or -ETIMEDOUT.
  90  */
  91 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  92 {
  93         int             retries = 10000;
  94         u32             reg;
  95
  96         /*
  97          * Wait until device controller is ready. Only applies to 1.94a and
  98          * later RTL.
  99          */
 100         if (dwc->revision >= DWC3_REVISION_194A) {
 101                 while (--retries) {
 102                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 103                         if (reg & DWC3_DSTS_DCNRD)
 104                                 udelay(5);
 105                         else
 106                                 break;
 107                 }
 108
 109                 if (retries <= 0)
 110                         return -ETIMEDOUT;
 111         }
 112
 113         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 114         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 115
 116         /* set requested state */
 117         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 118         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 119
 120         /*
 121          * The following code is racy when called from dwc3_gadget_wakeup,
 122          * and is not needed, at least on newer versions
 123          */
 124         if (dwc->revision >= DWC3_REVISION_194A)
 125                 return 0;
 126
 127         /* wait for a change in DSTS */
 128         retries = 10000;
 129         while (--retries) {
 130                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 131
 132                 if (DWC3_DSTS_USBLNKST(reg) == state)
 133                         return 0;
 134
 135                 udelay(5);
 136         }
 137
 138         dev_vdbg(dwc->dev, "link state change request timed out\n");
 139
 140         return -ETIMEDOUT;
 141 }
 142
 143 /**
 144  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 145  * @dwc: pointer to our context structure
 146  *
 147  * This function will a best effort FIFO allocation in order
 148  * to improve FIFO usage and throughput, while still allowing
 149  * us to enable as many endpoints as possible.
 150  *
 151  * Keep in mind that this operation will be highly dependent
 152  * on the configured size for RAM1 - which contains TxFifo -,
 153  * the amount of endpoints enabled on coreConsultant tool, and
 154  * the width of the Master Bus.
 155  *
 156  * In the ideal world, we would always be able to satisfy the
 157  * following equation:
 158  *
 159  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 160  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 161  *
 162  * Unfortunately, due to many variables that's not always the case.
 163  */
 164 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 165 {
 166         int             last_fifo_depth = 0;
 167         int             fifo_size;
 168         int             mdwidth;
 169         int             num;
 170
 171         if (!dwc->needs_fifo_resize)
 172                 return 0;
 173
 174         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 175
 176         /* MDWIDTH is represented in bits, we need it in bytes */
 177         mdwidth >>= 3;
 178
 179         /*
 180          * FIXME For now we will only allocate 1 wMaxPacketSize space
 181          * for each enabled endpoint, later patches will come to
 182          * improve this algorithm so that we better use the internal
 183          * FIFO space
 184          */
 185         for (num = 0; num < dwc->num_in_eps; num++) {
 186                 /* bit0 indicates direction; 1 means IN ep */
 187                 struct dwc3_ep  *dep = dwc->eps[(num << 1) | 1];
 188                 int             mult = 1;
 189                 int             tmp;
 190
 191                 if (!(dep->flags & DWC3_EP_ENABLED))
 192                         continue;
 193
 194                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 195                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 196                         mult = 3;
 197
 198                 /*
 199                  * REVISIT: the following assumes we will always have enough
 200                  * space available on the FIFO RAM for all possible use cases.
 201                  * Make sure that's true somehow and change FIFO allocation
 202                  * accordingly.
 203                  *
 204                  * If we have Bulk or Isochronous endpoints, we want
 205                  * them to be able to be very, very fast. So we're giving
 206                  * those endpoints a fifo_size which is enough for 3 full
 207                  * packets
 208                  */
 209                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 210                 tmp += mdwidth;
 211
 212                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 213
 214                 fifo_size |= (last_fifo_depth << 16);
 215
 216                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 217                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 218
 219                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
 220
 221                 last_fifo_depth += (fifo_size & 0xffff);
 222         }
 223
 224         return 0;
 225 }
 226
 227 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 228                 int status)
 229 {
 230         struct dwc3                     *dwc = dep->dwc;
 231
 232         if (req->queued) {
 233                 dep->busy_slot++;
 234                 /*
 235                  * Skip LINK TRB. We can't use req->trb and check for
 236                  * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 237                  * just completed (not the LINK TRB).
 238                  */
 239                 if (((dep->busy_slot & DWC3_TRB_MASK) ==
 240                         DWC3_TRB_NUM- 1) &&
 241                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 242                         dep->busy_slot++;
 243                 req->queued = false;
 244         }
 245
 246         list_del(&req->list);
 247         req->trb = NULL;
 248         if (req->request.length)
 249                 dwc3_flush_cache((uintptr_t)req->request.dma, req->request.length);
 250
 251         if (req->request.status == -EINPROGRESS)
 252                 req->request.status = status;
 253
 254         if (dwc->ep0_bounced && dep->number == 0)
 255                 dwc->ep0_bounced = false;
 256         else
 257                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 258                                 req->direction);
 259
 260         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 261                         req, dep->name, req->request.actual,
 262                         req->request.length, status);
 263
 264         spin_unlock(&dwc->lock);
 265         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 266         spin_lock(&dwc->lock);
 267 }
 268
 269 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 270 {
 271         u32             timeout = 500;
 272         u32             reg;
 273
 274         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 275         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 276
 277         do {
 278                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 279                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 280                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 281                                         DWC3_DGCMD_STATUS(reg));
 282                         return 0;
 283                 }
 284
 285                 /*
 286                  * We can't sleep here, because it's also called from
 287                  * interrupt context.
 288                  */
 289                 timeout--;
 290                 if (!timeout)
 291                         return -ETIMEDOUT;
 292                 udelay(1);
 293         } while (1);
 294 }
 295
 296 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 297                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 298 {
 299         u32                     timeout = 500;
 300         u32                     reg;
 301
 302         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 303         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 304         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 305
 306         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 307         do {
 308                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 309                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 310                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 311                                         DWC3_DEPCMD_STATUS(reg));
 312                         return 0;
 313                 }
 314
 315                 /*
 316                  * We can't sleep here, because it is also called from
 317                  * interrupt context.
 318                  */
 319                 timeout--;
 320                 if (!timeout)
 321                         return -ETIMEDOUT;
 322
 323                 udelay(1);
 324         } while (1);
 325 }
 326
 327 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 328                 struct dwc3_trb *trb)
 329 {
 330         u32             offset = (char *) trb - (char *) dep->trb_pool;
 331
 332         return dep->trb_pool_dma + offset;
 333 }
 334
 335 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 336 {
 337         if (dep->trb_pool)
 338                 return 0;
 339
 340         if (dep->number == 0 || dep->number == 1)
 341                 return 0;
 342
 343         dep->trb_pool = dma_alloc_coherent(sizeof(struct dwc3_trb) *
 344                                            DWC3_TRB_NUM,
 345                                            (unsigned long *)&dep->trb_pool_dma);
 346         if (!dep->trb_pool) {
 347                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 348                                 dep->name);
 349                 return -ENOMEM;
 350         }
 351
 352         return 0;
 353 }
 354
 355 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 356 {
 357         dma_free_coherent(dep->trb_pool);
 358
 359         dep->trb_pool = NULL;
 360         dep->trb_pool_dma = 0;
 361 }
 362
 363 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 364 {
 365         struct dwc3_gadget_ep_cmd_params params;
 366         u32                     cmd;
 367
 368         memset(&params, 0x00, sizeof(params));
 369
 370         if (dep->number != 1) {
 371                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 372                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 373                 if (dep->number > 1) {
 374                         if (dwc->start_config_issued)
 375                                 return 0;
 376                         dwc->start_config_issued = true;
 377                         cmd |= DWC3_DEPCMD_PARAM(2);
 378                 }
 379
 380                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 381         }
 382
 383         return 0;
 384 }
 385
 386 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 387                 const struct usb_endpoint_descriptor *desc,
 388                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 389                 bool ignore, bool restore)
 390 {
 391         struct dwc3_gadget_ep_cmd_params params;
 392
 393         memset(&params, 0x00, sizeof(params));
 394
 395         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 396                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 397
 398         /* Burst size is only needed in SuperSpeed mode */
 399         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 400                 u32 burst = dep->endpoint.maxburst - 1;
 401
 402                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 403         }
 404
 405         if (ignore)
 406                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 407
 408         if (restore) {
 409                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 410                 params.param2 |= dep->saved_state;
 411         }
 412
 413         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 414                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 415
 416         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 417                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 418                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 419                 dep->stream_capable = true;
 420         }
 421
 422         if (!usb_endpoint_xfer_control(desc))
 423                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 424
 425         /*
 426          * We are doing 1:1 mapping for endpoints, meaning
 427          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 428          * so on. We consider the direction bit as part of the physical
 429          * endpoint number. So USB endpoint 0x81 is 0x03.
 430          */
 431         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 432
 433         /*
 434          * We must use the lower 16 TX FIFOs even though
 435          * HW might have more
 436          */
 437         if (dep->direction)
 438                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 439
 440         if (desc->bInterval) {
 441                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 442                 dep->interval = 1 << (desc->bInterval - 1);
 443         }
 444
 445         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 446                         DWC3_DEPCMD_SETEPCONFIG, &params);
 447 }
 448
 449 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 450 {
 451         struct dwc3_gadget_ep_cmd_params params;
 452
 453         memset(&params, 0x00, sizeof(params));
 454
 455         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 456
 457         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 458                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 459 }
 460
 461 /**
 462  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 463  * @dep: endpoint to be initialized
 464  * @desc: USB Endpoint Descriptor
 465  *
 466  * Caller should take care of locking
 467  */
 468 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 469                 const struct usb_endpoint_descriptor *desc,
 470                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 471                 bool ignore, bool restore)
 472 {
 473         struct dwc3             *dwc = dep->dwc;
 474         u32                     reg;
 475         int                     ret;
 476
 477         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 478
 479         if (!(dep->flags & DWC3_EP_ENABLED)) {
 480                 ret = dwc3_gadget_start_config(dwc, dep);
 481                 if (ret)
 482                         return ret;
 483         }
 484
 485         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 486                         restore);
 487         if (ret)
 488                 return ret;
 489
 490         if (!(dep->flags & DWC3_EP_ENABLED)) {
 491                 struct dwc3_trb *trb_st_hw;
 492                 struct dwc3_trb *trb_link;
 493
 494                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 495                 if (ret)
 496                         return ret;
 497
 498                 dep->endpoint.desc = desc;
 499                 dep->comp_desc = comp_desc;
 500                 dep->type = usb_endpoint_type(desc);
 501                 dep->flags |= DWC3_EP_ENABLED;
 502
 503                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 504                 reg |= DWC3_DALEPENA_EP(dep->number);
 505                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 506
 507                 if (!usb_endpoint_xfer_isoc(desc))
 508                         return 0;
 509
 510                 /* Link TRB for ISOC. The HWO bit is never reset */
 511                 trb_st_hw = &dep->trb_pool[0];
 512
 513                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 514                 memset(trb_link, 0, sizeof(*trb_link));
 515
 516                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 517                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 518                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 519                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 520         }
 521
 522         return 0;
 523 }
 524
 525 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 526 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 527 {
 528         struct dwc3_request             *req;
 529
 530         if (!list_empty(&dep->req_queued)) {
 531                 dwc3_stop_active_transfer(dwc, dep->number, true);
 532
 533                 /* - giveback all requests to gadget driver */
 534                 while (!list_empty(&dep->req_queued)) {
 535                         req = next_request(&dep->req_queued);
 536
 537                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 538                 }
 539         }
 540
 541         while (!list_empty(&dep->request_list)) {
 542                 req = next_request(&dep->request_list);
 543
 544                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 545         }
 546 }
 547
 548 /**
 549  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 550  * @dep: the endpoint to disable
 551  *
 552  * This function also removes requests which are currently processed ny the
 553  * hardware and those which are not yet scheduled.
 554  * Caller should take care of locking.
 555  */
 556 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 557 {
 558         struct dwc3             *dwc = dep->dwc;
 559         u32                     reg;
 560
 561         dwc3_remove_requests(dwc, dep);
 562
 563         /* make sure HW endpoint isn't stalled */
 564         if (dep->flags & DWC3_EP_STALL)
 565                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 566
 567         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 568         reg &= ~DWC3_DALEPENA_EP(dep->number);
 569         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 570
 571         dep->stream_capable = false;
 572         dep->endpoint.desc = NULL;
 573         dep->comp_desc = NULL;
 574         dep->type = 0;
 575         dep->flags = 0;
 576
 577         return 0;
 578 }
 579
 580 /* -------------------------------------------------------------------------- */
 581
 582 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 583                 const struct usb_endpoint_descriptor *desc)
 584 {
 585         return -EINVAL;
 586 }
 587
 588 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 589 {
 590         return -EINVAL;
 591 }
 592
 593 /* -------------------------------------------------------------------------- */
 594
 595 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 596                 const struct usb_endpoint_descriptor *desc)
 597 {
 598         struct dwc3_ep                  *dep;
 599         unsigned long                   flags;
 600         int                             ret;
 601
 602         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 603                 pr_debug("dwc3: invalid parameters\n");
 604                 return -EINVAL;
 605         }
 606
 607         if (!desc->wMaxPacketSize) {
 608                 pr_debug("dwc3: missing wMaxPacketSize\n");
 609                 return -EINVAL;
 610         }
 611
 612         dep = to_dwc3_ep(ep);
 613
 614         if (dep->flags & DWC3_EP_ENABLED) {
 615                 WARN(true, "%s is already enabled\n",
 616                                 dep->name);
 617                 return 0;
 618         }
 619
 620         switch (usb_endpoint_type(desc)) {
 621         case USB_ENDPOINT_XFER_CONTROL:
 622                 strlcat(dep->name, "-control", sizeof(dep->name));
 623                 break;
 624         case USB_ENDPOINT_XFER_ISOC:
 625                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 626                 break;
 627         case USB_ENDPOINT_XFER_BULK:
 628                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 629                 break;
 630         case USB_ENDPOINT_XFER_INT:
 631                 strlcat(dep->name, "-int", sizeof(dep->name));
 632                 break;
 633         default:
 634                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 635         }
 636
 637         spin_lock_irqsave(&dwc->lock, flags);
 638         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 639         spin_unlock_irqrestore(&dwc->lock, flags);
 640
 641         return ret;
 642 }
 643
 644 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 645 {
 646         struct dwc3_ep                  *dep;
 647         unsigned long                   flags;
 648         int                             ret;
 649
 650         if (!ep) {
 651                 pr_debug("dwc3: invalid parameters\n");
 652                 return -EINVAL;
 653         }
 654
 655         dep = to_dwc3_ep(ep);
 656
 657         if (!(dep->flags & DWC3_EP_ENABLED)) {
 658                 WARN(true, "%s is already disabled\n",
 659                                 dep->name);
 660                 return 0;
 661         }
 662
 663         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 664                         dep->number >> 1,
 665                         (dep->number & 1) ? "in" : "out");
 666
 667         spin_lock_irqsave(&dwc->lock, flags);
 668         ret = __dwc3_gadget_ep_disable(dep);
 669         spin_unlock_irqrestore(&dwc->lock, flags);
 670
 671         return ret;
 672 }
 673
 674 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 675         gfp_t gfp_flags)
 676 {
 677         struct dwc3_request             *req;
 678         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 679
 680         req = kzalloc(sizeof(*req), gfp_flags);
 681         if (!req)
 682                 return NULL;
 683
 684         req->epnum      = dep->number;
 685         req->dep        = dep;
 686
 687         return &req->request;
 688 }
 689
 690 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 691                 struct usb_request *request)
 692 {
 693         struct dwc3_request             *req = to_dwc3_request(request);
 694
 695         kfree(req);
 696 }
 697
 698 /**
 699  * dwc3_prepare_one_trb - setup one TRB from one request
 700  * @dep: endpoint for which this request is prepared
 701  * @req: dwc3_request pointer
 702  */
 703 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 704                 struct dwc3_request *req, dma_addr_t dma,
 705                 unsigned length, unsigned last, unsigned chain, unsigned node)
 706 {
 707         struct dwc3_trb         *trb;
 708
 709         dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 710                         dep->name, req, (unsigned long long) dma,
 711                         length, last ? " last" : "",
 712                         chain ? " chain" : "");
 713
 714
 715         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 716
 717         if (!req->trb) {
 718                 dwc3_gadget_move_request_queued(req);
 719                 req->trb = trb;
 720                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 721                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 722         }
 723
 724         dep->free_slot++;
 725         /* Skip the LINK-TRB on ISOC */
 726         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 727                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 728                 dep->free_slot++;
 729
 730         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 731         trb->bpl = lower_32_bits(dma);
 732         trb->bph = upper_32_bits(dma);
 733
 734         switch (usb_endpoint_type(dep->endpoint.desc)) {
 735         case USB_ENDPOINT_XFER_CONTROL:
 736                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 737                 break;
 738
 739         case USB_ENDPOINT_XFER_ISOC:
 740                 if (!node)
 741                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 742                 else
 743                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 744                 break;
 745
 746         case USB_ENDPOINT_XFER_BULK:
 747         case USB_ENDPOINT_XFER_INT:
 748                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 749                 break;
 750         default:
 751                 /*
 752                  * This is only possible with faulty memory because we
 753                  * checked it already :)
 754                  */
 755                 BUG();
 756         }
 757
 758         if (!req->request.no_interrupt && !chain)
 759                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 760
 761         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 762                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 763                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 764         } else if (last) {
 765                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 766         }
 767
 768         if (chain)
 769                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 770
 771         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 772                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 773
 774         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 775
 776         dwc3_flush_cache((uintptr_t)dma, length);
 777         dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
 778 }
 779
 780 /*
 781  * dwc3_prepare_trbs - setup TRBs from requests
 782  * @dep: endpoint for which requests are being prepared
 783  * @starting: true if the endpoint is idle and no requests are queued.
 784  *
 785  * The function goes through the requests list and sets up TRBs for the
 786  * transfers. The function returns once there are no more TRBs available or
 787  * it runs out of requests.
 788  */
 789 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 790 {
 791         struct dwc3_request     *req, *n;
 792         u32                     trbs_left;
 793         u32                     max;
 794
 795         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 796
 797         /* the first request must not be queued */
 798         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 799
 800         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 801         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 802                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 803                 if (trbs_left > max)
 804                         trbs_left = max;
 805         }
 806
 807         /*
 808          * If busy & slot are equal than it is either full or empty. If we are
 809          * starting to process requests then we are empty. Otherwise we are
 810          * full and don't do anything
 811          */
 812         if (!trbs_left) {
 813                 if (!starting)
 814                         return;
 815                 trbs_left = DWC3_TRB_NUM;
 816                 /*
 817                  * In case we start from scratch, we queue the ISOC requests
 818                  * starting from slot 1. This is done because we use ring
 819                  * buffer and have no LST bit to stop us. Instead, we place
 820                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 821                  * after the first request so we start at slot 1 and have
 822                  * 7 requests proceed before we hit the first IOC.
 823                  * Other transfer types don't use the ring buffer and are
 824                  * processed from the first TRB until the last one. Since we
 825                  * don't wrap around we have to start at the beginning.
 826                  */
 827                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 828                         dep->busy_slot = 1;
 829                         dep->free_slot = 1;
 830                 } else {
 831                         dep->busy_slot = 0;
 832                         dep->free_slot = 0;
 833                 }
 834         }
 835
 836         /* The last TRB is a link TRB, not used for xfer */
 837         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 838                 return;
 839
 840         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 841                 unsigned        length;
 842                 dma_addr_t      dma;
 843
 844                 dma = req->request.dma;
 845                 length = req->request.length;
 846
 847                 dwc3_prepare_one_trb(dep, req, dma, length,
 848                                      true, false, 0);
 849
 850                 break;
 851         }
 852 }
 853
 854 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 855                 int start_new)
 856 {
 857         struct dwc3_gadget_ep_cmd_params params;
 858         struct dwc3_request             *req;
 859         struct dwc3                     *dwc = dep->dwc;
 860         int                             ret;
 861         u32                             cmd;
 862
 863         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 864                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 865                 return -EBUSY;
 866         }
 867         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 868
 869         /*
 870          * If we are getting here after a short-out-packet we don't enqueue any
 871          * new requests as we try to set the IOC bit only on the last request.
 872          */
 873         if (start_new) {
 874                 if (list_empty(&dep->req_queued))
 875                         dwc3_prepare_trbs(dep, start_new);
 876
 877                 /* req points to the first request which will be sent */
 878                 req = next_request(&dep->req_queued);
 879         } else {
 880                 dwc3_prepare_trbs(dep, start_new);
 881
 882                 /*
 883                  * req points to the first request where HWO changed from 0 to 1
 884                  */
 885                 req = next_request(&dep->req_queued);
 886         }
 887         if (!req) {
 888                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 889                 return 0;
 890         }
 891
 892         memset(&params, 0, sizeof(params));
 893
 894         if (start_new) {
 895                 params.param0 = upper_32_bits(req->trb_dma);
 896                 params.param1 = lower_32_bits(req->trb_dma);
 897                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 898         } else {
 899                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 900         }
 901
 902         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 903         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 904         if (ret < 0) {
 905                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 906
 907                 /*
 908                  * FIXME we need to iterate over the list of requests
 909                  * here and stop, unmap, free and del each of the linked
 910                  * requests instead of what we do now.
 911                  */
 912                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 913                                 req->direction);
 914                 list_del(&req->list);
 915                 return ret;
 916         }
 917
 918         dep->flags |= DWC3_EP_BUSY;
 919
 920         if (start_new) {
 921                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 922                                 dep->number);
 923                 WARN_ON_ONCE(!dep->resource_index);
 924         }
 925
 926         return 0;
 927 }
 928
 929 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
 930                 struct dwc3_ep *dep, u32 cur_uf)
 931 {
 932         u32 uf;
 933
 934         if (list_empty(&dep->request_list)) {
 935                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
 936                         dep->name);
 937                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 938                 return;
 939         }
 940
 941         /* 4 micro frames in the future */
 942         uf = cur_uf + dep->interval * 4;
 943
 944         __dwc3_gadget_kick_transfer(dep, uf, 1);
 945 }
 946
 947 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
 948                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
 949 {
 950         u32 cur_uf, mask;
 951
 952         mask = ~(dep->interval - 1);
 953         cur_uf = event->parameters & mask;
 954
 955         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
 956 }
 957
 958 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
 959 {
 960         struct dwc3             *dwc = dep->dwc;
 961         int                     ret;
 962
 963         req->request.actual     = 0;
 964         req->request.status     = -EINPROGRESS;
 965         req->direction          = dep->direction;
 966         req->epnum              = dep->number;
 967
 968         /*
 969          * DWC3 hangs on OUT requests smaller than maxpacket size,
 970          * so HACK the request length
 971          */
 972         if (dep->direction == 0 &&
 973             req->request.length < dep->endpoint.maxpacket)
 974                 req->request.length = dep->endpoint.maxpacket;
 975
 976         /*
 977          * We only add to our list of requests now and
 978          * start consuming the list once we get XferNotReady
 979          * IRQ.
 980          *
 981          * That way, we avoid doing anything that we don't need
 982          * to do now and defer it until the point we receive a
 983          * particular token from the Host side.
 984          *
 985          * This will also avoid Host cancelling URBs due to too
 986          * many NAKs.
 987          */
 988         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 989                         dep->direction);
 990         if (ret)
 991                 return ret;
 992
 993         list_add_tail(&req->list, &dep->request_list);
 994
 995         /*
 996          * There are a few special cases:
 997          *
 998          * 1. XferNotReady with empty list of requests. We need to kick the
 999          *    transfer here in that situation, otherwise we will be NAKing
1000          *    forever. If we get XferNotReady before gadget driver has a
1001          *    chance to queue a request, we will ACK the IRQ but won't be
1002          *    able to receive the data until the next request is queued.
1003          *    The following code is handling exactly that.
1004          *
1005          */
1006         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1007                 /*
1008                  * If xfernotready is already elapsed and it is a case
1009                  * of isoc transfer, then issue END TRANSFER, so that
1010                  * you can receive xfernotready again and can have
1011                  * notion of current microframe.
1012                  */
1013                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1014                         if (list_empty(&dep->req_queued)) {
1015                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1016                                 dep->flags = DWC3_EP_ENABLED;
1017                         }
1018                         return 0;
1019                 }
1020
1021                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1022                 if (ret && ret != -EBUSY)
1023                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1024                                         dep->name);
1025                 return ret;
1026         }
1027
1028         /*
1029          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1030          *    kick the transfer here after queuing a request, otherwise the
1031          *    core may not see the modified TRB(s).
1032          */
1033         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1034                         (dep->flags & DWC3_EP_BUSY) &&
1035                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1036                 WARN_ON_ONCE(!dep->resource_index);
1037                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1038                                 false);
1039                 if (ret && ret != -EBUSY)
1040                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1041                                         dep->name);
1042                 return ret;
1043         }
1044
1045         /*
1046          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1047          * right away, otherwise host will not know we have streams to be
1048          * handled.
1049          */
1050         if (dep->stream_capable) {
1051                 int     ret;
1052
1053                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1054                 if (ret && ret != -EBUSY) {
1055                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1056                                         dep->name);
1057                 }
1058         }
1059
1060         return 0;
1061 }
1062
1063 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1064         gfp_t gfp_flags)
1065 {
1066         struct dwc3_request             *req = to_dwc3_request(request);
1067         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1068
1069         unsigned long                   flags;
1070
1071         int                             ret;
1072
1073         spin_lock_irqsave(&dwc->lock, flags);
1074         if (!dep->endpoint.desc) {
1075                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1076                                 request, ep->name);
1077                 ret = -ESHUTDOWN;
1078                 goto out;
1079         }
1080
1081         if (req->dep != dep) {
1082                 WARN(true, "request %p belongs to '%s'\n",
1083                                 request, req->dep->name);
1084                 ret = -EINVAL;
1085                 goto out;
1086         }
1087
1088         dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1089                         request, ep->name, request->length);
1090
1091         ret = __dwc3_gadget_ep_queue(dep, req);
1092
1093 out:
1094         spin_unlock_irqrestore(&dwc->lock, flags);
1095
1096         return ret;
1097 }
1098
1099 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1100                 struct usb_request *request)
1101 {
1102         struct dwc3_request             *req = to_dwc3_request(request);
1103         struct dwc3_request             *r = NULL;
1104
1105         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1106         struct dwc3                     *dwc = dep->dwc;
1107
1108         unsigned long                   flags;
1109         int                             ret = 0;
1110
1111         spin_lock_irqsave(&dwc->lock, flags);
1112
1113         list_for_each_entry(r, &dep->request_list, list) {
1114                 if (r == req)
1115                         break;
1116         }
1117
1118         if (r != req) {
1119                 list_for_each_entry(r, &dep->req_queued, list) {
1120                         if (r == req)
1121                                 break;
1122                 }
1123                 if (r == req) {
1124                         /* wait until it is processed */
1125                         dwc3_stop_active_transfer(dwc, dep->number, true);
1126                         goto out1;
1127                 }
1128                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1129                                 request, ep->name);
1130                 ret = -EINVAL;
1131                 goto out0;
1132         }
1133
1134 out1:
1135         /* giveback the request */
1136         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1137
1138 out0:
1139         spin_unlock_irqrestore(&dwc->lock, flags);
1140
1141         return ret;
1142 }
1143
1144 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1145 {
1146         struct dwc3_gadget_ep_cmd_params        params;
1147         struct dwc3                             *dwc = dep->dwc;
1148         int                                     ret;
1149
1150         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1151                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1152                 return -EINVAL;
1153         }
1154
1155         memset(&params, 0x00, sizeof(params));
1156
1157         if (value) {
1158                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1159                                 (!list_empty(&dep->req_queued) ||
1160                                  !list_empty(&dep->request_list)))) {
1161                         dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1162                                         dep->name);
1163                         return -EAGAIN;
1164                 }
1165
1166                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1167                         DWC3_DEPCMD_SETSTALL, &params);
1168                 if (ret)
1169                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1170                                         dep->name);
1171                 else
1172                         dep->flags |= DWC3_EP_STALL;
1173         } else {
1174                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1175                         DWC3_DEPCMD_CLEARSTALL, &params);
1176                 if (ret)
1177                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1178                                         dep->name);
1179                 else
1180                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1181         }
1182
1183         return ret;
1184 }
1185
1186 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1187 {
1188         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1189
1190         unsigned long                   flags;
1191
1192         int                             ret;
1193
1194         spin_lock_irqsave(&dwc->lock, flags);
1195         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1196         spin_unlock_irqrestore(&dwc->lock, flags);
1197
1198         return ret;
1199 }
1200
1201 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1202 {
1203         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1204         unsigned long                   flags;
1205         int                             ret;
1206
1207         spin_lock_irqsave(&dwc->lock, flags);
1208         dep->flags |= DWC3_EP_WEDGE;
1209
1210         if (dep->number == 0 || dep->number == 1)
1211                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1212         else
1213                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1214         spin_unlock_irqrestore(&dwc->lock, flags);
1215
1216         return ret;
1217 }
1218
1219 /* -------------------------------------------------------------------------- */
1220
1221 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1222         .bLength        = USB_DT_ENDPOINT_SIZE,
1223         .bDescriptorType = USB_DT_ENDPOINT,
1224         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1225 };
1226
1227 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1228         .enable         = dwc3_gadget_ep0_enable,
1229         .disable        = dwc3_gadget_ep0_disable,
1230         .alloc_request  = dwc3_gadget_ep_alloc_request,
1231         .free_request   = dwc3_gadget_ep_free_request,
1232         .queue          = dwc3_gadget_ep0_queue,
1233         .dequeue        = dwc3_gadget_ep_dequeue,
1234         .set_halt       = dwc3_gadget_ep0_set_halt,
1235         .set_wedge      = dwc3_gadget_ep_set_wedge,
1236 };
1237
1238 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1239         .enable         = dwc3_gadget_ep_enable,
1240         .disable        = dwc3_gadget_ep_disable,
1241         .alloc_request  = dwc3_gadget_ep_alloc_request,
1242         .free_request   = dwc3_gadget_ep_free_request,
1243         .queue          = dwc3_gadget_ep_queue,
1244         .dequeue        = dwc3_gadget_ep_dequeue,
1245         .set_halt       = dwc3_gadget_ep_set_halt,
1246         .set_wedge      = dwc3_gadget_ep_set_wedge,
1247 };
1248
1249 /* -------------------------------------------------------------------------- */
1250
1251 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1252 {
1253         struct dwc3             *dwc = gadget_to_dwc(g);
1254         u32                     reg;
1255
1256         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1257         return DWC3_DSTS_SOFFN(reg);
1258 }
1259
1260 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1261 {
1262         struct dwc3             *dwc = gadget_to_dwc(g);
1263
1264         unsigned long           timeout;
1265         unsigned long           flags;
1266
1267         u32                     reg;
1268
1269         int                     ret = 0;
1270
1271         u8                      link_state;
1272         u8                      speed;
1273
1274         spin_lock_irqsave(&dwc->lock, flags);
1275
1276         /*
1277          * According to the Databook Remote wakeup request should
1278          * be issued only when the device is in early suspend state.
1279          *
1280          * We can check that via USB Link State bits in DSTS register.
1281          */
1282         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1283
1284         speed = reg & DWC3_DSTS_CONNECTSPD;
1285         if (speed == DWC3_DSTS_SUPERSPEED) {
1286                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1287                 ret = -EINVAL;
1288                 goto out;
1289         }
1290
1291         link_state = DWC3_DSTS_USBLNKST(reg);
1292
1293         switch (link_state) {
1294         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1295         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1296                 break;
1297         default:
1298                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1299                                 link_state);
1300                 ret = -EINVAL;
1301                 goto out;
1302         }
1303
1304         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1305         if (ret < 0) {
1306                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1307                 goto out;
1308         }
1309
1310         /* Recent versions do this automatically */
1311         if (dwc->revision < DWC3_REVISION_194A) {
1312                 /* write zeroes to Link Change Request */
1313                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1314                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1315                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1316         }
1317
1318         /* poll until Link State changes to ON */
1319         timeout = 1000;
1320
1321         while (timeout--) {
1322                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1323
1324                 /* in HS, means ON */
1325                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1326                         break;
1327         }
1328
1329         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1330                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1331                 ret = -EINVAL;
1332         }
1333
1334 out:
1335         spin_unlock_irqrestore(&dwc->lock, flags);
1336
1337         return ret;
1338 }
1339
1340 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1341                 int is_selfpowered)
1342 {
1343         struct dwc3             *dwc = gadget_to_dwc(g);
1344         unsigned long           flags;
1345
1346         spin_lock_irqsave(&dwc->lock, flags);
1347         dwc->is_selfpowered = !!is_selfpowered;
1348         spin_unlock_irqrestore(&dwc->lock, flags);
1349
1350         return 0;
1351 }
1352
1353 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1354 {
1355         u32                     reg;
1356         u32                     timeout = 500;
1357
1358         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1359         if (is_on) {
1360                 if (dwc->revision <= DWC3_REVISION_187A) {
1361                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1362                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1363                 }
1364
1365                 if (dwc->revision >= DWC3_REVISION_194A)
1366                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1367                 reg |= DWC3_DCTL_RUN_STOP;
1368
1369                 if (dwc->has_hibernation)
1370                         reg |= DWC3_DCTL_KEEP_CONNECT;
1371
1372                 dwc->pullups_connected = true;
1373         } else {
1374                 reg &= ~DWC3_DCTL_RUN_STOP;
1375
1376                 if (dwc->has_hibernation && !suspend)
1377                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1378
1379                 dwc->pullups_connected = false;
1380         }
1381
1382         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1383
1384         do {
1385                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1386                 if (is_on) {
1387                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1388                                 break;
1389                 } else {
1390                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1391                                 break;
1392                 }
1393                 timeout--;
1394                 if (!timeout)
1395                         return -ETIMEDOUT;
1396                 udelay(1);
1397         } while (1);
1398
1399         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1400                         dwc->gadget_driver
1401                         ? dwc->gadget_driver->function : "no-function",
1402                         is_on ? "connect" : "disconnect");
1403
1404         return 0;
1405 }
1406
1407 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1408 {
1409         struct dwc3             *dwc = gadget_to_dwc(g);
1410         unsigned long           flags;
1411         int                     ret;
1412
1413         is_on = !!is_on;
1414
1415         spin_lock_irqsave(&dwc->lock, flags);
1416         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1417         spin_unlock_irqrestore(&dwc->lock, flags);
1418
1419         return ret;
1420 }
1421
1422 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1423 {
1424         u32                     reg;
1425
1426         /* Enable all but Start and End of Frame IRQs */
1427         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1428                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1429                         DWC3_DEVTEN_CMDCMPLTEN |
1430                         DWC3_DEVTEN_ERRTICERREN |
1431                         DWC3_DEVTEN_WKUPEVTEN |
1432                         DWC3_DEVTEN_ULSTCNGEN |
1433                         DWC3_DEVTEN_CONNECTDONEEN |
1434                         DWC3_DEVTEN_USBRSTEN |
1435                         DWC3_DEVTEN_DISCONNEVTEN);
1436
1437         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1438 }
1439
1440 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1441 {
1442         /* mask all interrupts */
1443         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1444 }
1445
1446 static int dwc3_gadget_start(struct usb_gadget *g,
1447                 struct usb_gadget_driver *driver)
1448 {
1449         struct dwc3             *dwc = gadget_to_dwc(g);
1450         struct dwc3_ep          *dep;
1451         unsigned long           flags;
1452         int                     ret = 0;
1453         u32                     reg;
1454
1455         spin_lock_irqsave(&dwc->lock, flags);
1456
1457         if (dwc->gadget_driver) {
1458                 dev_err(dwc->dev, "%s is already bound to %s\n",
1459                                 dwc->gadget.name,
1460                                 dwc->gadget_driver->function);
1461                 ret = -EBUSY;
1462                 goto err1;
1463         }
1464
1465         dwc->gadget_driver      = driver;
1466
1467         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1468         reg &= ~(DWC3_DCFG_SPEED_MASK);
1469
1470         /**
1471          * WORKAROUND: DWC3 revision < 2.20a have an issue
1472          * which would cause metastability state on Run/Stop
1473          * bit if we try to force the IP to USB2-only mode.
1474          *
1475          * Because of that, we cannot configure the IP to any
1476          * speed other than the SuperSpeed
1477          *
1478          * Refers to:
1479          *
1480          * STAR#9000525659: Clock Domain Crossing on DCTL in
1481          * USB 2.0 Mode
1482          */
1483         if (dwc->revision < DWC3_REVISION_220A) {
1484                 reg |= DWC3_DCFG_SUPERSPEED;
1485         } else {
1486                 switch (dwc->maximum_speed) {
1487                 case USB_SPEED_LOW:
1488                         reg |= DWC3_DSTS_LOWSPEED;
1489                         break;
1490                 case USB_SPEED_FULL:
1491                         reg |= DWC3_DSTS_FULLSPEED1;
1492                         break;
1493                 case USB_SPEED_HIGH:
1494                         reg |= DWC3_DSTS_HIGHSPEED;
1495                         break;
1496                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1497                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1498                 default:
1499                         reg |= DWC3_DSTS_SUPERSPEED;
1500                 }
1501         }
1502         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1503
1504         dwc->start_config_issued = false;
1505
1506         /* Start with SuperSpeed Default */
1507         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1508
1509         dep = dwc->eps[0];
1510         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1511                         false);
1512         if (ret) {
1513                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1514                 goto err2;
1515         }
1516
1517         dep = dwc->eps[1];
1518         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1519                         false);
1520         if (ret) {
1521                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1522                 goto err3;
1523         }
1524
1525         /* begin to receive SETUP packets */
1526         dwc->ep0state = EP0_SETUP_PHASE;
1527         dwc3_ep0_out_start(dwc);
1528
1529         dwc3_gadget_enable_irq(dwc);
1530
1531         spin_unlock_irqrestore(&dwc->lock, flags);
1532
1533         return 0;
1534
1535 err3:
1536         __dwc3_gadget_ep_disable(dwc->eps[0]);
1537
1538 err2:
1539         dwc->gadget_driver = NULL;
1540
1541 err1:
1542         spin_unlock_irqrestore(&dwc->lock, flags);
1543
1544         return ret;
1545 }
1546
1547 static int dwc3_gadget_stop(struct usb_gadget *g)
1548 {
1549         struct dwc3             *dwc = gadget_to_dwc(g);
1550         unsigned long           flags;
1551
1552         spin_lock_irqsave(&dwc->lock, flags);
1553
1554         dwc3_gadget_disable_irq(dwc);
1555         __dwc3_gadget_ep_disable(dwc->eps[0]);
1556         __dwc3_gadget_ep_disable(dwc->eps[1]);
1557
1558         dwc->gadget_driver      = NULL;
1559
1560         spin_unlock_irqrestore(&dwc->lock, flags);
1561
1562         return 0;
1563 }
1564
1565 static const struct usb_gadget_ops dwc3_gadget_ops = {
1566         .get_frame              = dwc3_gadget_get_frame,
1567         .wakeup                 = dwc3_gadget_wakeup,
1568         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1569         .pullup                 = dwc3_gadget_pullup,
1570         .udc_start              = dwc3_gadget_start,
1571         .udc_stop               = dwc3_gadget_stop,
1572 };
1573
1574 /* -------------------------------------------------------------------------- */
1575
1576 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1577                 u8 num, u32 direction)
1578 {
1579         struct dwc3_ep                  *dep;
1580         u8                              i;
1581
1582         for (i = 0; i < num; i++) {
1583                 u8 epnum = (i << 1) | (!!direction);
1584
1585                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1586                 if (!dep)
1587                         return -ENOMEM;
1588
1589                 dep->dwc = dwc;
1590                 dep->number = epnum;
1591                 dep->direction = !!direction;
1592                 dwc->eps[epnum] = dep;
1593
1594                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1595                                 (epnum & 1) ? "in" : "out");
1596
1597                 dep->endpoint.name = dep->name;
1598
1599                 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1600
1601                 if (epnum == 0 || epnum == 1) {
1602                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1603                         dep->endpoint.maxburst = 1;
1604                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1605                         if (!epnum)
1606                                 dwc->gadget.ep0 = &dep->endpoint;
1607                 } else {
1608                         int             ret;
1609
1610                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1611                         dep->endpoint.max_streams = 15;
1612                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1613                         list_add_tail(&dep->endpoint.ep_list,
1614                                         &dwc->gadget.ep_list);
1615
1616                         ret = dwc3_alloc_trb_pool(dep);
1617                         if (ret)
1618                                 return ret;
1619                 }
1620
1621                 INIT_LIST_HEAD(&dep->request_list);
1622                 INIT_LIST_HEAD(&dep->req_queued);
1623         }
1624
1625         return 0;
1626 }
1627
1628 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1629 {
1630         int                             ret;
1631
1632         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1633
1634         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1635         if (ret < 0) {
1636                 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1637                 return ret;
1638         }
1639
1640         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1641         if (ret < 0) {
1642                 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1643                 return ret;
1644         }
1645
1646         return 0;
1647 }
1648
1649 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1650 {
1651         struct dwc3_ep                  *dep;
1652         u8                              epnum;
1653
1654         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1655                 dep = dwc->eps[epnum];
1656                 if (!dep)
1657                         continue;
1658                 /*
1659                  * Physical endpoints 0 and 1 are special; they form the
1660                  * bi-directional USB endpoint 0.
1661                  *
1662                  * For those two physical endpoints, we don't allocate a TRB
1663                  * pool nor do we add them the endpoints list. Due to that, we
1664                  * shouldn't do these two operations otherwise we would end up
1665                  * with all sorts of bugs when removing dwc3.ko.
1666                  */
1667                 if (epnum != 0 && epnum != 1) {
1668                         dwc3_free_trb_pool(dep);
1669                         list_del(&dep->endpoint.ep_list);
1670                 }
1671
1672                 kfree(dep);
1673         }
1674 }
1675
1676 /* -------------------------------------------------------------------------- */
1677
1678 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1679                 struct dwc3_request *req, struct dwc3_trb *trb,
1680                 const struct dwc3_event_depevt *event, int status)
1681 {
1682         unsigned int            count;
1683         unsigned int            s_pkt = 0;
1684         unsigned int            trb_status;
1685
1686         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1687                 /*
1688                  * We continue despite the error. There is not much we
1689                  * can do. If we don't clean it up we loop forever. If
1690                  * we skip the TRB then it gets overwritten after a
1691                  * while since we use them in a ring buffer. A BUG()
1692                  * would help. Lets hope that if this occurs, someone
1693                  * fixes the root cause instead of looking away :)
1694                  */
1695                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1696                                 dep->name, trb);
1697         count = trb->size & DWC3_TRB_SIZE_MASK;
1698
1699         if (dep->direction) {
1700                 if (count) {
1701                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1702                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1703                                 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1704                                                 dep->name);
1705                                 /*
1706                                  * If missed isoc occurred and there is
1707                                  * no request queued then issue END
1708                                  * TRANSFER, so that core generates
1709                                  * next xfernotready and we will issue
1710                                  * a fresh START TRANSFER.
1711                                  * If there are still queued request
1712                                  * then wait, do not issue either END
1713                                  * or UPDATE TRANSFER, just attach next
1714                                  * request in request_list during
1715                                  * giveback.If any future queued request
1716                                  * is successfully transferred then we
1717                                  * will issue UPDATE TRANSFER for all
1718                                  * request in the request_list.
1719                                  */
1720                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1721                         } else {
1722                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1723                                                 dep->name);
1724                                 status = -ECONNRESET;
1725                         }
1726                 } else {
1727                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1728                 }
1729         } else {
1730                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1731                         s_pkt = 1;
1732         }
1733
1734         /*
1735          * We assume here we will always receive the entire data block
1736          * which we should receive. Meaning, if we program RX to
1737          * receive 4K but we receive only 2K, we assume that's all we
1738          * should receive and we simply bounce the request back to the
1739          * gadget driver for further processing.
1740          */
1741         req->request.actual += req->request.length - count;
1742         if (s_pkt)
1743                 return 1;
1744         if ((event->status & DEPEVT_STATUS_LST) &&
1745                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1746                                 DWC3_TRB_CTRL_HWO)))
1747                 return 1;
1748         if ((event->status & DEPEVT_STATUS_IOC) &&
1749                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1750                 return 1;
1751         return 0;
1752 }
1753
1754 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1755                 const struct dwc3_event_depevt *event, int status)
1756 {
1757         struct dwc3_request     *req;
1758         struct dwc3_trb         *trb;
1759         unsigned int            slot;
1760
1761         req = next_request(&dep->req_queued);
1762         if (!req) {
1763                 WARN_ON_ONCE(1);
1764                 return 1;
1765         }
1766
1767         slot = req->start_slot;
1768         if ((slot == DWC3_TRB_NUM - 1) &&
1769             usb_endpoint_xfer_isoc(dep->endpoint.desc))
1770                 slot++;
1771         slot %= DWC3_TRB_NUM;
1772         trb = &dep->trb_pool[slot];
1773
1774         dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
1775         __dwc3_cleanup_done_trbs(dwc, dep, req, trb, event, status);
1776         dwc3_gadget_giveback(dep, req, status);
1777
1778         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1779                         list_empty(&dep->req_queued)) {
1780                 if (list_empty(&dep->request_list)) {
1781                         /*
1782                          * If there is no entry in request list then do
1783                          * not issue END TRANSFER now. Just set PENDING
1784                          * flag, so that END TRANSFER is issued when an
1785                          * entry is added into request list.
1786                          */
1787                         dep->flags = DWC3_EP_PENDING_REQUEST;
1788                 } else {
1789                         dwc3_stop_active_transfer(dwc, dep->number, true);
1790                         dep->flags = DWC3_EP_ENABLED;
1791                 }
1792                 return 1;
1793         }
1794
1795         return 1;
1796 }
1797
1798 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1799                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1800 {
1801         unsigned                status = 0;
1802         int                     clean_busy;
1803
1804         if (event->status & DEPEVT_STATUS_BUSERR)
1805                 status = -ECONNRESET;
1806
1807         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1808         if (clean_busy)
1809                 dep->flags &= ~DWC3_EP_BUSY;
1810
1811         /*
1812          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1813          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1814          */
1815         if (dwc->revision < DWC3_REVISION_183A) {
1816                 u32             reg;
1817                 int             i;
1818
1819                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1820                         dep = dwc->eps[i];
1821
1822                         if (!(dep->flags & DWC3_EP_ENABLED))
1823                                 continue;
1824
1825                         if (!list_empty(&dep->req_queued))
1826                                 return;
1827                 }
1828
1829                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1830                 reg |= dwc->u1u2;
1831                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1832
1833                 dwc->u1u2 = 0;
1834         }
1835 }
1836
1837 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1838                 const struct dwc3_event_depevt *event)
1839 {
1840         struct dwc3_ep          *dep;
1841         u8                      epnum = event->endpoint_number;
1842
1843         dep = dwc->eps[epnum];
1844
1845         if (!(dep->flags & DWC3_EP_ENABLED))
1846                 return;
1847
1848         if (epnum == 0 || epnum == 1) {
1849                 dwc3_ep0_interrupt(dwc, event);
1850                 return;
1851         }
1852
1853         switch (event->endpoint_event) {
1854         case DWC3_DEPEVT_XFERCOMPLETE:
1855                 dep->resource_index = 0;
1856
1857                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1858                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1859                                         dep->name);
1860                         return;
1861                 }
1862
1863                 dwc3_endpoint_transfer_complete(dwc, dep, event);
1864                 break;
1865         case DWC3_DEPEVT_XFERINPROGRESS:
1866                 dwc3_endpoint_transfer_complete(dwc, dep, event);
1867                 break;
1868         case DWC3_DEPEVT_XFERNOTREADY:
1869                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1870                         dwc3_gadget_start_isoc(dwc, dep, event);
1871                 } else {
1872                         int ret;
1873
1874                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1875                                         dep->name, event->status &
1876                                         DEPEVT_STATUS_TRANSFER_ACTIVE
1877                                         ? "Transfer Active"
1878                                         : "Transfer Not Active");
1879
1880                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1881                         if (!ret || ret == -EBUSY)
1882                                 return;
1883
1884                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1885                                         dep->name);
1886                 }
1887
1888                 break;
1889         case DWC3_DEPEVT_STREAMEVT:
1890                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1891                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1892                                         dep->name);
1893                         return;
1894                 }
1895
1896                 switch (event->status) {
1897                 case DEPEVT_STREAMEVT_FOUND:
1898                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
1899                                         event->parameters);
1900
1901                         break;
1902                 case DEPEVT_STREAMEVT_NOTFOUND:
1903                         /* FALLTHROUGH */
1904                 default:
1905                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1906                 }
1907                 break;
1908         case DWC3_DEPEVT_RXTXFIFOEVT:
1909                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1910                 break;
1911         case DWC3_DEPEVT_EPCMDCMPLT:
1912                 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1913                 break;
1914         }
1915 }
1916
1917 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1918 {
1919         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1920                 spin_unlock(&dwc->lock);
1921                 dwc->gadget_driver->disconnect(&dwc->gadget);
1922                 spin_lock(&dwc->lock);
1923         }
1924 }
1925
1926 static void dwc3_suspend_gadget(struct dwc3 *dwc)
1927 {
1928         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
1929                 spin_unlock(&dwc->lock);
1930                 dwc->gadget_driver->suspend(&dwc->gadget);
1931                 spin_lock(&dwc->lock);
1932         }
1933 }
1934
1935 static void dwc3_resume_gadget(struct dwc3 *dwc)
1936 {
1937         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
1938                 spin_unlock(&dwc->lock);
1939                 dwc->gadget_driver->resume(&dwc->gadget);
1940         }
1941 }
1942
1943 static void dwc3_reset_gadget(struct dwc3 *dwc)
1944 {
1945         if (!dwc->gadget_driver)
1946                 return;
1947
1948         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
1949                 spin_unlock(&dwc->lock);
1950                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
1951                 spin_lock(&dwc->lock);
1952         }
1953 }
1954
1955 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
1956 {
1957         struct dwc3_ep *dep;
1958         struct dwc3_gadget_ep_cmd_params params;
1959         u32 cmd;
1960         int ret;
1961
1962         dep = dwc->eps[epnum];
1963
1964         if (!dep->resource_index)
1965                 return;
1966
1967         /*
1968          * NOTICE: We are violating what the Databook says about the
1969          * EndTransfer command. Ideally we would _always_ wait for the
1970          * EndTransfer Command Completion IRQ, but that's causing too
1971          * much trouble synchronizing between us and gadget driver.
1972          *
1973          * We have discussed this with the IP Provider and it was
1974          * suggested to giveback all requests here, but give HW some
1975          * extra time to synchronize with the interconnect. We're using
1976          * an arbitraty 100us delay for that.
1977          *
1978          * Note also that a similar handling was tested by Synopsys
1979          * (thanks a lot Paul) and nothing bad has come out of it.
1980          * In short, what we're doing is:
1981          *
1982          * - Issue EndTransfer WITH CMDIOC bit set
1983          * - Wait 100us
1984          */
1985
1986         cmd = DWC3_DEPCMD_ENDTRANSFER;
1987         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1988         cmd |= DWC3_DEPCMD_CMDIOC;
1989         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1990         memset(&params, 0, sizeof(params));
1991         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1992         WARN_ON_ONCE(ret);
1993         dep->resource_index = 0;
1994         dep->flags &= ~DWC3_EP_BUSY;
1995         udelay(100);
1996 }
1997
1998 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1999 {
2000         u32 epnum;
2001
2002         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2003                 struct dwc3_ep *dep;
2004
2005                 dep = dwc->eps[epnum];
2006                 if (!dep)
2007                         continue;
2008
2009                 if (!(dep->flags & DWC3_EP_ENABLED))
2010                         continue;
2011
2012                 dwc3_remove_requests(dwc, dep);
2013         }
2014 }
2015
2016 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2017 {
2018         u32 epnum;
2019
2020         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2021                 struct dwc3_ep *dep;
2022                 struct dwc3_gadget_ep_cmd_params params;
2023                 int ret;
2024
2025                 dep = dwc->eps[epnum];
2026                 if (!dep)
2027                         continue;
2028
2029                 if (!(dep->flags & DWC3_EP_STALL))
2030                         continue;
2031
2032                 dep->flags &= ~DWC3_EP_STALL;
2033
2034                 memset(&params, 0, sizeof(params));
2035                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2036                                 DWC3_DEPCMD_CLEARSTALL, &params);
2037                 WARN_ON_ONCE(ret);
2038         }
2039 }
2040
2041 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2042 {
2043         int                     reg;
2044
2045         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2046         reg &= ~DWC3_DCTL_INITU1ENA;
2047         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2048
2049         reg &= ~DWC3_DCTL_INITU2ENA;
2050         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2051
2052         dwc3_disconnect_gadget(dwc);
2053         dwc->start_config_issued = false;
2054
2055         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2056         dwc->setup_packet_pending = false;
2057         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2058 }
2059
2060 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2061 {
2062         u32                     reg;
2063
2064         /*
2065          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2066          * would cause a missing Disconnect Event if there's a
2067          * pending Setup Packet in the FIFO.
2068          *
2069          * There's no suggested workaround on the official Bug
2070          * report, which states that "unless the driver/application
2071          * is doing any special handling of a disconnect event,
2072          * there is no functional issue".
2073          *
2074          * Unfortunately, it turns out that we _do_ some special
2075          * handling of a disconnect event, namely complete all
2076          * pending transfers, notify gadget driver of the
2077          * disconnection, and so on.
2078          *
2079          * Our suggested workaround is to follow the Disconnect
2080          * Event steps here, instead, based on a setup_packet_pending
2081          * flag. Such flag gets set whenever we have a XferNotReady
2082          * event on EP0 and gets cleared on XferComplete for the
2083          * same endpoint.
2084          *
2085          * Refers to:
2086          *
2087          * STAR#9000466709: RTL: Device : Disconnect event not
2088          * generated if setup packet pending in FIFO
2089          */
2090         if (dwc->revision < DWC3_REVISION_188A) {
2091                 if (dwc->setup_packet_pending)
2092                         dwc3_gadget_disconnect_interrupt(dwc);
2093         }
2094
2095         dwc3_reset_gadget(dwc);
2096
2097         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2098         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2099         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2100         dwc->test_mode = false;
2101
2102         dwc3_stop_active_transfers(dwc);
2103         dwc3_clear_stall_all_ep(dwc);
2104         dwc->start_config_issued = false;
2105
2106         /* Reset device address to zero */
2107         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2108         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2109         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2110 }
2111
2112 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2113 {
2114         u32 reg;
2115         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2116
2117         /*
2118          * We change the clock only at SS but I dunno why I would want to do
2119          * this. Maybe it becomes part of the power saving plan.
2120          */
2121
2122         if (speed != DWC3_DSTS_SUPERSPEED)
2123                 return;
2124
2125         /*
2126          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2127          * each time on Connect Done.
2128          */
2129         if (!usb30_clock)
2130                 return;
2131
2132         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2133         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2134         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2135 }
2136
2137 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2138 {
2139         struct dwc3_ep          *dep;
2140         int                     ret;
2141         u32                     reg;
2142         u8                      speed;
2143
2144         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2145         speed = reg & DWC3_DSTS_CONNECTSPD;
2146         dwc->speed = speed;
2147
2148         dwc3_update_ram_clk_sel(dwc, speed);
2149
2150         switch (speed) {
2151         case DWC3_DCFG_SUPERSPEED:
2152                 /*
2153                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2154                  * would cause a missing USB3 Reset event.
2155                  *
2156                  * In such situations, we should force a USB3 Reset
2157                  * event by calling our dwc3_gadget_reset_interrupt()
2158                  * routine.
2159                  *
2160                  * Refers to:
2161                  *
2162                  * STAR#9000483510: RTL: SS : USB3 reset event may
2163                  * not be generated always when the link enters poll
2164                  */
2165                 if (dwc->revision < DWC3_REVISION_190A)
2166                         dwc3_gadget_reset_interrupt(dwc);
2167
2168                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2169                 dwc->gadget.ep0->maxpacket = 512;
2170                 dwc->gadget.speed = USB_SPEED_SUPER;
2171                 break;
2172         case DWC3_DCFG_HIGHSPEED:
2173                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2174                 dwc->gadget.ep0->maxpacket = 64;
2175                 dwc->gadget.speed = USB_SPEED_HIGH;
2176                 break;
2177         case DWC3_DCFG_FULLSPEED2:
2178         case DWC3_DCFG_FULLSPEED1:
2179                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2180                 dwc->gadget.ep0->maxpacket = 64;
2181                 dwc->gadget.speed = USB_SPEED_FULL;
2182                 break;
2183         case DWC3_DCFG_LOWSPEED:
2184                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2185                 dwc->gadget.ep0->maxpacket = 8;
2186                 dwc->gadget.speed = USB_SPEED_LOW;
2187                 break;
2188         }
2189
2190         /* Enable USB2 LPM Capability */
2191
2192         if ((dwc->revision > DWC3_REVISION_194A)
2193                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2194                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2195                 reg |= DWC3_DCFG_LPM_CAP;
2196                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2197
2198                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2199                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2200
2201                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2202
2203                 /*
2204                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2205                  * DCFG.LPMCap is set, core responses with an ACK and the
2206                  * BESL value in the LPM token is less than or equal to LPM
2207                  * NYET threshold.
2208                  */
2209                 if (dwc->revision < DWC3_REVISION_240A  && dwc->has_lpm_erratum)
2210                         WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2211
2212                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2213                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2214
2215                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2216         } else {
2217                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2218                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2219                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2220         }
2221
2222         dep = dwc->eps[0];
2223         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2224                         false);
2225         if (ret) {
2226                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2227                 return;
2228         }
2229
2230         dep = dwc->eps[1];
2231         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2232                         false);
2233         if (ret) {
2234                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2235                 return;
2236         }
2237
2238         /*
2239          * Configure PHY via GUSB3PIPECTLn if required.
2240          *
2241          * Update GTXFIFOSIZn
2242          *
2243          * In both cases reset values should be sufficient.
2244          */
2245 }
2246
2247 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2248 {
2249         /*
2250          * TODO take core out of low power mode when that's
2251          * implemented.
2252          */
2253
2254         dwc->gadget_driver->resume(&dwc->gadget);
2255 }
2256
2257 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2258                 unsigned int evtinfo)
2259 {
2260         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2261         unsigned int            pwropt;
2262
2263         /*
2264          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2265          * Hibernation mode enabled which would show up when device detects
2266          * host-initiated U3 exit.
2267          *
2268          * In that case, device will generate a Link State Change Interrupt
2269          * from U3 to RESUME which is only necessary if Hibernation is
2270          * configured in.
2271          *
2272          * There are no functional changes due to such spurious event and we
2273          * just need to ignore it.
2274          *
2275          * Refers to:
2276          *
2277          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2278          * operational mode
2279          */
2280         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2281         if ((dwc->revision < DWC3_REVISION_250A) &&
2282                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2283                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2284                                 (next == DWC3_LINK_STATE_RESUME)) {
2285                         dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2286                         return;
2287                 }
2288         }
2289
2290         /*
2291          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2292          * on the link partner, the USB session might do multiple entry/exit
2293          * of low power states before a transfer takes place.
2294          *
2295          * Due to this problem, we might experience lower throughput. The
2296          * suggested workaround is to disable DCTL[12:9] bits if we're
2297          * transitioning from U1/U2 to U0 and enable those bits again
2298          * after a transfer completes and there are no pending transfers
2299          * on any of the enabled endpoints.
2300          *
2301          * This is the first half of that workaround.
2302          *
2303          * Refers to:
2304          *
2305          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2306          * core send LGO_Ux entering U0
2307          */
2308         if (dwc->revision < DWC3_REVISION_183A) {
2309                 if (next == DWC3_LINK_STATE_U0) {
2310                         u32     u1u2;
2311                         u32     reg;
2312
2313                         switch (dwc->link_state) {
2314                         case DWC3_LINK_STATE_U1:
2315                         case DWC3_LINK_STATE_U2:
2316                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2317                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2318                                                 | DWC3_DCTL_ACCEPTU2ENA
2319                                                 | DWC3_DCTL_INITU1ENA
2320                                                 | DWC3_DCTL_ACCEPTU1ENA);
2321
2322                                 if (!dwc->u1u2)
2323                                         dwc->u1u2 = reg & u1u2;
2324
2325                                 reg &= ~u1u2;
2326
2327                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2328                                 break;
2329                         default:
2330                                 /* do nothing */
2331                                 break;
2332                         }
2333                 }
2334         }
2335
2336         switch (next) {
2337         case DWC3_LINK_STATE_U1:
2338                 if (dwc->speed == USB_SPEED_SUPER)
2339                         dwc3_suspend_gadget(dwc);
2340                 break;
2341         case DWC3_LINK_STATE_U2:
2342         case DWC3_LINK_STATE_U3:
2343                 dwc3_suspend_gadget(dwc);
2344                 break;
2345         case DWC3_LINK_STATE_RESUME:
2346                 dwc3_resume_gadget(dwc);
2347                 break;
2348         default:
2349                 /* do nothing */
2350                 break;
2351         }
2352
2353         dwc->link_state = next;
2354 }
2355
2356 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2357                 unsigned int evtinfo)
2358 {
2359         unsigned int is_ss = evtinfo & (1UL << 4);
2360
2361         /**
2362          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2363          * have a known issue which can cause USB CV TD.9.23 to fail
2364          * randomly.
2365          *
2366          * Because of this issue, core could generate bogus hibernation
2367          * events which SW needs to ignore.
2368          *
2369          * Refers to:
2370          *
2371          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2372          * Device Fallback from SuperSpeed
2373          */
2374         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2375                 return;
2376
2377         /* enter hibernation here */
2378 }
2379
2380 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2381                 const struct dwc3_event_devt *event)
2382 {
2383         switch (event->type) {
2384         case DWC3_DEVICE_EVENT_DISCONNECT:
2385                 dwc3_gadget_disconnect_interrupt(dwc);
2386                 break;
2387         case DWC3_DEVICE_EVENT_RESET:
2388                 dwc3_gadget_reset_interrupt(dwc);
2389                 break;
2390         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2391                 dwc3_gadget_conndone_interrupt(dwc);
2392                 break;
2393         case DWC3_DEVICE_EVENT_WAKEUP:
2394                 dwc3_gadget_wakeup_interrupt(dwc);
2395                 break;
2396         case DWC3_DEVICE_EVENT_HIBER_REQ:
2397                 if (!dwc->has_hibernation) {
2398                         WARN(1 ,"unexpected hibernation event\n");
2399                         break;
2400                 }
2401                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2402                 break;
2403         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2404                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2405                 break;
2406         case DWC3_DEVICE_EVENT_EOPF:
2407                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2408                 break;
2409         case DWC3_DEVICE_EVENT_SOF:
2410                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2411                 break;
2412         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2413                 dev_vdbg(dwc->dev, "Erratic Error\n");
2414                 break;
2415         case DWC3_DEVICE_EVENT_CMD_CMPL:
2416                 dev_vdbg(dwc->dev, "Command Complete\n");
2417                 break;
2418         case DWC3_DEVICE_EVENT_OVERFLOW:
2419                 dev_vdbg(dwc->dev, "Overflow\n");
2420                 break;
2421         default:
2422                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2423         }
2424 }
2425
2426 static void dwc3_process_event_entry(struct dwc3 *dwc,
2427                 const union dwc3_event *event)
2428 {
2429         /* Endpoint IRQ, handle it and return early */
2430         if (event->type.is_devspec == 0) {
2431                 /* depevt */
2432                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2433         }
2434
2435         switch (event->type.type) {
2436         case DWC3_EVENT_TYPE_DEV:
2437                 dwc3_gadget_interrupt(dwc, &event->devt);
2438                 break;
2439         /* REVISIT what to do with Carkit and I2C events ? */
2440         default:
2441                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2442         }
2443 }
2444
2445 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2446 {
2447         struct dwc3_event_buffer *evt;
2448         irqreturn_t ret = IRQ_NONE;
2449         int left;
2450         u32 reg;
2451
2452         evt = dwc->ev_buffs[buf];
2453         left = evt->count;
2454
2455         if (!(evt->flags & DWC3_EVENT_PENDING))
2456                 return IRQ_NONE;
2457
2458         while (left > 0) {
2459                 union dwc3_event event;
2460
2461                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2462
2463                 dwc3_process_event_entry(dwc, &event);
2464
2465                 /*
2466                  * FIXME we wrap around correctly to the next entry as
2467                  * almost all entries are 4 bytes in size. There is one
2468                  * entry which has 12 bytes which is a regular entry
2469                  * followed by 8 bytes data. ATM I don't know how
2470                  * things are organized if we get next to the a
2471                  * boundary so I worry about that once we try to handle
2472                  * that.
2473                  */
2474                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2475                 left -= 4;
2476
2477                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2478         }
2479
2480         evt->count = 0;
2481         evt->flags &= ~DWC3_EVENT_PENDING;
2482         ret = IRQ_HANDLED;
2483
2484         /* Unmask interrupt */
2485         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2486         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2487         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2488
2489         return ret;
2490 }
2491
2492 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2493 {
2494         struct dwc3 *dwc = _dwc;
2495         unsigned long flags;
2496         irqreturn_t ret = IRQ_NONE;
2497         int i;
2498
2499         spin_lock_irqsave(&dwc->lock, flags);
2500
2501         for (i = 0; i < dwc->num_event_buffers; i++)
2502                 ret |= dwc3_process_event_buf(dwc, i);
2503
2504         spin_unlock_irqrestore(&dwc->lock, flags);
2505
2506         return ret;
2507 }
2508
2509 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2510 {
2511         struct dwc3_event_buffer *evt;
2512         u32 count;
2513         u32 reg;
2514
2515         evt = dwc->ev_buffs[buf];
2516
2517         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2518         count &= DWC3_GEVNTCOUNT_MASK;
2519         if (!count)
2520                 return IRQ_NONE;
2521
2522         evt->count = count;
2523         evt->flags |= DWC3_EVENT_PENDING;
2524
2525         /* Mask interrupt */
2526         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2527         reg |= DWC3_GEVNTSIZ_INTMASK;
2528         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2529
2530         return IRQ_WAKE_THREAD;
2531 }
2532
2533 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2534 {
2535         struct dwc3                     *dwc = _dwc;
2536         int                             i;
2537         irqreturn_t                     ret = IRQ_NONE;
2538
2539         spin_lock(&dwc->lock);
2540
2541         for (i = 0; i < dwc->num_event_buffers; i++) {
2542                 irqreturn_t status;
2543
2544                 status = dwc3_check_event_buf(dwc, i);
2545                 if (status == IRQ_WAKE_THREAD)
2546                         ret = status;
2547         }
2548
2549         spin_unlock(&dwc->lock);
2550
2551         return ret;
2552 }
2553
2554 /**
2555  * dwc3_gadget_init - Initializes gadget related registers
2556  * @dwc: pointer to our controller context structure
2557  *
2558  * Returns 0 on success otherwise negative errno.
2559  */
2560 int dwc3_gadget_init(struct dwc3 *dwc)
2561 {
2562         int                                     ret;
2563
2564         dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req),
2565                                         (unsigned long *)&dwc->ctrl_req_addr);
2566         if (!dwc->ctrl_req) {
2567                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2568                 ret = -ENOMEM;
2569                 goto err0;
2570         }
2571
2572         dwc->ep0_trb = dma_alloc_coherent(sizeof(*dwc->ep0_trb) * 2,
2573                                           (unsigned long *)&dwc->ep0_trb_addr);
2574         if (!dwc->ep0_trb) {
2575                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2576                 ret = -ENOMEM;
2577                 goto err1;
2578         }
2579
2580         dwc->setup_buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
2581                                   DWC3_EP0_BOUNCE_SIZE);
2582         if (!dwc->setup_buf) {
2583                 ret = -ENOMEM;
2584                 goto err2;
2585         }
2586
2587         dwc->ep0_bounce = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE,
2588                                         (unsigned long *)&dwc->ep0_bounce_addr);
2589         if (!dwc->ep0_bounce) {
2590                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2591                 ret = -ENOMEM;
2592                 goto err3;
2593         }
2594
2595         dwc->gadget.ops                 = &dwc3_gadget_ops;
2596         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2597         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2598         dwc->gadget.name                = "dwc3-gadget";
2599
2600         /*
2601          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2602          * on ep out.
2603          */
2604         dwc->gadget.quirk_ep_out_aligned_size = true;
2605
2606         /*
2607          * REVISIT: Here we should clear all pending IRQs to be
2608          * sure we're starting from a well known location.
2609          */
2610
2611         ret = dwc3_gadget_init_endpoints(dwc);
2612         if (ret)
2613                 goto err4;
2614
2615         ret = usb_add_gadget_udc((struct device *)dwc->dev, &dwc->gadget);
2616         if (ret) {
2617                 dev_err(dwc->dev, "failed to register udc\n");
2618                 goto err4;
2619         }
2620
2621         return 0;
2622
2623 err4:
2624         dwc3_gadget_free_endpoints(dwc);
2625         dma_free_coherent(dwc->ep0_bounce);
2626
2627 err3:
2628         kfree(dwc->setup_buf);
2629
2630 err2:
2631         dma_free_coherent(dwc->ep0_trb);
2632
2633 err1:
2634         dma_free_coherent(dwc->ctrl_req);
2635
2636 err0:
2637         return ret;
2638 }
2639
2640 /* -------------------------------------------------------------------------- */
2641
2642 void dwc3_gadget_exit(struct dwc3 *dwc)
2643 {
2644         usb_del_gadget_udc(&dwc->gadget);
2645
2646         dwc3_gadget_free_endpoints(dwc);
2647
2648         dma_free_coherent(dwc->ep0_bounce);
2649
2650         kfree(dwc->setup_buf);
2651
2652         dma_free_coherent(dwc->ep0_trb);
2653
2654         dma_free_coherent(dwc->ctrl_req);
2655 }
2656
2657 /**
2658  * dwc3_gadget_uboot_handle_interrupt - handle dwc3 gadget interrupt
2659  * @dwc: struct dwce *
2660  *
2661  * Handles ep0 and gadget interrupt
2662  *
2663  * Should be called from dwc3 core.
2664  */
2665 void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
2666 {
2667         int ret = dwc3_interrupt(0, dwc);
2668
2669         if (ret == IRQ_WAKE_THREAD) {
2670                 int i;
2671                 struct dwc3_event_buffer *evt;
2672
2673                 dwc3_thread_interrupt(0, dwc);
2674
2675                 /* Clean + Invalidate the buffers after touching them */
2676                 for (i = 0; i < dwc->num_event_buffers; i++) {
2677                         evt = dwc->ev_buffs[i];
2678                         dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
2679                 }
2680         }
2681 }