1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/gadget.c) and ported
13 * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier
18 #include <asm/dma-mapping.h>
19 #include <linux/bug.h>
20 #include <linux/list.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
29 #include "linux-compat.h"
32 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
33 * @dwc: pointer to our context structure
34 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
36 * Caller should take care of locking. This function will
37 * return 0 on success or -EINVAL if wrong Test Selector
40 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
44 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
45 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
59 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
65 * dwc3_gadget_get_link_state - Gets current state of USB Link
66 * @dwc: pointer to our context structure
68 * Caller should take care of locking. This function will
69 * return the link state on success (>= 0) or -ETIMEDOUT.
71 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
75 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
77 return DWC3_DSTS_USBLNKST(reg);
81 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
82 * @dwc: pointer to our context structure
83 * @state: the state to put link into
85 * Caller should take care of locking. This function will
86 * return 0 on success or -ETIMEDOUT.
88 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
94 * Wait until device controller is ready. Only applies to 1.94a and
97 if (dwc->revision >= DWC3_REVISION_194A) {
99 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
100 if (reg & DWC3_DSTS_DCNRD)
110 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
111 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
113 /* set requested state */
114 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
115 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
118 * The following code is racy when called from dwc3_gadget_wakeup,
119 * and is not needed, at least on newer versions
121 if (dwc->revision >= DWC3_REVISION_194A)
124 /* wait for a change in DSTS */
127 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
129 if (DWC3_DSTS_USBLNKST(reg) == state)
135 dev_vdbg(dwc->dev, "link state change request timed out\n");
141 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
142 * @dwc: pointer to our context structure
144 * This function will a best effort FIFO allocation in order
145 * to improve FIFO usage and throughput, while still allowing
146 * us to enable as many endpoints as possible.
148 * Keep in mind that this operation will be highly dependent
149 * on the configured size for RAM1 - which contains TxFifo -,
150 * the amount of endpoints enabled on coreConsultant tool, and
151 * the width of the Master Bus.
153 * In the ideal world, we would always be able to satisfy the
154 * following equation:
156 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
157 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
159 * Unfortunately, due to many variables that's not always the case.
161 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
163 int last_fifo_depth = 0;
168 if (!dwc->needs_fifo_resize)
171 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
173 /* MDWIDTH is represented in bits, we need it in bytes */
177 * FIXME For now we will only allocate 1 wMaxPacketSize space
178 * for each enabled endpoint, later patches will come to
179 * improve this algorithm so that we better use the internal
182 for (num = 0; num < dwc->num_in_eps; num++) {
183 /* bit0 indicates direction; 1 means IN ep */
184 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
188 if (!(dep->flags & DWC3_EP_ENABLED))
191 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
192 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
196 * REVISIT: the following assumes we will always have enough
197 * space available on the FIFO RAM for all possible use cases.
198 * Make sure that's true somehow and change FIFO allocation
201 * If we have Bulk or Isochronous endpoints, we want
202 * them to be able to be very, very fast. So we're giving
203 * those endpoints a fifo_size which is enough for 3 full
206 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
209 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
211 fifo_size |= (last_fifo_depth << 16);
213 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
214 dep->name, last_fifo_depth, fifo_size & 0xffff);
216 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
218 last_fifo_depth += (fifo_size & 0xffff);
224 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
227 struct dwc3 *dwc = dep->dwc;
232 * Skip LINK TRB. We can't use req->trb and check for
233 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
234 * just completed (not the LINK TRB).
236 if (((dep->busy_slot & DWC3_TRB_MASK) ==
238 usb_endpoint_xfer_isoc(dep->endpoint.desc))
243 list_del(&req->list);
245 dwc3_flush_cache((uintptr_t)req->request.dma, req->request.length);
247 if (req->request.status == -EINPROGRESS)
248 req->request.status = status;
250 if (dwc->ep0_bounced && dep->number == 0)
251 dwc->ep0_bounced = false;
253 usb_gadget_unmap_request(&dwc->gadget, &req->request,
256 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
257 req, dep->name, req->request.actual,
258 req->request.length, status);
260 spin_unlock(&dwc->lock);
261 usb_gadget_giveback_request(&dep->endpoint, &req->request);
262 spin_lock(&dwc->lock);
265 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
270 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
271 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
274 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
275 if (!(reg & DWC3_DGCMD_CMDACT)) {
276 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
277 DWC3_DGCMD_STATUS(reg));
282 * We can't sleep here, because it's also called from
292 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
293 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
298 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
299 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
300 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
302 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
304 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
305 if (!(reg & DWC3_DEPCMD_CMDACT)) {
306 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
307 DWC3_DEPCMD_STATUS(reg));
312 * We can't sleep here, because it is also called from
323 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
324 struct dwc3_trb *trb)
326 u32 offset = (char *) trb - (char *) dep->trb_pool;
328 return dep->trb_pool_dma + offset;
331 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
336 if (dep->number == 0 || dep->number == 1)
339 dep->trb_pool = dma_alloc_coherent(sizeof(struct dwc3_trb) *
341 (unsigned long *)&dep->trb_pool_dma);
342 if (!dep->trb_pool) {
343 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
351 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
353 dma_free_coherent(dep->trb_pool);
355 dep->trb_pool = NULL;
356 dep->trb_pool_dma = 0;
359 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
361 struct dwc3_gadget_ep_cmd_params params;
364 memset(¶ms, 0x00, sizeof(params));
366 if (dep->number != 1) {
367 cmd = DWC3_DEPCMD_DEPSTARTCFG;
368 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
369 if (dep->number > 1) {
370 if (dwc->start_config_issued)
372 dwc->start_config_issued = true;
373 cmd |= DWC3_DEPCMD_PARAM(2);
376 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
382 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
383 const struct usb_endpoint_descriptor *desc,
384 const struct usb_ss_ep_comp_descriptor *comp_desc,
385 bool ignore, bool restore)
387 struct dwc3_gadget_ep_cmd_params params;
389 memset(¶ms, 0x00, sizeof(params));
391 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
392 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
394 /* Burst size is only needed in SuperSpeed mode */
395 if (dwc->gadget.speed == USB_SPEED_SUPER) {
396 u32 burst = dep->endpoint.maxburst - 1;
398 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
402 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
405 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
406 params.param2 |= dep->saved_state;
409 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
410 | DWC3_DEPCFG_XFER_NOT_READY_EN;
412 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
413 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
414 | DWC3_DEPCFG_STREAM_EVENT_EN;
415 dep->stream_capable = true;
418 if (!usb_endpoint_xfer_control(desc))
419 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
422 * We are doing 1:1 mapping for endpoints, meaning
423 * Physical Endpoints 2 maps to Logical Endpoint 2 and
424 * so on. We consider the direction bit as part of the physical
425 * endpoint number. So USB endpoint 0x81 is 0x03.
427 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
430 * We must use the lower 16 TX FIFOs even though
434 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
436 if (desc->bInterval) {
437 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
438 dep->interval = 1 << (desc->bInterval - 1);
441 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
442 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
445 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
447 struct dwc3_gadget_ep_cmd_params params;
449 memset(¶ms, 0x00, sizeof(params));
451 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
453 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
454 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
458 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
459 * @dep: endpoint to be initialized
460 * @desc: USB Endpoint Descriptor
462 * Caller should take care of locking
464 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
465 const struct usb_endpoint_descriptor *desc,
466 const struct usb_ss_ep_comp_descriptor *comp_desc,
467 bool ignore, bool restore)
469 struct dwc3 *dwc = dep->dwc;
473 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
475 if (!(dep->flags & DWC3_EP_ENABLED)) {
476 ret = dwc3_gadget_start_config(dwc, dep);
481 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
486 if (!(dep->flags & DWC3_EP_ENABLED)) {
487 struct dwc3_trb *trb_st_hw;
488 struct dwc3_trb *trb_link;
490 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
494 dep->endpoint.desc = desc;
495 dep->comp_desc = comp_desc;
496 dep->type = usb_endpoint_type(desc);
497 dep->flags |= DWC3_EP_ENABLED;
499 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
500 reg |= DWC3_DALEPENA_EP(dep->number);
501 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
503 if (!usb_endpoint_xfer_isoc(desc))
506 /* Link TRB for ISOC. The HWO bit is never reset */
507 trb_st_hw = &dep->trb_pool[0];
509 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
510 memset(trb_link, 0, sizeof(*trb_link));
512 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
513 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
514 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
515 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
521 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
522 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
524 struct dwc3_request *req;
526 if (!list_empty(&dep->req_queued)) {
527 dwc3_stop_active_transfer(dwc, dep->number, true);
529 /* - giveback all requests to gadget driver */
530 while (!list_empty(&dep->req_queued)) {
531 req = next_request(&dep->req_queued);
533 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
537 while (!list_empty(&dep->request_list)) {
538 req = next_request(&dep->request_list);
540 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
545 * __dwc3_gadget_ep_disable - Disables a HW endpoint
546 * @dep: the endpoint to disable
548 * This function also removes requests which are currently processed ny the
549 * hardware and those which are not yet scheduled.
550 * Caller should take care of locking.
552 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
554 struct dwc3 *dwc = dep->dwc;
557 dwc3_remove_requests(dwc, dep);
559 /* make sure HW endpoint isn't stalled */
560 if (dep->flags & DWC3_EP_STALL)
561 __dwc3_gadget_ep_set_halt(dep, 0, false);
563 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
564 reg &= ~DWC3_DALEPENA_EP(dep->number);
565 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
567 dep->stream_capable = false;
568 dep->endpoint.desc = NULL;
569 dep->comp_desc = NULL;
576 /* -------------------------------------------------------------------------- */
578 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
579 const struct usb_endpoint_descriptor *desc)
584 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
589 /* -------------------------------------------------------------------------- */
591 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
592 const struct usb_endpoint_descriptor *desc)
598 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
599 pr_debug("dwc3: invalid parameters\n");
603 if (!desc->wMaxPacketSize) {
604 pr_debug("dwc3: missing wMaxPacketSize\n");
608 dep = to_dwc3_ep(ep);
610 if (dep->flags & DWC3_EP_ENABLED) {
611 WARN(true, "%s is already enabled\n",
616 switch (usb_endpoint_type(desc)) {
617 case USB_ENDPOINT_XFER_CONTROL:
618 strlcat(dep->name, "-control", sizeof(dep->name));
620 case USB_ENDPOINT_XFER_ISOC:
621 strlcat(dep->name, "-isoc", sizeof(dep->name));
623 case USB_ENDPOINT_XFER_BULK:
624 strlcat(dep->name, "-bulk", sizeof(dep->name));
626 case USB_ENDPOINT_XFER_INT:
627 strlcat(dep->name, "-int", sizeof(dep->name));
630 dev_err(dwc->dev, "invalid endpoint transfer type\n");
633 spin_lock_irqsave(&dwc->lock, flags);
634 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
635 spin_unlock_irqrestore(&dwc->lock, flags);
640 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
647 pr_debug("dwc3: invalid parameters\n");
651 dep = to_dwc3_ep(ep);
653 if (!(dep->flags & DWC3_EP_ENABLED)) {
654 WARN(true, "%s is already disabled\n",
659 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
661 (dep->number & 1) ? "in" : "out");
663 spin_lock_irqsave(&dwc->lock, flags);
664 ret = __dwc3_gadget_ep_disable(dep);
665 spin_unlock_irqrestore(&dwc->lock, flags);
670 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
673 struct dwc3_request *req;
674 struct dwc3_ep *dep = to_dwc3_ep(ep);
676 req = kzalloc(sizeof(*req), gfp_flags);
680 req->epnum = dep->number;
683 return &req->request;
686 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
687 struct usb_request *request)
689 struct dwc3_request *req = to_dwc3_request(request);
695 * dwc3_prepare_one_trb - setup one TRB from one request
696 * @dep: endpoint for which this request is prepared
697 * @req: dwc3_request pointer
699 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
700 struct dwc3_request *req, dma_addr_t dma,
701 unsigned length, unsigned last, unsigned chain, unsigned node)
703 struct dwc3_trb *trb;
705 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
706 dep->name, req, (unsigned long long) dma,
707 length, last ? " last" : "",
708 chain ? " chain" : "");
711 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
714 dwc3_gadget_move_request_queued(req);
716 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
717 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
721 /* Skip the LINK-TRB on ISOC */
722 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
723 usb_endpoint_xfer_isoc(dep->endpoint.desc))
726 trb->size = DWC3_TRB_SIZE_LENGTH(length);
727 trb->bpl = lower_32_bits(dma);
728 trb->bph = upper_32_bits(dma);
730 switch (usb_endpoint_type(dep->endpoint.desc)) {
731 case USB_ENDPOINT_XFER_CONTROL:
732 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
735 case USB_ENDPOINT_XFER_ISOC:
737 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
739 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
742 case USB_ENDPOINT_XFER_BULK:
743 case USB_ENDPOINT_XFER_INT:
744 trb->ctrl = DWC3_TRBCTL_NORMAL;
748 * This is only possible with faulty memory because we
749 * checked it already :)
754 if (!req->request.no_interrupt && !chain)
755 trb->ctrl |= DWC3_TRB_CTRL_IOC;
757 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
758 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
759 trb->ctrl |= DWC3_TRB_CTRL_CSP;
761 trb->ctrl |= DWC3_TRB_CTRL_LST;
765 trb->ctrl |= DWC3_TRB_CTRL_CHN;
767 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
768 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
770 trb->ctrl |= DWC3_TRB_CTRL_HWO;
772 dwc3_flush_cache((uintptr_t)dma, length);
773 dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
777 * dwc3_prepare_trbs - setup TRBs from requests
778 * @dep: endpoint for which requests are being prepared
779 * @starting: true if the endpoint is idle and no requests are queued.
781 * The function goes through the requests list and sets up TRBs for the
782 * transfers. The function returns once there are no more TRBs available or
783 * it runs out of requests.
785 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
787 struct dwc3_request *req, *n;
791 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
793 /* the first request must not be queued */
794 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
796 /* Can't wrap around on a non-isoc EP since there's no link TRB */
797 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
798 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
804 * If busy & slot are equal than it is either full or empty. If we are
805 * starting to process requests then we are empty. Otherwise we are
806 * full and don't do anything
811 trbs_left = DWC3_TRB_NUM;
813 * In case we start from scratch, we queue the ISOC requests
814 * starting from slot 1. This is done because we use ring
815 * buffer and have no LST bit to stop us. Instead, we place
816 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
817 * after the first request so we start at slot 1 and have
818 * 7 requests proceed before we hit the first IOC.
819 * Other transfer types don't use the ring buffer and are
820 * processed from the first TRB until the last one. Since we
821 * don't wrap around we have to start at the beginning.
823 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
832 /* The last TRB is a link TRB, not used for xfer */
833 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
836 list_for_each_entry_safe(req, n, &dep->request_list, list) {
840 dma = req->request.dma;
841 length = req->request.length;
843 dwc3_prepare_one_trb(dep, req, dma, length,
850 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
853 struct dwc3_gadget_ep_cmd_params params;
854 struct dwc3_request *req;
855 struct dwc3 *dwc = dep->dwc;
859 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
860 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
863 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
866 * If we are getting here after a short-out-packet we don't enqueue any
867 * new requests as we try to set the IOC bit only on the last request.
870 if (list_empty(&dep->req_queued))
871 dwc3_prepare_trbs(dep, start_new);
873 /* req points to the first request which will be sent */
874 req = next_request(&dep->req_queued);
876 dwc3_prepare_trbs(dep, start_new);
879 * req points to the first request where HWO changed from 0 to 1
881 req = next_request(&dep->req_queued);
884 dep->flags |= DWC3_EP_PENDING_REQUEST;
888 memset(¶ms, 0, sizeof(params));
891 params.param0 = upper_32_bits(req->trb_dma);
892 params.param1 = lower_32_bits(req->trb_dma);
893 cmd = DWC3_DEPCMD_STARTTRANSFER;
895 cmd = DWC3_DEPCMD_UPDATETRANSFER;
898 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
899 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
901 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
904 * FIXME we need to iterate over the list of requests
905 * here and stop, unmap, free and del each of the linked
906 * requests instead of what we do now.
908 usb_gadget_unmap_request(&dwc->gadget, &req->request,
910 list_del(&req->list);
914 dep->flags |= DWC3_EP_BUSY;
917 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
919 WARN_ON_ONCE(!dep->resource_index);
925 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
926 struct dwc3_ep *dep, u32 cur_uf)
930 if (list_empty(&dep->request_list)) {
931 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
933 dep->flags |= DWC3_EP_PENDING_REQUEST;
937 /* 4 micro frames in the future */
938 uf = cur_uf + dep->interval * 4;
940 __dwc3_gadget_kick_transfer(dep, uf, 1);
943 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
944 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
948 mask = ~(dep->interval - 1);
949 cur_uf = event->parameters & mask;
951 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
954 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
956 struct dwc3 *dwc = dep->dwc;
959 req->request.actual = 0;
960 req->request.status = -EINPROGRESS;
961 req->direction = dep->direction;
962 req->epnum = dep->number;
965 * DWC3 hangs on OUT requests smaller than maxpacket size,
966 * so HACK the request length
968 if (dep->direction == 0 &&
969 req->request.length < dep->endpoint.maxpacket)
970 req->request.length = dep->endpoint.maxpacket;
973 * We only add to our list of requests now and
974 * start consuming the list once we get XferNotReady
977 * That way, we avoid doing anything that we don't need
978 * to do now and defer it until the point we receive a
979 * particular token from the Host side.
981 * This will also avoid Host cancelling URBs due to too
984 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
989 list_add_tail(&req->list, &dep->request_list);
992 * There are a few special cases:
994 * 1. XferNotReady with empty list of requests. We need to kick the
995 * transfer here in that situation, otherwise we will be NAKing
996 * forever. If we get XferNotReady before gadget driver has a
997 * chance to queue a request, we will ACK the IRQ but won't be
998 * able to receive the data until the next request is queued.
999 * The following code is handling exactly that.
1002 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1004 * If xfernotready is already elapsed and it is a case
1005 * of isoc transfer, then issue END TRANSFER, so that
1006 * you can receive xfernotready again and can have
1007 * notion of current microframe.
1009 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1010 if (list_empty(&dep->req_queued)) {
1011 dwc3_stop_active_transfer(dwc, dep->number, true);
1012 dep->flags = DWC3_EP_ENABLED;
1017 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1018 if (ret && ret != -EBUSY)
1019 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1025 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1026 * kick the transfer here after queuing a request, otherwise the
1027 * core may not see the modified TRB(s).
1029 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1030 (dep->flags & DWC3_EP_BUSY) &&
1031 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1032 WARN_ON_ONCE(!dep->resource_index);
1033 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1035 if (ret && ret != -EBUSY)
1036 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1042 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1043 * right away, otherwise host will not know we have streams to be
1046 if (dep->stream_capable) {
1049 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1050 if (ret && ret != -EBUSY) {
1051 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1059 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1062 struct dwc3_request *req = to_dwc3_request(request);
1063 struct dwc3_ep *dep = to_dwc3_ep(ep);
1065 unsigned long flags;
1069 spin_lock_irqsave(&dwc->lock, flags);
1070 if (!dep->endpoint.desc) {
1071 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1077 if (req->dep != dep) {
1078 WARN(true, "request %p belongs to '%s'\n",
1079 request, req->dep->name);
1084 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1085 request, ep->name, request->length);
1087 ret = __dwc3_gadget_ep_queue(dep, req);
1090 spin_unlock_irqrestore(&dwc->lock, flags);
1095 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1096 struct usb_request *request)
1098 struct dwc3_request *req = to_dwc3_request(request);
1099 struct dwc3_request *r = NULL;
1101 struct dwc3_ep *dep = to_dwc3_ep(ep);
1102 struct dwc3 *dwc = dep->dwc;
1104 unsigned long flags;
1107 spin_lock_irqsave(&dwc->lock, flags);
1109 list_for_each_entry(r, &dep->request_list, list) {
1115 list_for_each_entry(r, &dep->req_queued, list) {
1120 /* wait until it is processed */
1121 dwc3_stop_active_transfer(dwc, dep->number, true);
1124 dev_err(dwc->dev, "request %p was not queued to %s\n",
1131 /* giveback the request */
1132 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1135 spin_unlock_irqrestore(&dwc->lock, flags);
1140 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1142 struct dwc3_gadget_ep_cmd_params params;
1143 struct dwc3 *dwc = dep->dwc;
1146 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1147 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1151 memset(¶ms, 0x00, sizeof(params));
1154 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1155 (!list_empty(&dep->req_queued) ||
1156 !list_empty(&dep->request_list)))) {
1157 dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1162 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1163 DWC3_DEPCMD_SETSTALL, ¶ms);
1165 dev_err(dwc->dev, "failed to set STALL on %s\n",
1168 dep->flags |= DWC3_EP_STALL;
1170 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1171 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1173 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1176 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1182 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1184 struct dwc3_ep *dep = to_dwc3_ep(ep);
1186 unsigned long flags;
1190 spin_lock_irqsave(&dwc->lock, flags);
1191 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1192 spin_unlock_irqrestore(&dwc->lock, flags);
1197 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1199 struct dwc3_ep *dep = to_dwc3_ep(ep);
1200 unsigned long flags;
1203 spin_lock_irqsave(&dwc->lock, flags);
1204 dep->flags |= DWC3_EP_WEDGE;
1206 if (dep->number == 0 || dep->number == 1)
1207 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1209 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1210 spin_unlock_irqrestore(&dwc->lock, flags);
1215 /* -------------------------------------------------------------------------- */
1217 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1218 .bLength = USB_DT_ENDPOINT_SIZE,
1219 .bDescriptorType = USB_DT_ENDPOINT,
1220 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1223 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1224 .enable = dwc3_gadget_ep0_enable,
1225 .disable = dwc3_gadget_ep0_disable,
1226 .alloc_request = dwc3_gadget_ep_alloc_request,
1227 .free_request = dwc3_gadget_ep_free_request,
1228 .queue = dwc3_gadget_ep0_queue,
1229 .dequeue = dwc3_gadget_ep_dequeue,
1230 .set_halt = dwc3_gadget_ep0_set_halt,
1231 .set_wedge = dwc3_gadget_ep_set_wedge,
1234 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1235 .enable = dwc3_gadget_ep_enable,
1236 .disable = dwc3_gadget_ep_disable,
1237 .alloc_request = dwc3_gadget_ep_alloc_request,
1238 .free_request = dwc3_gadget_ep_free_request,
1239 .queue = dwc3_gadget_ep_queue,
1240 .dequeue = dwc3_gadget_ep_dequeue,
1241 .set_halt = dwc3_gadget_ep_set_halt,
1242 .set_wedge = dwc3_gadget_ep_set_wedge,
1245 /* -------------------------------------------------------------------------- */
1247 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1249 struct dwc3 *dwc = gadget_to_dwc(g);
1252 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1253 return DWC3_DSTS_SOFFN(reg);
1256 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1258 struct dwc3 *dwc = gadget_to_dwc(g);
1260 unsigned long timeout;
1261 unsigned long flags;
1270 spin_lock_irqsave(&dwc->lock, flags);
1273 * According to the Databook Remote wakeup request should
1274 * be issued only when the device is in early suspend state.
1276 * We can check that via USB Link State bits in DSTS register.
1278 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1280 speed = reg & DWC3_DSTS_CONNECTSPD;
1281 if (speed == DWC3_DSTS_SUPERSPEED) {
1282 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1287 link_state = DWC3_DSTS_USBLNKST(reg);
1289 switch (link_state) {
1290 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1291 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1294 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1300 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1302 dev_err(dwc->dev, "failed to put link in Recovery\n");
1306 /* Recent versions do this automatically */
1307 if (dwc->revision < DWC3_REVISION_194A) {
1308 /* write zeroes to Link Change Request */
1309 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1310 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1311 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1314 /* poll until Link State changes to ON */
1318 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1320 /* in HS, means ON */
1321 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1325 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1326 dev_err(dwc->dev, "failed to send remote wakeup\n");
1331 spin_unlock_irqrestore(&dwc->lock, flags);
1336 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1339 struct dwc3 *dwc = gadget_to_dwc(g);
1340 unsigned long flags;
1342 spin_lock_irqsave(&dwc->lock, flags);
1343 dwc->is_selfpowered = !!is_selfpowered;
1344 spin_unlock_irqrestore(&dwc->lock, flags);
1349 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1354 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1356 if (dwc->revision <= DWC3_REVISION_187A) {
1357 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1358 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1361 if (dwc->revision >= DWC3_REVISION_194A)
1362 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1363 reg |= DWC3_DCTL_RUN_STOP;
1365 if (dwc->has_hibernation)
1366 reg |= DWC3_DCTL_KEEP_CONNECT;
1368 dwc->pullups_connected = true;
1370 reg &= ~DWC3_DCTL_RUN_STOP;
1372 if (dwc->has_hibernation && !suspend)
1373 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1375 dwc->pullups_connected = false;
1378 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1381 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1383 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1386 if (reg & DWC3_DSTS_DEVCTRLHLT)
1395 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1397 ? dwc->gadget_driver->function : "no-function",
1398 is_on ? "connect" : "disconnect");
1403 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1405 struct dwc3 *dwc = gadget_to_dwc(g);
1406 unsigned long flags;
1411 spin_lock_irqsave(&dwc->lock, flags);
1412 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1413 spin_unlock_irqrestore(&dwc->lock, flags);
1418 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1422 /* Enable all but Start and End of Frame IRQs */
1423 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1424 DWC3_DEVTEN_EVNTOVERFLOWEN |
1425 DWC3_DEVTEN_CMDCMPLTEN |
1426 DWC3_DEVTEN_ERRTICERREN |
1427 DWC3_DEVTEN_WKUPEVTEN |
1428 DWC3_DEVTEN_ULSTCNGEN |
1429 DWC3_DEVTEN_CONNECTDONEEN |
1430 DWC3_DEVTEN_USBRSTEN |
1431 DWC3_DEVTEN_DISCONNEVTEN);
1433 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1436 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1438 /* mask all interrupts */
1439 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1442 static int dwc3_gadget_start(struct usb_gadget *g,
1443 struct usb_gadget_driver *driver)
1445 struct dwc3 *dwc = gadget_to_dwc(g);
1446 struct dwc3_ep *dep;
1447 unsigned long flags;
1451 spin_lock_irqsave(&dwc->lock, flags);
1453 if (dwc->gadget_driver) {
1454 dev_err(dwc->dev, "%s is already bound to %s\n",
1456 dwc->gadget_driver->function);
1461 dwc->gadget_driver = driver;
1463 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1464 reg &= ~(DWC3_DCFG_SPEED_MASK);
1467 * WORKAROUND: DWC3 revision < 2.20a have an issue
1468 * which would cause metastability state on Run/Stop
1469 * bit if we try to force the IP to USB2-only mode.
1471 * Because of that, we cannot configure the IP to any
1472 * speed other than the SuperSpeed
1476 * STAR#9000525659: Clock Domain Crossing on DCTL in
1479 if (dwc->revision < DWC3_REVISION_220A) {
1480 reg |= DWC3_DCFG_SUPERSPEED;
1482 switch (dwc->maximum_speed) {
1484 reg |= DWC3_DSTS_LOWSPEED;
1486 case USB_SPEED_FULL:
1487 reg |= DWC3_DSTS_FULLSPEED1;
1489 case USB_SPEED_HIGH:
1490 reg |= DWC3_DSTS_HIGHSPEED;
1492 case USB_SPEED_SUPER: /* FALLTHROUGH */
1493 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1495 reg |= DWC3_DSTS_SUPERSPEED;
1498 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1500 dwc->start_config_issued = false;
1502 /* Start with SuperSpeed Default */
1503 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1506 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1509 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1514 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1517 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1521 /* begin to receive SETUP packets */
1522 dwc->ep0state = EP0_SETUP_PHASE;
1523 dwc3_ep0_out_start(dwc);
1525 dwc3_gadget_enable_irq(dwc);
1527 spin_unlock_irqrestore(&dwc->lock, flags);
1532 __dwc3_gadget_ep_disable(dwc->eps[0]);
1535 dwc->gadget_driver = NULL;
1538 spin_unlock_irqrestore(&dwc->lock, flags);
1543 static int dwc3_gadget_stop(struct usb_gadget *g)
1545 struct dwc3 *dwc = gadget_to_dwc(g);
1546 unsigned long flags;
1548 spin_lock_irqsave(&dwc->lock, flags);
1550 dwc3_gadget_disable_irq(dwc);
1551 __dwc3_gadget_ep_disable(dwc->eps[0]);
1552 __dwc3_gadget_ep_disable(dwc->eps[1]);
1554 dwc->gadget_driver = NULL;
1556 spin_unlock_irqrestore(&dwc->lock, flags);
1561 static const struct usb_gadget_ops dwc3_gadget_ops = {
1562 .get_frame = dwc3_gadget_get_frame,
1563 .wakeup = dwc3_gadget_wakeup,
1564 .set_selfpowered = dwc3_gadget_set_selfpowered,
1565 .pullup = dwc3_gadget_pullup,
1566 .udc_start = dwc3_gadget_start,
1567 .udc_stop = dwc3_gadget_stop,
1570 /* -------------------------------------------------------------------------- */
1572 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1573 u8 num, u32 direction)
1575 struct dwc3_ep *dep;
1578 for (i = 0; i < num; i++) {
1579 u8 epnum = (i << 1) | (!!direction);
1581 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1586 dep->number = epnum;
1587 dep->direction = !!direction;
1588 dwc->eps[epnum] = dep;
1590 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1591 (epnum & 1) ? "in" : "out");
1593 dep->endpoint.name = dep->name;
1595 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1597 if (epnum == 0 || epnum == 1) {
1598 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1599 dep->endpoint.maxburst = 1;
1600 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1602 dwc->gadget.ep0 = &dep->endpoint;
1606 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1607 dep->endpoint.max_streams = 15;
1608 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1609 list_add_tail(&dep->endpoint.ep_list,
1610 &dwc->gadget.ep_list);
1612 ret = dwc3_alloc_trb_pool(dep);
1617 INIT_LIST_HEAD(&dep->request_list);
1618 INIT_LIST_HEAD(&dep->req_queued);
1624 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1628 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1630 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1632 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1636 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1638 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1645 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1647 struct dwc3_ep *dep;
1650 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1651 dep = dwc->eps[epnum];
1655 * Physical endpoints 0 and 1 are special; they form the
1656 * bi-directional USB endpoint 0.
1658 * For those two physical endpoints, we don't allocate a TRB
1659 * pool nor do we add them the endpoints list. Due to that, we
1660 * shouldn't do these two operations otherwise we would end up
1661 * with all sorts of bugs when removing dwc3.ko.
1663 if (epnum != 0 && epnum != 1) {
1664 dwc3_free_trb_pool(dep);
1665 list_del(&dep->endpoint.ep_list);
1672 /* -------------------------------------------------------------------------- */
1674 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1675 struct dwc3_request *req, struct dwc3_trb *trb,
1676 const struct dwc3_event_depevt *event, int status)
1679 unsigned int s_pkt = 0;
1680 unsigned int trb_status;
1682 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1684 * We continue despite the error. There is not much we
1685 * can do. If we don't clean it up we loop forever. If
1686 * we skip the TRB then it gets overwritten after a
1687 * while since we use them in a ring buffer. A BUG()
1688 * would help. Lets hope that if this occurs, someone
1689 * fixes the root cause instead of looking away :)
1691 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1693 count = trb->size & DWC3_TRB_SIZE_MASK;
1695 if (dep->direction) {
1697 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1698 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1699 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1702 * If missed isoc occurred and there is
1703 * no request queued then issue END
1704 * TRANSFER, so that core generates
1705 * next xfernotready and we will issue
1706 * a fresh START TRANSFER.
1707 * If there are still queued request
1708 * then wait, do not issue either END
1709 * or UPDATE TRANSFER, just attach next
1710 * request in request_list during
1711 * giveback.If any future queued request
1712 * is successfully transferred then we
1713 * will issue UPDATE TRANSFER for all
1714 * request in the request_list.
1716 dep->flags |= DWC3_EP_MISSED_ISOC;
1718 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1720 status = -ECONNRESET;
1723 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1726 if (count && (event->status & DEPEVT_STATUS_SHORT))
1731 * We assume here we will always receive the entire data block
1732 * which we should receive. Meaning, if we program RX to
1733 * receive 4K but we receive only 2K, we assume that's all we
1734 * should receive and we simply bounce the request back to the
1735 * gadget driver for further processing.
1737 req->request.actual += req->request.length - count;
1740 if ((event->status & DEPEVT_STATUS_LST) &&
1741 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1742 DWC3_TRB_CTRL_HWO)))
1744 if ((event->status & DEPEVT_STATUS_IOC) &&
1745 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1750 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1751 const struct dwc3_event_depevt *event, int status)
1753 struct dwc3_request *req;
1754 struct dwc3_trb *trb;
1757 req = next_request(&dep->req_queued);
1763 slot = req->start_slot;
1764 if ((slot == DWC3_TRB_NUM - 1) &&
1765 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1767 slot %= DWC3_TRB_NUM;
1768 trb = &dep->trb_pool[slot];
1770 dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
1771 __dwc3_cleanup_done_trbs(dwc, dep, req, trb, event, status);
1772 dwc3_gadget_giveback(dep, req, status);
1774 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1775 list_empty(&dep->req_queued)) {
1776 if (list_empty(&dep->request_list)) {
1778 * If there is no entry in request list then do
1779 * not issue END TRANSFER now. Just set PENDING
1780 * flag, so that END TRANSFER is issued when an
1781 * entry is added into request list.
1783 dep->flags = DWC3_EP_PENDING_REQUEST;
1785 dwc3_stop_active_transfer(dwc, dep->number, true);
1786 dep->flags = DWC3_EP_ENABLED;
1794 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1795 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1797 unsigned status = 0;
1800 if (event->status & DEPEVT_STATUS_BUSERR)
1801 status = -ECONNRESET;
1803 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1805 dep->flags &= ~DWC3_EP_BUSY;
1808 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1809 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1811 if (dwc->revision < DWC3_REVISION_183A) {
1815 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1818 if (!(dep->flags & DWC3_EP_ENABLED))
1821 if (!list_empty(&dep->req_queued))
1825 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1827 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1833 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1834 const struct dwc3_event_depevt *event)
1836 struct dwc3_ep *dep;
1837 u8 epnum = event->endpoint_number;
1839 dep = dwc->eps[epnum];
1841 if (!(dep->flags & DWC3_EP_ENABLED))
1844 if (epnum == 0 || epnum == 1) {
1845 dwc3_ep0_interrupt(dwc, event);
1849 switch (event->endpoint_event) {
1850 case DWC3_DEPEVT_XFERCOMPLETE:
1851 dep->resource_index = 0;
1853 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1854 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1859 dwc3_endpoint_transfer_complete(dwc, dep, event);
1861 case DWC3_DEPEVT_XFERINPROGRESS:
1862 dwc3_endpoint_transfer_complete(dwc, dep, event);
1864 case DWC3_DEPEVT_XFERNOTREADY:
1865 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1866 dwc3_gadget_start_isoc(dwc, dep, event);
1870 dev_vdbg(dwc->dev, "%s: reason %s\n",
1871 dep->name, event->status &
1872 DEPEVT_STATUS_TRANSFER_ACTIVE
1874 : "Transfer Not Active");
1876 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1877 if (!ret || ret == -EBUSY)
1880 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1885 case DWC3_DEPEVT_STREAMEVT:
1886 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1887 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1892 switch (event->status) {
1893 case DEPEVT_STREAMEVT_FOUND:
1894 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1898 case DEPEVT_STREAMEVT_NOTFOUND:
1901 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1904 case DWC3_DEPEVT_RXTXFIFOEVT:
1905 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1907 case DWC3_DEPEVT_EPCMDCMPLT:
1908 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1913 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1915 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1916 spin_unlock(&dwc->lock);
1917 dwc->gadget_driver->disconnect(&dwc->gadget);
1918 spin_lock(&dwc->lock);
1922 static void dwc3_suspend_gadget(struct dwc3 *dwc)
1924 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
1925 spin_unlock(&dwc->lock);
1926 dwc->gadget_driver->suspend(&dwc->gadget);
1927 spin_lock(&dwc->lock);
1931 static void dwc3_resume_gadget(struct dwc3 *dwc)
1933 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
1934 spin_unlock(&dwc->lock);
1935 dwc->gadget_driver->resume(&dwc->gadget);
1939 static void dwc3_reset_gadget(struct dwc3 *dwc)
1941 if (!dwc->gadget_driver)
1944 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
1945 spin_unlock(&dwc->lock);
1946 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
1947 spin_lock(&dwc->lock);
1951 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
1953 struct dwc3_ep *dep;
1954 struct dwc3_gadget_ep_cmd_params params;
1958 dep = dwc->eps[epnum];
1960 if (!dep->resource_index)
1964 * NOTICE: We are violating what the Databook says about the
1965 * EndTransfer command. Ideally we would _always_ wait for the
1966 * EndTransfer Command Completion IRQ, but that's causing too
1967 * much trouble synchronizing between us and gadget driver.
1969 * We have discussed this with the IP Provider and it was
1970 * suggested to giveback all requests here, but give HW some
1971 * extra time to synchronize with the interconnect. We're using
1972 * an arbitraty 100us delay for that.
1974 * Note also that a similar handling was tested by Synopsys
1975 * (thanks a lot Paul) and nothing bad has come out of it.
1976 * In short, what we're doing is:
1978 * - Issue EndTransfer WITH CMDIOC bit set
1982 cmd = DWC3_DEPCMD_ENDTRANSFER;
1983 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1984 cmd |= DWC3_DEPCMD_CMDIOC;
1985 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1986 memset(¶ms, 0, sizeof(params));
1987 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1989 dep->resource_index = 0;
1990 dep->flags &= ~DWC3_EP_BUSY;
1994 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1998 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1999 struct dwc3_ep *dep;
2001 dep = dwc->eps[epnum];
2005 if (!(dep->flags & DWC3_EP_ENABLED))
2008 dwc3_remove_requests(dwc, dep);
2012 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2016 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2017 struct dwc3_ep *dep;
2018 struct dwc3_gadget_ep_cmd_params params;
2021 dep = dwc->eps[epnum];
2025 if (!(dep->flags & DWC3_EP_STALL))
2028 dep->flags &= ~DWC3_EP_STALL;
2030 memset(¶ms, 0, sizeof(params));
2031 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2032 DWC3_DEPCMD_CLEARSTALL, ¶ms);
2037 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2041 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2042 reg &= ~DWC3_DCTL_INITU1ENA;
2043 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2045 reg &= ~DWC3_DCTL_INITU2ENA;
2046 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2048 dwc3_disconnect_gadget(dwc);
2049 dwc->start_config_issued = false;
2051 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2052 dwc->setup_packet_pending = false;
2053 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2056 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2061 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2062 * would cause a missing Disconnect Event if there's a
2063 * pending Setup Packet in the FIFO.
2065 * There's no suggested workaround on the official Bug
2066 * report, which states that "unless the driver/application
2067 * is doing any special handling of a disconnect event,
2068 * there is no functional issue".
2070 * Unfortunately, it turns out that we _do_ some special
2071 * handling of a disconnect event, namely complete all
2072 * pending transfers, notify gadget driver of the
2073 * disconnection, and so on.
2075 * Our suggested workaround is to follow the Disconnect
2076 * Event steps here, instead, based on a setup_packet_pending
2077 * flag. Such flag gets set whenever we have a XferNotReady
2078 * event on EP0 and gets cleared on XferComplete for the
2083 * STAR#9000466709: RTL: Device : Disconnect event not
2084 * generated if setup packet pending in FIFO
2086 if (dwc->revision < DWC3_REVISION_188A) {
2087 if (dwc->setup_packet_pending)
2088 dwc3_gadget_disconnect_interrupt(dwc);
2091 dwc3_reset_gadget(dwc);
2093 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2094 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2095 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2096 dwc->test_mode = false;
2098 dwc3_stop_active_transfers(dwc);
2099 dwc3_clear_stall_all_ep(dwc);
2100 dwc->start_config_issued = false;
2102 /* Reset device address to zero */
2103 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2104 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2105 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2108 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2111 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2114 * We change the clock only at SS but I dunno why I would want to do
2115 * this. Maybe it becomes part of the power saving plan.
2118 if (speed != DWC3_DSTS_SUPERSPEED)
2122 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2123 * each time on Connect Done.
2128 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2129 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2130 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2133 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2135 struct dwc3_ep *dep;
2140 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2141 speed = reg & DWC3_DSTS_CONNECTSPD;
2144 dwc3_update_ram_clk_sel(dwc, speed);
2147 case DWC3_DCFG_SUPERSPEED:
2149 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2150 * would cause a missing USB3 Reset event.
2152 * In such situations, we should force a USB3 Reset
2153 * event by calling our dwc3_gadget_reset_interrupt()
2158 * STAR#9000483510: RTL: SS : USB3 reset event may
2159 * not be generated always when the link enters poll
2161 if (dwc->revision < DWC3_REVISION_190A)
2162 dwc3_gadget_reset_interrupt(dwc);
2164 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2165 dwc->gadget.ep0->maxpacket = 512;
2166 dwc->gadget.speed = USB_SPEED_SUPER;
2168 case DWC3_DCFG_HIGHSPEED:
2169 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2170 dwc->gadget.ep0->maxpacket = 64;
2171 dwc->gadget.speed = USB_SPEED_HIGH;
2173 case DWC3_DCFG_FULLSPEED2:
2174 case DWC3_DCFG_FULLSPEED1:
2175 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2176 dwc->gadget.ep0->maxpacket = 64;
2177 dwc->gadget.speed = USB_SPEED_FULL;
2179 case DWC3_DCFG_LOWSPEED:
2180 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2181 dwc->gadget.ep0->maxpacket = 8;
2182 dwc->gadget.speed = USB_SPEED_LOW;
2186 /* Enable USB2 LPM Capability */
2188 if ((dwc->revision > DWC3_REVISION_194A)
2189 && (speed != DWC3_DCFG_SUPERSPEED)) {
2190 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2191 reg |= DWC3_DCFG_LPM_CAP;
2192 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2194 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2195 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2197 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2200 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2201 * DCFG.LPMCap is set, core responses with an ACK and the
2202 * BESL value in the LPM token is less than or equal to LPM
2205 if (dwc->revision < DWC3_REVISION_240A && dwc->has_lpm_erratum)
2206 WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2208 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2209 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2211 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2213 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2214 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2215 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2219 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2222 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2227 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2230 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2235 * Configure PHY via GUSB3PIPECTLn if required.
2237 * Update GTXFIFOSIZn
2239 * In both cases reset values should be sufficient.
2243 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2246 * TODO take core out of low power mode when that's
2250 dwc->gadget_driver->resume(&dwc->gadget);
2253 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2254 unsigned int evtinfo)
2256 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2257 unsigned int pwropt;
2260 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2261 * Hibernation mode enabled which would show up when device detects
2262 * host-initiated U3 exit.
2264 * In that case, device will generate a Link State Change Interrupt
2265 * from U3 to RESUME which is only necessary if Hibernation is
2268 * There are no functional changes due to such spurious event and we
2269 * just need to ignore it.
2273 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2276 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2277 if ((dwc->revision < DWC3_REVISION_250A) &&
2278 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2279 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2280 (next == DWC3_LINK_STATE_RESUME)) {
2281 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2287 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2288 * on the link partner, the USB session might do multiple entry/exit
2289 * of low power states before a transfer takes place.
2291 * Due to this problem, we might experience lower throughput. The
2292 * suggested workaround is to disable DCTL[12:9] bits if we're
2293 * transitioning from U1/U2 to U0 and enable those bits again
2294 * after a transfer completes and there are no pending transfers
2295 * on any of the enabled endpoints.
2297 * This is the first half of that workaround.
2301 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2302 * core send LGO_Ux entering U0
2304 if (dwc->revision < DWC3_REVISION_183A) {
2305 if (next == DWC3_LINK_STATE_U0) {
2309 switch (dwc->link_state) {
2310 case DWC3_LINK_STATE_U1:
2311 case DWC3_LINK_STATE_U2:
2312 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2313 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2314 | DWC3_DCTL_ACCEPTU2ENA
2315 | DWC3_DCTL_INITU1ENA
2316 | DWC3_DCTL_ACCEPTU1ENA);
2319 dwc->u1u2 = reg & u1u2;
2323 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2333 case DWC3_LINK_STATE_U1:
2334 if (dwc->speed == USB_SPEED_SUPER)
2335 dwc3_suspend_gadget(dwc);
2337 case DWC3_LINK_STATE_U2:
2338 case DWC3_LINK_STATE_U3:
2339 dwc3_suspend_gadget(dwc);
2341 case DWC3_LINK_STATE_RESUME:
2342 dwc3_resume_gadget(dwc);
2349 dwc->link_state = next;
2352 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2353 unsigned int evtinfo)
2355 unsigned int is_ss = evtinfo & (1UL << 4);
2358 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2359 * have a known issue which can cause USB CV TD.9.23 to fail
2362 * Because of this issue, core could generate bogus hibernation
2363 * events which SW needs to ignore.
2367 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2368 * Device Fallback from SuperSpeed
2370 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2373 /* enter hibernation here */
2376 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2377 const struct dwc3_event_devt *event)
2379 switch (event->type) {
2380 case DWC3_DEVICE_EVENT_DISCONNECT:
2381 dwc3_gadget_disconnect_interrupt(dwc);
2383 case DWC3_DEVICE_EVENT_RESET:
2384 dwc3_gadget_reset_interrupt(dwc);
2386 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2387 dwc3_gadget_conndone_interrupt(dwc);
2389 case DWC3_DEVICE_EVENT_WAKEUP:
2390 dwc3_gadget_wakeup_interrupt(dwc);
2392 case DWC3_DEVICE_EVENT_HIBER_REQ:
2393 if (!dwc->has_hibernation) {
2394 WARN(1 ,"unexpected hibernation event\n");
2397 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2399 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2400 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2402 case DWC3_DEVICE_EVENT_EOPF:
2403 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2405 case DWC3_DEVICE_EVENT_SOF:
2406 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2408 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2409 dev_vdbg(dwc->dev, "Erratic Error\n");
2411 case DWC3_DEVICE_EVENT_CMD_CMPL:
2412 dev_vdbg(dwc->dev, "Command Complete\n");
2414 case DWC3_DEVICE_EVENT_OVERFLOW:
2415 dev_vdbg(dwc->dev, "Overflow\n");
2418 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2422 static void dwc3_process_event_entry(struct dwc3 *dwc,
2423 const union dwc3_event *event)
2425 /* Endpoint IRQ, handle it and return early */
2426 if (event->type.is_devspec == 0) {
2428 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2431 switch (event->type.type) {
2432 case DWC3_EVENT_TYPE_DEV:
2433 dwc3_gadget_interrupt(dwc, &event->devt);
2435 /* REVISIT what to do with Carkit and I2C events ? */
2437 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2441 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2443 struct dwc3_event_buffer *evt;
2444 irqreturn_t ret = IRQ_NONE;
2448 evt = dwc->ev_buffs[buf];
2451 if (!(evt->flags & DWC3_EVENT_PENDING))
2455 union dwc3_event event;
2457 event.raw = *(u32 *) (evt->buf + evt->lpos);
2459 dwc3_process_event_entry(dwc, &event);
2462 * FIXME we wrap around correctly to the next entry as
2463 * almost all entries are 4 bytes in size. There is one
2464 * entry which has 12 bytes which is a regular entry
2465 * followed by 8 bytes data. ATM I don't know how
2466 * things are organized if we get next to the a
2467 * boundary so I worry about that once we try to handle
2470 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2473 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2477 evt->flags &= ~DWC3_EVENT_PENDING;
2480 /* Unmask interrupt */
2481 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2482 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2483 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2488 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2490 struct dwc3 *dwc = _dwc;
2491 unsigned long flags;
2492 irqreturn_t ret = IRQ_NONE;
2495 spin_lock_irqsave(&dwc->lock, flags);
2497 for (i = 0; i < dwc->num_event_buffers; i++)
2498 ret |= dwc3_process_event_buf(dwc, i);
2500 spin_unlock_irqrestore(&dwc->lock, flags);
2505 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2507 struct dwc3_event_buffer *evt;
2511 evt = dwc->ev_buffs[buf];
2513 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2514 count &= DWC3_GEVNTCOUNT_MASK;
2519 evt->flags |= DWC3_EVENT_PENDING;
2521 /* Mask interrupt */
2522 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2523 reg |= DWC3_GEVNTSIZ_INTMASK;
2524 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2526 return IRQ_WAKE_THREAD;
2529 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2531 struct dwc3 *dwc = _dwc;
2533 irqreturn_t ret = IRQ_NONE;
2535 spin_lock(&dwc->lock);
2537 for (i = 0; i < dwc->num_event_buffers; i++) {
2540 status = dwc3_check_event_buf(dwc, i);
2541 if (status == IRQ_WAKE_THREAD)
2545 spin_unlock(&dwc->lock);
2551 * dwc3_gadget_init - Initializes gadget related registers
2552 * @dwc: pointer to our controller context structure
2554 * Returns 0 on success otherwise negative errno.
2556 int dwc3_gadget_init(struct dwc3 *dwc)
2560 dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req),
2561 (unsigned long *)&dwc->ctrl_req_addr);
2562 if (!dwc->ctrl_req) {
2563 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2568 dwc->ep0_trb = dma_alloc_coherent(sizeof(*dwc->ep0_trb) * 2,
2569 (unsigned long *)&dwc->ep0_trb_addr);
2570 if (!dwc->ep0_trb) {
2571 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2576 dwc->setup_buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
2577 DWC3_EP0_BOUNCE_SIZE);
2578 if (!dwc->setup_buf) {
2583 dwc->ep0_bounce = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE,
2584 (unsigned long *)&dwc->ep0_bounce_addr);
2585 if (!dwc->ep0_bounce) {
2586 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2591 dwc->gadget.ops = &dwc3_gadget_ops;
2592 dwc->gadget.max_speed = USB_SPEED_SUPER;
2593 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2594 dwc->gadget.name = "dwc3-gadget";
2597 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2600 dwc->gadget.quirk_ep_out_aligned_size = true;
2603 * REVISIT: Here we should clear all pending IRQs to be
2604 * sure we're starting from a well known location.
2607 ret = dwc3_gadget_init_endpoints(dwc);
2611 ret = usb_add_gadget_udc((struct device *)dwc->dev, &dwc->gadget);
2613 dev_err(dwc->dev, "failed to register udc\n");
2620 dwc3_gadget_free_endpoints(dwc);
2621 dma_free_coherent(dwc->ep0_bounce);
2624 kfree(dwc->setup_buf);
2627 dma_free_coherent(dwc->ep0_trb);
2630 dma_free_coherent(dwc->ctrl_req);
2636 /* -------------------------------------------------------------------------- */
2638 void dwc3_gadget_exit(struct dwc3 *dwc)
2640 usb_del_gadget_udc(&dwc->gadget);
2642 dwc3_gadget_free_endpoints(dwc);
2644 dma_free_coherent(dwc->ep0_bounce);
2646 kfree(dwc->setup_buf);
2648 dma_free_coherent(dwc->ep0_trb);
2650 dma_free_coherent(dwc->ctrl_req);
2654 * dwc3_gadget_uboot_handle_interrupt - handle dwc3 gadget interrupt
2655 * @dwc: struct dwce *
2657 * Handles ep0 and gadget interrupt
2659 * Should be called from dwc3 core.
2661 void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
2663 int ret = dwc3_interrupt(0, dwc);
2665 if (ret == IRQ_WAKE_THREAD) {
2667 struct dwc3_event_buffer *evt;
2669 dwc3_thread_interrupt(0, dwc);
2671 /* Clean + Invalidate the buffers after touching them */
2672 for (i = 0; i < dwc->num_event_buffers; i++) {
2673 evt = dwc->ev_buffs[i];
2674 dwc3_flush_cache((uintptr_t)evt->buf, evt->length);