1 // SPDX-License-Identifier: GPL-2.0
3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/ep0.c) and ported
13 * commit c00552ebaf : Merge 3.18-rc7 into usb-next
16 #include <linux/kernel.h>
17 #include <linux/list.h>
19 #include <linux/usb/ch9.h>
20 #include <linux/usb/gadget.h>
21 #include <linux/usb/composite.h>
27 #include "linux-compat.h"
29 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
30 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
31 struct dwc3_ep *dep, struct dwc3_request *req);
33 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
42 case EP0_STATUS_PHASE:
43 return "Status Phase";
49 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
50 u32 len, u32 type, unsigned chain)
52 struct dwc3_gadget_ep_cmd_params params;
58 dep = dwc->eps[epnum];
59 if (dep->flags & DWC3_EP_BUSY) {
60 dev_vdbg(dwc->dev, "%s still busy", dep->name);
64 trb = &dwc->ep0_trb[dep->free_slot];
69 trb->bpl = lower_32_bits(buf_dma);
70 trb->bph = upper_32_bits(buf_dma);
74 trb->ctrl |= (DWC3_TRB_CTRL_HWO
75 | DWC3_TRB_CTRL_ISP_IMI);
78 trb->ctrl |= DWC3_TRB_CTRL_CHN;
80 trb->ctrl |= (DWC3_TRB_CTRL_IOC
83 dwc3_flush_cache((uintptr_t)buf_dma, len);
84 dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
89 memset(¶ms, 0, sizeof(params));
90 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
91 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
93 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
94 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
96 dev_dbg(dwc->dev, "%s STARTTRANSFER failed", dep->name);
100 dep->flags |= DWC3_EP_BUSY;
101 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
104 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
109 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
110 struct dwc3_request *req)
112 struct dwc3 *dwc = dep->dwc;
114 req->request.actual = 0;
115 req->request.status = -EINPROGRESS;
116 req->epnum = dep->number;
118 list_add_tail(&req->list, &dep->request_list);
121 * Gadget driver might not be quick enough to queue a request
122 * before we get a Transfer Not Ready event on this endpoint.
124 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
125 * flag is set, it's telling us that as soon as Gadget queues the
126 * required request, we should kick the transfer here because the
127 * IRQ we were waiting for is long gone.
129 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
132 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
134 if (dwc->ep0state != EP0_DATA_PHASE) {
135 dev_WARN(dwc->dev, "Unexpected pending request\n");
139 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
141 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
148 * In case gadget driver asked us to delay the STATUS phase,
151 if (dwc->delayed_status) {
154 direction = !dwc->ep0_expect_in;
155 dwc->delayed_status = false;
156 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
158 if (dwc->ep0state == EP0_STATUS_PHASE)
159 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
161 dev_dbg(dwc->dev, "too early for delayed status");
167 * Unfortunately we have uncovered a limitation wrt the Data Phase.
169 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
170 * come before issueing Start Transfer command, but if we do, we will
171 * miss situations where the host starts another SETUP phase instead of
172 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
173 * Layer Compliance Suite.
175 * The problem surfaces due to the fact that in case of back-to-back
176 * SETUP packets there will be no XferNotReady(DATA) generated and we
177 * will be stuck waiting for XferNotReady(DATA) forever.
179 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
180 * it tells us to start Data Phase right away. It also mentions that if
181 * we receive a SETUP phase instead of the DATA phase, core will issue
182 * XferComplete for the DATA phase, before actually initiating it in
183 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
184 * can only be used to print some debugging logs, as the core expects
185 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
186 * just so it completes right away, without transferring anything and,
187 * only then, we can go back to the SETUP phase.
189 * Because of this scenario, SNPS decided to change the programming
190 * model of control transfers and support on-demand transfers only for
191 * the STATUS phase. To fix the issue we have now, we will always wait
192 * for gadget driver to queue the DATA phase's struct usb_request, then
193 * start it right away.
195 * If we're actually in a 2-stage transfer, we will wait for
196 * XferNotReady(STATUS).
198 if (dwc->three_stage_setup) {
201 direction = dwc->ep0_expect_in;
202 dwc->ep0state = EP0_DATA_PHASE;
204 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
206 dep->flags &= ~DWC3_EP0_DIR_IN;
212 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
215 struct dwc3_request *req = to_dwc3_request(request);
216 struct dwc3_ep *dep = to_dwc3_ep(ep);
217 struct dwc3 *dwc = dep->dwc;
223 spin_lock_irqsave(&dwc->lock, flags);
224 if (!dep->endpoint.desc) {
225 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s",
231 /* we share one TRB for ep0/1 */
232 if (!list_empty(&dep->request_list)) {
237 dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s'",
238 request, dep->name, request->length,
239 dwc3_ep0_state_string(dwc->ep0state));
241 ret = __dwc3_gadget_ep0_queue(dep, req);
244 spin_unlock_irqrestore(&dwc->lock, flags);
249 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
253 /* reinitialize physical ep1 */
255 dep->flags = DWC3_EP_ENABLED;
257 /* stall is always issued on EP0 */
259 __dwc3_gadget_ep_set_halt(dep, 1, false);
260 dep->flags = DWC3_EP_ENABLED;
261 dwc->delayed_status = false;
263 if (!list_empty(&dep->request_list)) {
264 struct dwc3_request *req;
266 req = next_request(&dep->request_list);
267 dwc3_gadget_giveback(dep, req, -ECONNRESET);
270 dwc->ep0state = EP0_SETUP_PHASE;
271 dwc3_ep0_out_start(dwc);
274 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
276 struct dwc3_ep *dep = to_dwc3_ep(ep);
277 struct dwc3 *dwc = dep->dwc;
279 dwc3_ep0_stall_and_restart(dwc);
284 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
289 spin_lock_irqsave(&dwc->lock, flags);
290 ret = __dwc3_gadget_ep0_set_halt(ep, value);
291 spin_unlock_irqrestore(&dwc->lock, flags);
296 void dwc3_ep0_out_start(struct dwc3 *dwc)
300 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
301 DWC3_TRBCTL_CONTROL_SETUP, 0);
305 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
308 u32 windex = le16_to_cpu(wIndex_le);
311 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
312 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
315 dep = dwc->eps[epnum];
316 if (dep->flags & DWC3_EP_ENABLED)
322 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
328 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
329 struct usb_ctrlrequest *ctrl)
335 __le16 *response_pkt;
337 recip = ctrl->bRequestType & USB_RECIP_MASK;
339 case USB_RECIP_DEVICE:
341 * LTM will be set once we know how to set this in HW.
343 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
345 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
346 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
347 if (reg & DWC3_DCTL_INITU1ENA)
348 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
349 if (reg & DWC3_DCTL_INITU2ENA)
350 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
355 case USB_RECIP_INTERFACE:
357 * Function Remote Wake Capable D0
358 * Function Remote Wakeup D1
362 case USB_RECIP_ENDPOINT:
363 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
367 if (dep->flags & DWC3_EP_STALL)
368 usb_status = 1 << USB_ENDPOINT_HALT;
374 response_pkt = (__le16 *) dwc->setup_buf;
375 *response_pkt = cpu_to_le16(usb_status);
378 dwc->ep0_usb_req.dep = dep;
379 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
380 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
381 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
383 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
386 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
387 struct usb_ctrlrequest *ctrl, int set)
395 enum usb_device_state state;
397 wValue = le16_to_cpu(ctrl->wValue);
398 wIndex = le16_to_cpu(ctrl->wIndex);
399 recip = ctrl->bRequestType & USB_RECIP_MASK;
400 state = dwc->gadget.state;
403 case USB_RECIP_DEVICE:
406 case USB_DEVICE_REMOTE_WAKEUP:
409 * 9.4.1 says only only for SS, in AddressState only for
410 * default control pipe
412 case USB_DEVICE_U1_ENABLE:
413 if (state != USB_STATE_CONFIGURED)
415 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
418 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
420 reg |= DWC3_DCTL_INITU1ENA;
422 reg &= ~DWC3_DCTL_INITU1ENA;
423 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
426 case USB_DEVICE_U2_ENABLE:
427 if (state != USB_STATE_CONFIGURED)
429 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
432 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
434 reg |= DWC3_DCTL_INITU2ENA;
436 reg &= ~DWC3_DCTL_INITU2ENA;
437 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
440 case USB_DEVICE_LTM_ENABLE:
443 case USB_DEVICE_TEST_MODE:
444 if ((wIndex & 0xff) != 0)
449 dwc->test_mode_nr = wIndex >> 8;
450 dwc->test_mode = true;
457 case USB_RECIP_INTERFACE:
459 case USB_INTRF_FUNC_SUSPEND:
460 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
461 /* XXX enable Low power suspend */
463 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
464 /* XXX enable remote wakeup */
472 case USB_RECIP_ENDPOINT:
474 case USB_ENDPOINT_HALT:
475 dep = dwc3_wIndex_to_dep(dwc, wIndex);
478 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
480 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
496 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
498 enum usb_device_state state = dwc->gadget.state;
502 addr = le16_to_cpu(ctrl->wValue);
504 dev_dbg(dwc->dev, "invalid device address %d", addr);
508 if (state == USB_STATE_CONFIGURED) {
509 dev_dbg(dwc->dev, "trying to set address when configured");
513 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
514 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
515 reg |= DWC3_DCFG_DEVADDR(addr);
516 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
519 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
521 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
526 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
530 spin_unlock(&dwc->lock);
531 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
532 spin_lock(&dwc->lock);
536 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
538 enum usb_device_state state = dwc->gadget.state;
543 dwc->start_config_issued = false;
544 cfg = le16_to_cpu(ctrl->wValue);
547 case USB_STATE_DEFAULT:
550 case USB_STATE_ADDRESS:
551 ret = dwc3_ep0_delegate_req(dwc, ctrl);
552 /* if the cfg matches and the cfg is non zero */
553 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
556 * only change state if set_config has already
557 * been processed. If gadget driver returns
558 * USB_GADGET_DELAYED_STATUS, we will wait
559 * to change the state on the next usb_ep_queue()
562 usb_gadget_set_state(&dwc->gadget,
563 USB_STATE_CONFIGURED);
566 * Enable transition to U1/U2 state when
567 * nothing is pending from application.
569 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
570 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
571 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
573 dwc->resize_fifos = true;
574 dev_dbg(dwc->dev, "resize FIFOs flag SET");
578 case USB_STATE_CONFIGURED:
579 ret = dwc3_ep0_delegate_req(dwc, ctrl);
581 usb_gadget_set_state(&dwc->gadget,
590 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
592 struct dwc3_ep *dep = to_dwc3_ep(ep);
593 struct dwc3 *dwc = dep->dwc;
607 memcpy(&timing, req->buf, sizeof(timing));
609 dwc->u1sel = timing.u1sel;
610 dwc->u1pel = timing.u1pel;
611 dwc->u2sel = le16_to_cpu(timing.u2sel);
612 dwc->u2pel = le16_to_cpu(timing.u2pel);
614 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
615 if (reg & DWC3_DCTL_INITU2ENA)
617 if (reg & DWC3_DCTL_INITU1ENA)
621 * According to Synopsys Databook, if parameter is
622 * greater than 125, a value of zero should be
623 * programmed in the register.
628 /* now that we have the time, issue DGCMD Set Sel */
629 ret = dwc3_send_gadget_generic_command(dwc,
630 DWC3_DGCMD_SET_PERIODIC_PAR, param);
634 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
637 enum usb_device_state state = dwc->gadget.state;
640 if (state == USB_STATE_DEFAULT)
643 wLength = le16_to_cpu(ctrl->wLength);
646 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
652 * To handle Set SEL we need to receive 6 bytes from Host. So let's
653 * queue a usb_request for 6 bytes.
655 * Remember, though, this controller can't handle non-wMaxPacketSize
656 * aligned transfers on the OUT direction, so we queue a request for
657 * wMaxPacketSize instead.
660 dwc->ep0_usb_req.dep = dep;
661 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
662 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
663 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
665 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
668 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
674 wValue = le16_to_cpu(ctrl->wValue);
675 wLength = le16_to_cpu(ctrl->wLength);
676 wIndex = le16_to_cpu(ctrl->wIndex);
678 if (wIndex || wLength)
682 * REVISIT It's unclear from Databook what to do with this
683 * value. For now, just cache it.
685 dwc->isoch_delay = wValue;
690 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
694 switch (ctrl->bRequest) {
695 case USB_REQ_GET_STATUS:
696 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS");
697 ret = dwc3_ep0_handle_status(dwc, ctrl);
699 case USB_REQ_CLEAR_FEATURE:
700 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE");
701 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
703 case USB_REQ_SET_FEATURE:
704 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE");
705 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
707 case USB_REQ_SET_ADDRESS:
708 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS");
709 ret = dwc3_ep0_set_address(dwc, ctrl);
711 case USB_REQ_SET_CONFIGURATION:
712 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION");
713 ret = dwc3_ep0_set_config(dwc, ctrl);
715 case USB_REQ_SET_SEL:
716 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL");
717 ret = dwc3_ep0_set_sel(dwc, ctrl);
719 case USB_REQ_SET_ISOCH_DELAY:
720 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY");
721 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
724 dev_vdbg(dwc->dev, "Forwarding to gadget driver");
725 ret = dwc3_ep0_delegate_req(dwc, ctrl);
732 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
733 const struct dwc3_event_depevt *event)
735 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
739 if (!dwc->gadget_driver)
742 len = le16_to_cpu(ctrl->wLength);
744 dwc->three_stage_setup = false;
745 dwc->ep0_expect_in = false;
746 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
748 dwc->three_stage_setup = true;
749 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
750 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
753 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
754 ret = dwc3_ep0_std_request(dwc, ctrl);
756 ret = dwc3_ep0_delegate_req(dwc, ctrl);
758 if (ret == USB_GADGET_DELAYED_STATUS)
759 dwc->delayed_status = true;
763 dwc3_ep0_stall_and_restart(dwc);
766 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
767 const struct dwc3_event_depevt *event)
769 struct dwc3_request *r = NULL;
770 struct usb_request *ur;
771 struct dwc3_trb *trb;
773 unsigned transfer_size = 0;
781 epnum = event->endpoint_number;
784 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
788 r = next_request(&ep0->request_list);
792 dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
794 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
795 if (status == DWC3_TRBSTS_SETUP_PENDING) {
796 dev_dbg(dwc->dev, "Setup Pending received");
799 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
807 length = trb->size & DWC3_TRB_SIZE_MASK;
809 maxp = ep0->endpoint.maxpacket;
811 if (dwc->ep0_bounced) {
813 * Handle the first TRB before handling the bounce buffer if
814 * the request length is greater than the bounce buffer size.
816 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
817 transfer_size = (ur->length / maxp) * maxp;
818 transferred = transfer_size - length;
819 buf = (u8 *)buf + transferred;
820 ur->actual += transferred;
823 dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
824 length = trb->size & DWC3_TRB_SIZE_MASK;
829 transfer_size = roundup((ur->length - transfer_size),
831 transferred = min_t(u32, ur->length - transferred,
832 transfer_size - length);
833 dwc3_flush_cache((uintptr_t)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
834 memcpy(buf, dwc->ep0_bounce, transferred);
836 transferred = ur->length - length;
839 ur->actual += transferred;
841 if ((epnum & 1) && ur->actual < ur->length) {
842 /* for some reason we did not get everything out */
844 dwc3_ep0_stall_and_restart(dwc);
846 dwc3_gadget_giveback(ep0, r, 0);
848 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
849 ur->length && ur->zero) {
852 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
854 ret = dwc3_ep0_start_trans(dwc, epnum,
855 dwc->ctrl_req_addr, 0,
856 DWC3_TRBCTL_CONTROL_DATA, 0);
862 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
863 const struct dwc3_event_depevt *event)
865 struct dwc3_request *r;
867 struct dwc3_trb *trb;
873 if (!list_empty(&dep->request_list)) {
874 r = next_request(&dep->request_list);
876 dwc3_gadget_giveback(dep, r, 0);
879 if (dwc->test_mode) {
882 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
884 dev_dbg(dwc->dev, "Invalid Test #%d",
886 dwc3_ep0_stall_and_restart(dwc);
891 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
892 if (status == DWC3_TRBSTS_SETUP_PENDING)
893 dev_dbg(dwc->dev, "Setup Pending received");
895 dwc->ep0state = EP0_SETUP_PHASE;
896 dwc3_ep0_out_start(dwc);
899 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
900 const struct dwc3_event_depevt *event)
902 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
904 dep->flags &= ~DWC3_EP_BUSY;
905 dep->resource_index = 0;
906 dwc->setup_packet_pending = false;
908 switch (dwc->ep0state) {
909 case EP0_SETUP_PHASE:
910 dev_vdbg(dwc->dev, "Setup Phase");
911 dwc3_ep0_inspect_setup(dwc, event);
915 dev_vdbg(dwc->dev, "Data Phase");
916 dwc3_ep0_complete_data(dwc, event);
919 case EP0_STATUS_PHASE:
920 dev_vdbg(dwc->dev, "Status Phase");
921 dwc3_ep0_complete_status(dwc, event);
924 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
928 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
929 struct dwc3_ep *dep, struct dwc3_request *req)
933 req->direction = !!dep->number;
935 if (req->request.length == 0) {
936 ret = dwc3_ep0_start_trans(dwc, dep->number,
937 dwc->ctrl_req_addr, 0,
938 DWC3_TRBCTL_CONTROL_DATA, 0);
939 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
940 (dep->number == 0)) {
941 u32 transfer_size = 0;
944 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
947 dev_dbg(dwc->dev, "failed to map request\n");
951 maxpacket = dep->endpoint.maxpacket;
952 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
953 transfer_size = (req->request.length / maxpacket) *
955 ret = dwc3_ep0_start_trans(dwc, dep->number,
958 DWC3_TRBCTL_CONTROL_DATA, 1);
961 transfer_size = roundup((req->request.length - transfer_size),
964 dwc->ep0_bounced = true;
967 * REVISIT in case request length is bigger than
968 * DWC3_EP0_BOUNCE_SIZE we will need two chained
969 * TRBs to handle the transfer.
971 ret = dwc3_ep0_start_trans(dwc, dep->number,
972 dwc->ep0_bounce_addr, transfer_size,
973 DWC3_TRBCTL_CONTROL_DATA, 0);
975 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
978 dev_dbg(dwc->dev, "failed to map request\n");
982 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
984 DWC3_TRBCTL_CONTROL_DATA, 0);
990 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
992 struct dwc3 *dwc = dep->dwc;
995 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
996 : DWC3_TRBCTL_CONTROL_STATUS2;
998 return dwc3_ep0_start_trans(dwc, dep->number,
999 dwc->ctrl_req_addr, 0, type, 0);
1002 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1004 if (dwc->resize_fifos) {
1005 dev_dbg(dwc->dev, "Resizing FIFOs");
1006 dwc3_gadget_resize_tx_fifos(dwc);
1007 dwc->resize_fifos = 0;
1010 WARN_ON(dwc3_ep0_start_control_status(dep));
1013 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1014 const struct dwc3_event_depevt *event)
1016 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1018 __dwc3_ep0_do_control_status(dwc, dep);
1021 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1023 struct dwc3_gadget_ep_cmd_params params;
1027 if (!dep->resource_index)
1030 cmd = DWC3_DEPCMD_ENDTRANSFER;
1031 cmd |= DWC3_DEPCMD_CMDIOC;
1032 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1033 memset(¶ms, 0, sizeof(params));
1034 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1036 dep->resource_index = 0;
1039 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1040 const struct dwc3_event_depevt *event)
1042 dwc->setup_packet_pending = true;
1044 switch (event->status) {
1045 case DEPEVT_STATUS_CONTROL_DATA:
1046 dev_vdbg(dwc->dev, "Control Data");
1049 * We already have a DATA transfer in the controller's cache,
1050 * if we receive a XferNotReady(DATA) we will ignore it, unless
1051 * it's for the wrong direction.
1053 * In that case, we must issue END_TRANSFER command to the Data
1054 * Phase we already have started and issue SetStall on the
1057 if (dwc->ep0_expect_in != event->endpoint_number) {
1058 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1060 dev_vdbg(dwc->dev, "Wrong direction for Data phase");
1061 dwc3_ep0_end_control_data(dwc, dep);
1062 dwc3_ep0_stall_and_restart(dwc);
1068 case DEPEVT_STATUS_CONTROL_STATUS:
1069 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1072 dev_vdbg(dwc->dev, "Control Status");
1074 dwc->ep0state = EP0_STATUS_PHASE;
1076 if (dwc->delayed_status) {
1077 WARN_ON_ONCE(event->endpoint_number != 1);
1078 dev_vdbg(dwc->dev, "Delayed Status");
1082 dwc3_ep0_do_control_status(dwc, event);
1086 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1087 const struct dwc3_event_depevt *event)
1089 u8 epnum = event->endpoint_number;
1091 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'",
1092 dwc3_ep_event_string(event->endpoint_event),
1093 epnum >> 1, (epnum & 1) ? "in" : "out",
1094 dwc3_ep0_state_string(dwc->ep0state));
1096 switch (event->endpoint_event) {
1097 case DWC3_DEPEVT_XFERCOMPLETE:
1098 dwc3_ep0_xfer_complete(dwc, event);
1101 case DWC3_DEPEVT_XFERNOTREADY:
1102 dwc3_ep0_xfernotready(dwc, event);
1105 case DWC3_DEPEVT_XFERINPROGRESS:
1106 case DWC3_DEPEVT_RXTXFIFOEVT:
1107 case DWC3_DEPEVT_STREAMEVT:
1108 case DWC3_DEPEVT_EPCMDCMPLT: