2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/ep0.c) and ported
12 * commit c00552ebaf : Merge 3.18-rc7 into usb-next
14 * SPDX-License-Identifier: GPL-2.0
17 #include <linux/kernel.h>
18 #include <linux/list.h>
20 #include <linux/usb/ch9.h>
21 #include <linux/usb/gadget.h>
22 #include <linux/usb/composite.h>
28 #include "linux-compat.h"
30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 struct dwc3_ep *dep, struct dwc3_request *req);
34 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
43 case EP0_STATUS_PHASE:
44 return "Status Phase";
50 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
53 struct dwc3_gadget_ep_cmd_params params;
59 dep = dwc->eps[epnum];
60 if (dep->flags & DWC3_EP_BUSY) {
61 dev_vdbg(dwc->dev, "%s still busy", dep->name);
67 trb->bpl = lower_32_bits(buf_dma);
68 trb->bph = upper_32_bits(buf_dma);
72 trb->ctrl |= (DWC3_TRB_CTRL_HWO
75 | DWC3_TRB_CTRL_ISP_IMI);
77 dwc3_flush_cache((int)buf_dma, len);
78 dwc3_flush_cache((int)trb, sizeof(*trb));
80 memset(¶ms, 0, sizeof(params));
81 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
82 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
84 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
85 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
87 dev_dbg(dwc->dev, "%s STARTTRANSFER failed", dep->name);
91 dep->flags |= DWC3_EP_BUSY;
92 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
95 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
100 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
101 struct dwc3_request *req)
103 struct dwc3 *dwc = dep->dwc;
105 req->request.actual = 0;
106 req->request.status = -EINPROGRESS;
107 req->epnum = dep->number;
109 list_add_tail(&req->list, &dep->request_list);
112 * Gadget driver might not be quick enough to queue a request
113 * before we get a Transfer Not Ready event on this endpoint.
115 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
116 * flag is set, it's telling us that as soon as Gadget queues the
117 * required request, we should kick the transfer here because the
118 * IRQ we were waiting for is long gone.
120 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
123 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
125 if (dwc->ep0state != EP0_DATA_PHASE) {
126 dev_WARN(dwc->dev, "Unexpected pending request\n");
130 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
132 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
139 * In case gadget driver asked us to delay the STATUS phase,
142 if (dwc->delayed_status) {
145 direction = !dwc->ep0_expect_in;
146 dwc->delayed_status = false;
147 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
149 if (dwc->ep0state == EP0_STATUS_PHASE)
150 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
152 dev_dbg(dwc->dev, "too early for delayed status");
158 * Unfortunately we have uncovered a limitation wrt the Data Phase.
160 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
161 * come before issueing Start Transfer command, but if we do, we will
162 * miss situations where the host starts another SETUP phase instead of
163 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
164 * Layer Compliance Suite.
166 * The problem surfaces due to the fact that in case of back-to-back
167 * SETUP packets there will be no XferNotReady(DATA) generated and we
168 * will be stuck waiting for XferNotReady(DATA) forever.
170 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
171 * it tells us to start Data Phase right away. It also mentions that if
172 * we receive a SETUP phase instead of the DATA phase, core will issue
173 * XferComplete for the DATA phase, before actually initiating it in
174 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
175 * can only be used to print some debugging logs, as the core expects
176 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
177 * just so it completes right away, without transferring anything and,
178 * only then, we can go back to the SETUP phase.
180 * Because of this scenario, SNPS decided to change the programming
181 * model of control transfers and support on-demand transfers only for
182 * the STATUS phase. To fix the issue we have now, we will always wait
183 * for gadget driver to queue the DATA phase's struct usb_request, then
184 * start it right away.
186 * If we're actually in a 2-stage transfer, we will wait for
187 * XferNotReady(STATUS).
189 if (dwc->three_stage_setup) {
192 direction = dwc->ep0_expect_in;
193 dwc->ep0state = EP0_DATA_PHASE;
195 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
197 dep->flags &= ~DWC3_EP0_DIR_IN;
203 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
206 struct dwc3_request *req = to_dwc3_request(request);
207 struct dwc3_ep *dep = to_dwc3_ep(ep);
208 struct dwc3 *dwc = dep->dwc;
214 spin_lock_irqsave(&dwc->lock, flags);
215 if (!dep->endpoint.desc) {
216 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s",
222 /* we share one TRB for ep0/1 */
223 if (!list_empty(&dep->request_list)) {
228 dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s'",
229 request, dep->name, request->length,
230 dwc3_ep0_state_string(dwc->ep0state));
232 ret = __dwc3_gadget_ep0_queue(dep, req);
235 spin_unlock_irqrestore(&dwc->lock, flags);
240 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
244 /* reinitialize physical ep1 */
246 dep->flags = DWC3_EP_ENABLED;
248 /* stall is always issued on EP0 */
250 __dwc3_gadget_ep_set_halt(dep, 1, false);
251 dep->flags = DWC3_EP_ENABLED;
252 dwc->delayed_status = false;
254 if (!list_empty(&dep->request_list)) {
255 struct dwc3_request *req;
257 req = next_request(&dep->request_list);
258 dwc3_gadget_giveback(dep, req, -ECONNRESET);
261 dwc->ep0state = EP0_SETUP_PHASE;
262 dwc3_ep0_out_start(dwc);
265 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
267 struct dwc3_ep *dep = to_dwc3_ep(ep);
268 struct dwc3 *dwc = dep->dwc;
270 dwc3_ep0_stall_and_restart(dwc);
275 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
280 spin_lock_irqsave(&dwc->lock, flags);
281 ret = __dwc3_gadget_ep0_set_halt(ep, value);
282 spin_unlock_irqrestore(&dwc->lock, flags);
287 void dwc3_ep0_out_start(struct dwc3 *dwc)
291 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
292 DWC3_TRBCTL_CONTROL_SETUP);
296 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
299 u32 windex = le16_to_cpu(wIndex_le);
302 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
303 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
306 dep = dwc->eps[epnum];
307 if (dep->flags & DWC3_EP_ENABLED)
313 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
319 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
320 struct usb_ctrlrequest *ctrl)
326 __le16 *response_pkt;
328 recip = ctrl->bRequestType & USB_RECIP_MASK;
330 case USB_RECIP_DEVICE:
332 * LTM will be set once we know how to set this in HW.
334 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
336 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
337 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
338 if (reg & DWC3_DCTL_INITU1ENA)
339 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
340 if (reg & DWC3_DCTL_INITU2ENA)
341 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
346 case USB_RECIP_INTERFACE:
348 * Function Remote Wake Capable D0
349 * Function Remote Wakeup D1
353 case USB_RECIP_ENDPOINT:
354 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
358 if (dep->flags & DWC3_EP_STALL)
359 usb_status = 1 << USB_ENDPOINT_HALT;
365 response_pkt = (__le16 *) dwc->setup_buf;
366 *response_pkt = cpu_to_le16(usb_status);
369 dwc->ep0_usb_req.dep = dep;
370 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
371 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
372 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
374 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
377 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
378 struct usb_ctrlrequest *ctrl, int set)
386 enum usb_device_state state;
388 wValue = le16_to_cpu(ctrl->wValue);
389 wIndex = le16_to_cpu(ctrl->wIndex);
390 recip = ctrl->bRequestType & USB_RECIP_MASK;
391 state = dwc->gadget.state;
394 case USB_RECIP_DEVICE:
397 case USB_DEVICE_REMOTE_WAKEUP:
400 * 9.4.1 says only only for SS, in AddressState only for
401 * default control pipe
403 case USB_DEVICE_U1_ENABLE:
404 if (state != USB_STATE_CONFIGURED)
406 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
409 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
411 reg |= DWC3_DCTL_INITU1ENA;
413 reg &= ~DWC3_DCTL_INITU1ENA;
414 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
417 case USB_DEVICE_U2_ENABLE:
418 if (state != USB_STATE_CONFIGURED)
420 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
423 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
425 reg |= DWC3_DCTL_INITU2ENA;
427 reg &= ~DWC3_DCTL_INITU2ENA;
428 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
431 case USB_DEVICE_LTM_ENABLE:
434 case USB_DEVICE_TEST_MODE:
435 if ((wIndex & 0xff) != 0)
440 dwc->test_mode_nr = wIndex >> 8;
441 dwc->test_mode = true;
448 case USB_RECIP_INTERFACE:
450 case USB_INTRF_FUNC_SUSPEND:
451 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
452 /* XXX enable Low power suspend */
454 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
455 /* XXX enable remote wakeup */
463 case USB_RECIP_ENDPOINT:
465 case USB_ENDPOINT_HALT:
466 dep = dwc3_wIndex_to_dep(dwc, wIndex);
469 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
471 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
487 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
489 enum usb_device_state state = dwc->gadget.state;
493 addr = le16_to_cpu(ctrl->wValue);
495 dev_dbg(dwc->dev, "invalid device address %d", addr);
499 if (state == USB_STATE_CONFIGURED) {
500 dev_dbg(dwc->dev, "trying to set address when configured");
504 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
505 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
506 reg |= DWC3_DCFG_DEVADDR(addr);
507 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
510 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
512 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
517 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
521 spin_unlock(&dwc->lock);
522 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
523 spin_lock(&dwc->lock);
527 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
529 enum usb_device_state state = dwc->gadget.state;
534 dwc->start_config_issued = false;
535 cfg = le16_to_cpu(ctrl->wValue);
538 case USB_STATE_DEFAULT:
541 case USB_STATE_ADDRESS:
542 ret = dwc3_ep0_delegate_req(dwc, ctrl);
543 /* if the cfg matches and the cfg is non zero */
544 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
547 * only change state if set_config has already
548 * been processed. If gadget driver returns
549 * USB_GADGET_DELAYED_STATUS, we will wait
550 * to change the state on the next usb_ep_queue()
553 usb_gadget_set_state(&dwc->gadget,
554 USB_STATE_CONFIGURED);
557 * Enable transition to U1/U2 state when
558 * nothing is pending from application.
560 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
561 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
562 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
564 dwc->resize_fifos = true;
565 dev_dbg(dwc->dev, "resize FIFOs flag SET");
569 case USB_STATE_CONFIGURED:
570 ret = dwc3_ep0_delegate_req(dwc, ctrl);
572 usb_gadget_set_state(&dwc->gadget,
581 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
583 struct dwc3_ep *dep = to_dwc3_ep(ep);
584 struct dwc3 *dwc = dep->dwc;
598 memcpy(&timing, req->buf, sizeof(timing));
600 dwc->u1sel = timing.u1sel;
601 dwc->u1pel = timing.u1pel;
602 dwc->u2sel = le16_to_cpu(timing.u2sel);
603 dwc->u2pel = le16_to_cpu(timing.u2pel);
605 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
606 if (reg & DWC3_DCTL_INITU2ENA)
608 if (reg & DWC3_DCTL_INITU1ENA)
612 * According to Synopsys Databook, if parameter is
613 * greater than 125, a value of zero should be
614 * programmed in the register.
619 /* now that we have the time, issue DGCMD Set Sel */
620 ret = dwc3_send_gadget_generic_command(dwc,
621 DWC3_DGCMD_SET_PERIODIC_PAR, param);
625 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
628 enum usb_device_state state = dwc->gadget.state;
631 if (state == USB_STATE_DEFAULT)
634 wLength = le16_to_cpu(ctrl->wLength);
637 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
643 * To handle Set SEL we need to receive 6 bytes from Host. So let's
644 * queue a usb_request for 6 bytes.
646 * Remember, though, this controller can't handle non-wMaxPacketSize
647 * aligned transfers on the OUT direction, so we queue a request for
648 * wMaxPacketSize instead.
651 dwc->ep0_usb_req.dep = dep;
652 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
653 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
654 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
656 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
659 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
665 wValue = le16_to_cpu(ctrl->wValue);
666 wLength = le16_to_cpu(ctrl->wLength);
667 wIndex = le16_to_cpu(ctrl->wIndex);
669 if (wIndex || wLength)
673 * REVISIT It's unclear from Databook what to do with this
674 * value. For now, just cache it.
676 dwc->isoch_delay = wValue;
681 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
685 switch (ctrl->bRequest) {
686 case USB_REQ_GET_STATUS:
687 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS");
688 ret = dwc3_ep0_handle_status(dwc, ctrl);
690 case USB_REQ_CLEAR_FEATURE:
691 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE");
692 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
694 case USB_REQ_SET_FEATURE:
695 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE");
696 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
698 case USB_REQ_SET_ADDRESS:
699 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS");
700 ret = dwc3_ep0_set_address(dwc, ctrl);
702 case USB_REQ_SET_CONFIGURATION:
703 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION");
704 ret = dwc3_ep0_set_config(dwc, ctrl);
706 case USB_REQ_SET_SEL:
707 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL");
708 ret = dwc3_ep0_set_sel(dwc, ctrl);
710 case USB_REQ_SET_ISOCH_DELAY:
711 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY");
712 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
715 dev_vdbg(dwc->dev, "Forwarding to gadget driver");
716 ret = dwc3_ep0_delegate_req(dwc, ctrl);
723 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
724 const struct dwc3_event_depevt *event)
726 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
730 if (!dwc->gadget_driver)
733 len = le16_to_cpu(ctrl->wLength);
735 dwc->three_stage_setup = false;
736 dwc->ep0_expect_in = false;
737 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
739 dwc->three_stage_setup = true;
740 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
741 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
744 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
745 ret = dwc3_ep0_std_request(dwc, ctrl);
747 ret = dwc3_ep0_delegate_req(dwc, ctrl);
749 if (ret == USB_GADGET_DELAYED_STATUS)
750 dwc->delayed_status = true;
754 dwc3_ep0_stall_and_restart(dwc);
757 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
758 const struct dwc3_event_depevt *event)
760 struct dwc3_request *r = NULL;
761 struct usb_request *ur;
762 struct dwc3_trb *trb;
769 epnum = event->endpoint_number;
772 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
776 r = next_request(&ep0->request_list);
780 dwc3_flush_cache((int)trb, sizeof(*trb));
782 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
783 if (status == DWC3_TRBSTS_SETUP_PENDING) {
784 dev_dbg(dwc->dev, "Setup Pending received");
787 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
794 length = trb->size & DWC3_TRB_SIZE_MASK;
796 if (dwc->ep0_bounced) {
797 unsigned transfer_size = ur->length;
798 unsigned maxp = ep0->endpoint.maxpacket;
800 transfer_size += (maxp - (transfer_size % maxp));
801 transferred = min_t(u32, ur->length,
802 transfer_size - length);
803 dwc3_flush_cache((int)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
804 memcpy(ur->buf, dwc->ep0_bounce, transferred);
806 transferred = ur->length - length;
809 ur->actual += transferred;
811 if ((epnum & 1) && ur->actual < ur->length) {
812 /* for some reason we did not get everything out */
814 dwc3_ep0_stall_and_restart(dwc);
816 dwc3_gadget_giveback(ep0, r, 0);
818 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
819 ur->length && ur->zero) {
822 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
824 ret = dwc3_ep0_start_trans(dwc, epnum,
825 dwc->ctrl_req_addr, 0,
826 DWC3_TRBCTL_CONTROL_DATA);
832 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
833 const struct dwc3_event_depevt *event)
835 struct dwc3_request *r;
837 struct dwc3_trb *trb;
843 if (!list_empty(&dep->request_list)) {
844 r = next_request(&dep->request_list);
846 dwc3_gadget_giveback(dep, r, 0);
849 if (dwc->test_mode) {
852 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
854 dev_dbg(dwc->dev, "Invalid Test #%d",
856 dwc3_ep0_stall_and_restart(dwc);
861 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
862 if (status == DWC3_TRBSTS_SETUP_PENDING)
863 dev_dbg(dwc->dev, "Setup Pending received");
865 dwc->ep0state = EP0_SETUP_PHASE;
866 dwc3_ep0_out_start(dwc);
869 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
870 const struct dwc3_event_depevt *event)
872 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
874 dep->flags &= ~DWC3_EP_BUSY;
875 dep->resource_index = 0;
876 dwc->setup_packet_pending = false;
878 switch (dwc->ep0state) {
879 case EP0_SETUP_PHASE:
880 dev_vdbg(dwc->dev, "Setup Phase");
881 dwc3_ep0_inspect_setup(dwc, event);
885 dev_vdbg(dwc->dev, "Data Phase");
886 dwc3_ep0_complete_data(dwc, event);
889 case EP0_STATUS_PHASE:
890 dev_vdbg(dwc->dev, "Status Phase");
891 dwc3_ep0_complete_status(dwc, event);
894 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
898 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
899 struct dwc3_ep *dep, struct dwc3_request *req)
903 req->direction = !!dep->number;
905 if (req->request.length == 0) {
906 ret = dwc3_ep0_start_trans(dwc, dep->number,
907 dwc->ctrl_req_addr, 0,
908 DWC3_TRBCTL_CONTROL_DATA);
909 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
910 && (dep->number == 0)) {
914 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
917 dev_dbg(dwc->dev, "failed to map request\n");
921 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
923 maxpacket = dep->endpoint.maxpacket;
924 transfer_size = roundup(req->request.length, maxpacket);
926 dwc->ep0_bounced = true;
929 * REVISIT in case request length is bigger than
930 * DWC3_EP0_BOUNCE_SIZE we will need two chained
931 * TRBs to handle the transfer.
933 ret = dwc3_ep0_start_trans(dwc, dep->number,
934 dwc->ep0_bounce_addr, transfer_size,
935 DWC3_TRBCTL_CONTROL_DATA);
937 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
940 dev_dbg(dwc->dev, "failed to map request\n");
944 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
945 req->request.length, DWC3_TRBCTL_CONTROL_DATA);
951 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
953 struct dwc3 *dwc = dep->dwc;
956 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
957 : DWC3_TRBCTL_CONTROL_STATUS2;
959 return dwc3_ep0_start_trans(dwc, dep->number,
960 dwc->ctrl_req_addr, 0, type);
963 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
965 if (dwc->resize_fifos) {
966 dev_dbg(dwc->dev, "Resizing FIFOs");
967 dwc3_gadget_resize_tx_fifos(dwc);
968 dwc->resize_fifos = 0;
971 WARN_ON(dwc3_ep0_start_control_status(dep));
974 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
975 const struct dwc3_event_depevt *event)
977 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
979 __dwc3_ep0_do_control_status(dwc, dep);
982 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
984 struct dwc3_gadget_ep_cmd_params params;
988 if (!dep->resource_index)
991 cmd = DWC3_DEPCMD_ENDTRANSFER;
992 cmd |= DWC3_DEPCMD_CMDIOC;
993 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
994 memset(¶ms, 0, sizeof(params));
995 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
997 dep->resource_index = 0;
1000 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1001 const struct dwc3_event_depevt *event)
1003 dwc->setup_packet_pending = true;
1005 switch (event->status) {
1006 case DEPEVT_STATUS_CONTROL_DATA:
1007 dev_vdbg(dwc->dev, "Control Data");
1010 * We already have a DATA transfer in the controller's cache,
1011 * if we receive a XferNotReady(DATA) we will ignore it, unless
1012 * it's for the wrong direction.
1014 * In that case, we must issue END_TRANSFER command to the Data
1015 * Phase we already have started and issue SetStall on the
1018 if (dwc->ep0_expect_in != event->endpoint_number) {
1019 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1021 dev_vdbg(dwc->dev, "Wrong direction for Data phase");
1022 dwc3_ep0_end_control_data(dwc, dep);
1023 dwc3_ep0_stall_and_restart(dwc);
1029 case DEPEVT_STATUS_CONTROL_STATUS:
1030 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1033 dev_vdbg(dwc->dev, "Control Status");
1035 dwc->ep0state = EP0_STATUS_PHASE;
1037 if (dwc->delayed_status) {
1038 WARN_ON_ONCE(event->endpoint_number != 1);
1039 dev_vdbg(dwc->dev, "Delayed Status");
1043 dwc3_ep0_do_control_status(dwc, event);
1047 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1048 const struct dwc3_event_depevt *event)
1050 u8 epnum = event->endpoint_number;
1052 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'",
1053 dwc3_ep_event_string(event->endpoint_event),
1054 epnum >> 1, (epnum & 1) ? "in" : "out",
1055 dwc3_ep0_state_string(dwc->ep0state));
1057 switch (event->endpoint_event) {
1058 case DWC3_DEPEVT_XFERCOMPLETE:
1059 dwc3_ep0_xfer_complete(dwc, event);
1062 case DWC3_DEPEVT_XFERNOTREADY:
1063 dwc3_ep0_xfernotready(dwc, event);
1066 case DWC3_DEPEVT_XFERINPROGRESS:
1067 case DWC3_DEPEVT_RXTXFIFOEVT:
1068 case DWC3_DEPEVT_STREAMEVT:
1069 case DWC3_DEPEVT_EPCMDCMPLT: