drivers/usb/dwc3/dwc3-omap.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * dwc3-omap.c - OMAP Specific Glue layer
   4  *
   5  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  *
  10  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/dwc3-omap.c) and ported
  11  * to uboot.
  12  *
  13  * commit 7ee2566ff5 : usb: dwc3: dwc3-omap: get rid of ->prepare()/->complete()
  14  */
  15
  16 #include <common.h>
  17 #include <malloc.h>
  18 #include <asm/io.h>
  19 #include <dwc3-omap-uboot.h>
  20 #include <linux/usb/dwc3-omap.h>
  21 #include <linux/ioport.h>
  22
  23 #include <linux/usb/otg.h>
  24 #include <linux/compat.h>
  25
  26 #include "linux-compat.h"
  27
  28 /*
  29  * All these registers belong to OMAP's Wrapper around the
  30  * DesignWare USB3 Core.
  31  */
  32
  33 #define USBOTGSS_REVISION                       0x0000
  34 #define USBOTGSS_SYSCONFIG                      0x0010
  35 #define USBOTGSS_IRQ_EOI                        0x0020
  36 #define USBOTGSS_EOI_OFFSET                     0x0008
  37 #define USBOTGSS_IRQSTATUS_RAW_0                0x0024
  38 #define USBOTGSS_IRQSTATUS_0                    0x0028
  39 #define USBOTGSS_IRQENABLE_SET_0                0x002c
  40 #define USBOTGSS_IRQENABLE_CLR_0                0x0030
  41 #define USBOTGSS_IRQ0_OFFSET                    0x0004
  42 #define USBOTGSS_IRQSTATUS_RAW_1                0x0030
  43 #define USBOTGSS_IRQSTATUS_1                    0x0034
  44 #define USBOTGSS_IRQENABLE_SET_1                0x0038
  45 #define USBOTGSS_IRQENABLE_CLR_1                0x003c
  46 #define USBOTGSS_IRQSTATUS_RAW_2                0x0040
  47 #define USBOTGSS_IRQSTATUS_2                    0x0044
  48 #define USBOTGSS_IRQENABLE_SET_2                0x0048
  49 #define USBOTGSS_IRQENABLE_CLR_2                0x004c
  50 #define USBOTGSS_IRQSTATUS_RAW_3                0x0050
  51 #define USBOTGSS_IRQSTATUS_3                    0x0054
  52 #define USBOTGSS_IRQENABLE_SET_3                0x0058
  53 #define USBOTGSS_IRQENABLE_CLR_3                0x005c
  54 #define USBOTGSS_IRQSTATUS_EOI_MISC             0x0030
  55 #define USBOTGSS_IRQSTATUS_RAW_MISC             0x0034
  56 #define USBOTGSS_IRQSTATUS_MISC                 0x0038
  57 #define USBOTGSS_IRQENABLE_SET_MISC             0x003c
  58 #define USBOTGSS_IRQENABLE_CLR_MISC             0x0040
  59 #define USBOTGSS_IRQMISC_OFFSET                 0x03fc
  60 #define USBOTGSS_UTMI_OTG_CTRL                  0x0080
  61 #define USBOTGSS_UTMI_OTG_STATUS                0x0084
  62 #define USBOTGSS_UTMI_OTG_OFFSET                0x0480
  63 #define USBOTGSS_TXFIFO_DEPTH                   0x0508
  64 #define USBOTGSS_RXFIFO_DEPTH                   0x050c
  65 #define USBOTGSS_MMRAM_OFFSET                   0x0100
  66 #define USBOTGSS_FLADJ                          0x0104
  67 #define USBOTGSS_DEBUG_CFG                      0x0108
  68 #define USBOTGSS_DEBUG_DATA                     0x010c
  69 #define USBOTGSS_DEV_EBC_EN                     0x0110
  70 #define USBOTGSS_DEBUG_OFFSET                   0x0600
  71
  72 /* SYSCONFIG REGISTER */
  73 #define USBOTGSS_SYSCONFIG_DMADISABLE           (1 << 16)
  74
  75 /* IRQ_EOI REGISTER */
  76 #define USBOTGSS_IRQ_EOI_LINE_NUMBER            (1 << 0)
  77
  78 /* IRQS0 BITS */
  79 #define USBOTGSS_IRQO_COREIRQ_ST                (1 << 0)
  80
  81 /* IRQMISC BITS */
  82 #define USBOTGSS_IRQMISC_DMADISABLECLR          (1 << 17)
  83 #define USBOTGSS_IRQMISC_OEVT                   (1 << 16)
  84 #define USBOTGSS_IRQMISC_DRVVBUS_RISE           (1 << 13)
  85 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE          (1 << 12)
  86 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE       (1 << 11)
  87 #define USBOTGSS_IRQMISC_IDPULLUP_RISE          (1 << 8)
  88 #define USBOTGSS_IRQMISC_DRVVBUS_FALL           (1 << 5)
  89 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL          (1 << 4)
  90 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL               (1 << 3)
  91 #define USBOTGSS_IRQMISC_IDPULLUP_FALL          (1 << 0)
  92
  93 #define USBOTGSS_INTERRUPTS (USBOTGSS_IRQMISC_OEVT | \
  94                              USBOTGSS_IRQMISC_DRVVBUS_RISE | \
  95                              USBOTGSS_IRQMISC_CHRGVBUS_RISE | \
  96                              USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | \
  97                              USBOTGSS_IRQMISC_IDPULLUP_RISE | \
  98                              USBOTGSS_IRQMISC_DRVVBUS_FALL | \
  99                              USBOTGSS_IRQMISC_CHRGVBUS_FALL | \
 100                              USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | \
 101                              USBOTGSS_IRQMISC_IDPULLUP_FALL)
 102
 103 /* UTMI_OTG_CTRL REGISTER */
 104 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS          (1 << 5)
 105 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS         (1 << 4)
 106 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS      (1 << 3)
 107 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP         (1 << 0)
 108
 109 /* UTMI_OTG_STATUS REGISTER */
 110 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE        (1 << 31)
 111 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT   (1 << 9)
 112 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
 113 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG          (1 << 4)
 114 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND        (1 << 3)
 115 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID      (1 << 2)
 116 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID      (1 << 1)
 117
 118 struct dwc3_omap {
 119         struct device           *dev;
 120
 121         void __iomem            *base;
 122
 123         u32                     utmi_otg_status;
 124         u32                     utmi_otg_offset;
 125         u32                     irqmisc_offset;
 126         u32                     irq_eoi_offset;
 127         u32                     debug_offset;
 128         u32                     irq0_offset;
 129
 130         u32                     dma_status:1;
 131         struct list_head        list;
 132         u32                     index;
 133 };
 134
 135 static LIST_HEAD(dwc3_omap_list);
 136
 137 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
 138 {
 139         return readl(base + offset);
 140 }
 141
 142 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
 143 {
 144         writel(value, base + offset);
 145 }
 146
 147 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)
 148 {
 149         return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
 150                                                         omap->utmi_otg_offset);
 151 }
 152
 153 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)
 154 {
 155         dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
 156                                         omap->utmi_otg_offset, value);
 157
 158 }
 159
 160 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
 161 {
 162         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
 163                                                 omap->irq0_offset);
 164 }
 165
 166 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
 167 {
 168         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
 169                                                 omap->irq0_offset, value);
 170
 171 }
 172
 173 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
 174 {
 175         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
 176                                                 omap->irqmisc_offset);
 177 }
 178
 179 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
 180 {
 181         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
 182                                         omap->irqmisc_offset, value);
 183
 184 }
 185
 186 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
 187 {
 188         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
 189                                                 omap->irqmisc_offset, value);
 190
 191 }
 192
 193 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
 194 {
 195         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
 196                                                 omap->irq0_offset, value);
 197 }
 198
 199 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
 200 {
 201         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
 202                                                 omap->irqmisc_offset, value);
 203 }
 204
 205 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
 206 {
 207         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
 208                                                 omap->irq0_offset, value);
 209 }
 210
 211 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
 212         enum omap_dwc3_vbus_id_status status)
 213 {
 214         u32     val;
 215
 216         switch (status) {
 217         case OMAP_DWC3_ID_GROUND:
 218                 dev_dbg(omap->dev, "ID GND\n");
 219
 220                 val = dwc3_omap_read_utmi_status(omap);
 221                 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
 222                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 223                                 | USBOTGSS_UTMI_OTG_STATUS_SESSEND);
 224                 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 225                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
 226                 dwc3_omap_write_utmi_status(omap, val);
 227                 break;
 228
 229         case OMAP_DWC3_VBUS_VALID:
 230                 dev_dbg(omap->dev, "VBUS Connect\n");
 231
 232                 val = dwc3_omap_read_utmi_status(omap);
 233                 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
 234                 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
 235                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 236                                 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 237                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
 238                 dwc3_omap_write_utmi_status(omap, val);
 239                 break;
 240
 241         case OMAP_DWC3_ID_FLOAT:
 242         case OMAP_DWC3_VBUS_OFF:
 243                 dev_dbg(omap->dev, "VBUS Disconnect\n");
 244
 245                 val = dwc3_omap_read_utmi_status(omap);
 246                 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 247                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 248                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
 249                 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
 250                                 | USBOTGSS_UTMI_OTG_STATUS_IDDIG;
 251                 dwc3_omap_write_utmi_status(omap, val);
 252                 break;
 253
 254         default:
 255                 dev_dbg(omap->dev, "invalid state\n");
 256         }
 257 }
 258
 259 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
 260 {
 261         struct dwc3_omap        *omap = _omap;
 262         u32                     reg;
 263
 264         reg = dwc3_omap_read_irqmisc_status(omap);
 265
 266         if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) {
 267                 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
 268                 omap->dma_status = false;
 269         }
 270
 271         if (reg & USBOTGSS_IRQMISC_OEVT)
 272                 dev_dbg(omap->dev, "OTG Event\n");
 273
 274         if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE)
 275                 dev_dbg(omap->dev, "DRVVBUS Rise\n");
 276
 277         if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE)
 278                 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
 279
 280         if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE)
 281                 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
 282
 283         if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE)
 284                 dev_dbg(omap->dev, "IDPULLUP Rise\n");
 285
 286         if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL)
 287                 dev_dbg(omap->dev, "DRVVBUS Fall\n");
 288
 289         if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL)
 290                 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
 291
 292         if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL)
 293                 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
 294
 295         if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL)
 296                 dev_dbg(omap->dev, "IDPULLUP Fall\n");
 297
 298         dwc3_omap_write_irqmisc_status(omap, reg);
 299
 300         reg = dwc3_omap_read_irq0_status(omap);
 301
 302         dwc3_omap_write_irq0_status(omap, reg);
 303
 304         return IRQ_HANDLED;
 305 }
 306
 307 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
 308 {
 309         /* enable all IRQs */
 310         dwc3_omap_write_irq0_set(omap, USBOTGSS_IRQO_COREIRQ_ST);
 311
 312         dwc3_omap_write_irqmisc_set(omap, USBOTGSS_INTERRUPTS);
 313 }
 314
 315 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
 316 {
 317         /* disable all IRQs */
 318         dwc3_omap_write_irq0_clr(omap, USBOTGSS_IRQO_COREIRQ_ST);
 319
 320         dwc3_omap_write_irqmisc_clr(omap, USBOTGSS_INTERRUPTS);
 321 }
 322
 323 static void dwc3_omap_map_offset(struct dwc3_omap *omap)
 324 {
 325         /*
 326          * Differentiate between OMAP5 and AM437x.
 327          *
 328          * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
 329          * though there are changes in wrapper register offsets.
 330          *
 331          * Using dt compatible to differentiate AM437x.
 332          */
 333 #ifdef CONFIG_AM43XX
 334         omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
 335         omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
 336         omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
 337         omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
 338         omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
 339 #endif
 340 }
 341
 342 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap, int utmi_mode)
 343 {
 344         u32                     reg;
 345
 346         reg = dwc3_omap_read_utmi_status(omap);
 347
 348         switch (utmi_mode) {
 349         case DWC3_OMAP_UTMI_MODE_SW:
 350                 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
 351                 break;
 352         case DWC3_OMAP_UTMI_MODE_HW:
 353                 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
 354                 break;
 355         default:
 356                 dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
 357         }
 358
 359         dwc3_omap_write_utmi_status(omap, reg);
 360 }
 361
 362 /**
 363  * dwc3_omap_uboot_init - dwc3 omap uboot initialization code
 364  * @dev: struct dwc3_omap_device containing initialization data
 365  *
 366  * Entry point for dwc3 omap driver (equivalent to dwc3_omap_probe in linux
 367  * kernel driver). Pointer to dwc3_omap_device should be passed containing
 368  * base address and other initialization data. Returns '0' on success and
 369  * a negative value on failure.
 370  *
 371  * Generally called from board_usb_init() implemented in board file.
 372  */
 373 int dwc3_omap_uboot_init(struct dwc3_omap_device *omap_dev)
 374 {
 375         u32                     reg;
 376         struct device           *dev = NULL;
 377         struct dwc3_omap        *omap;
 378
 379         omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
 380         if (!omap)
 381                 return -ENOMEM;
 382
 383         omap->base      = omap_dev->base;
 384         omap->index     = omap_dev->index;
 385
 386         dwc3_omap_map_offset(omap);
 387         dwc3_omap_set_utmi_mode(omap, omap_dev->utmi_mode);
 388
 389         /* check the DMA Status */
 390         reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
 391         omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
 392
 393         dwc3_omap_set_mailbox(omap, omap_dev->vbus_id_status);
 394
 395         dwc3_omap_enable_irqs(omap);
 396         list_add_tail(&omap->list, &dwc3_omap_list);
 397
 398         return 0;
 399 }
 400
 401 /**
 402  * dwc3_omap_uboot_exit - dwc3 omap uboot cleanup code
 403  * @index: index of this controller
 404  *
 405  * Performs cleanup of memory allocated in dwc3_omap_uboot_init
 406  * (equivalent to dwc3_omap_remove in linux). index of _this_ controller
 407  * should be passed and should match with the index passed in
 408  * dwc3_omap_device during init.
 409  *
 410  * Generally called from board file.
 411  */
 412 void dwc3_omap_uboot_exit(int index)
 413 {
 414         struct dwc3_omap *omap = NULL;
 415
 416         list_for_each_entry(omap, &dwc3_omap_list, list) {
 417                 if (omap->index != index)
 418                         continue;
 419
 420                 dwc3_omap_disable_irqs(omap);
 421                 list_del(&omap->list);
 422                 kfree(omap);
 423                 break;
 424         }
 425 }
 426
 427 /**
 428  * dwc3_omap_uboot_interrupt_status - check the status of interrupt
 429  * @index: index of this controller
 430  *
 431  * Checks the status of interrupts and returns true if an interrupt
 432  * is detected or false otherwise.
 433  *
 434  * Generally called from board file.
 435  */
 436 int dwc3_omap_uboot_interrupt_status(int index)
 437 {
 438         struct dwc3_omap *omap = NULL;
 439
 440         list_for_each_entry(omap, &dwc3_omap_list, list)
 441                 if (omap->index == index)
 442                         return dwc3_omap_interrupt(-1, omap);
 443
 444         return 0;
 445 }
 446
 447 MODULE_ALIAS("platform:omap-dwc3");
 448 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 449 MODULE_LICENSE("GPL v2");
 450 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");