1 // SPDX-License-Identifier: GPL-2.0
3 * Amlogic G12A DWC3 Glue layer
5 * Copyright (C) 2019 BayLibre, SAS
6 * Author: Neil Armstrong <narmstrong@baylibre.com>
11 #include <asm-generic/io.h>
13 #include <dm/device-internal.h>
15 #include <dwc3-uboot.h>
16 #include <generic-phy.h>
17 #include <linux/delay.h>
18 #include <linux/usb/ch9.h>
19 #include <linux/usb/gadget.h>
27 #include <power/regulator.h>
28 #include <linux/bitfield.h>
29 #include <linux/bitops.h>
30 #include <linux/compat.h>
32 /* USB2 Ports Control Registers */
34 #define U2P_REG_SIZE 0x20
37 #define U2P_R0_HOST_DEVICE BIT(0)
38 #define U2P_R0_POWER_OK BIT(1)
39 #define U2P_R0_HAST_MODE BIT(2)
40 #define U2P_R0_POWER_ON_RESET BIT(3)
41 #define U2P_R0_ID_PULLUP BIT(4)
42 #define U2P_R0_DRV_VBUS BIT(5)
45 #define U2P_R1_PHY_READY BIT(0)
46 #define U2P_R1_ID_DIG BIT(1)
47 #define U2P_R1_OTG_SESSION_VALID BIT(2)
48 #define U2P_R1_VBUS_VALID BIT(3)
50 /* USB Glue Control Registers */
53 #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17)
54 #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18)
55 #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
56 #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
57 #define USB_R0_U2D_ACT BIT(31)
60 #define USB_R1_U3H_BIGENDIAN_GS BIT(0)
61 #define USB_R1_U3H_PME_ENABLE BIT(1)
62 #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(4, 2)
63 #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(9, 7)
64 #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(13, 12)
65 #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16)
66 #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17)
67 #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18)
68 #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
69 #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
72 #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)
73 #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)
76 #define USB_R3_P30_SSC_ENABLE BIT(0)
77 #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)
78 #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)
79 #define USB_R3_P30_REF_SSP_EN BIT(13)
82 #define USB_R4_P21_PORT_RESET_0 BIT(0)
83 #define USB_R4_P21_SLEEP_M0 BIT(1)
84 #define USB_R4_MEM_PD_MASK GENMASK(3, 2)
85 #define USB_R4_P21_ONLY BIT(4)
88 #define USB_R5_ID_DIG_SYNC BIT(0)
89 #define USB_R5_ID_DIG_REG BIT(1)
90 #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)
91 #define USB_R5_ID_DIG_EN_0 BIT(4)
92 #define USB_R5_ID_DIG_EN_1 BIT(5)
93 #define USB_R5_ID_DIG_CURR BIT(6)
94 #define USB_R5_ID_DIG_IRQ BIT(7)
95 #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
96 #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
105 static const char *phy_names[PHY_COUNT] = {
106 "usb2-phy0", "usb2-phy1", "usb3-phy0",
109 struct dwc3_meson_g12a {
111 struct regmap *regmap;
113 struct reset_ctl reset;
114 struct phy phys[PHY_COUNT];
115 enum usb_dr_mode otg_mode;
116 enum usb_dr_mode otg_phy_mode;
117 unsigned int usb2_ports;
118 unsigned int usb3_ports;
119 #if CONFIG_IS_ENABLED(DM_REGULATOR)
120 struct udevice *vbus_supply;
124 #define U2P_REG_SIZE 0x20
125 #define USB_REG_OFFSET 0x80
127 static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv,
128 int i, enum usb_dr_mode mode)
131 case USB_DR_MODE_HOST:
132 case USB_DR_MODE_OTG:
133 case USB_DR_MODE_UNKNOWN:
134 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
139 case USB_DR_MODE_PERIPHERAL:
140 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
141 U2P_R0_HOST_DEVICE, 0);
146 static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv)
150 if (priv->otg_mode == USB_DR_MODE_PERIPHERAL)
151 priv->otg_phy_mode = USB_DR_MODE_PERIPHERAL;
153 priv->otg_phy_mode = USB_DR_MODE_HOST;
155 for (i = 0 ; i < USB3_HOST_PHY ; ++i) {
156 if (!priv->phys[i].dev)
159 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
160 U2P_R0_POWER_ON_RESET,
161 U2P_R0_POWER_ON_RESET);
163 if (i == USB2_OTG_PHY) {
164 regmap_update_bits(priv->regmap,
165 U2P_R0 + (U2P_REG_SIZE * i),
166 U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS,
167 U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS);
169 dwc3_meson_g12a_usb2_set_mode(priv, i,
172 dwc3_meson_g12a_usb2_set_mode(priv, i,
175 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
176 U2P_R0_POWER_ON_RESET, 0);
182 static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv)
184 regmap_update_bits(priv->regmap, USB_R3,
185 USB_R3_P30_SSC_RANGE_MASK |
186 USB_R3_P30_REF_SSP_EN,
187 USB_R3_P30_SSC_ENABLE |
188 FIELD_PREP(USB_R3_P30_SSC_RANGE_MASK, 2) |
189 USB_R3_P30_REF_SSP_EN);
192 regmap_update_bits(priv->regmap, USB_R2,
193 USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK,
194 FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, 0x15));
196 regmap_update_bits(priv->regmap, USB_R2,
197 USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK,
198 FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, 0x20));
202 regmap_update_bits(priv->regmap, USB_R1,
203 USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT,
204 USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT);
206 regmap_update_bits(priv->regmap, USB_R1,
207 USB_R1_P30_PCS_TX_SWING_FULL_MASK,
208 FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127));
211 static void dwc3_meson_g12a_usb_init_mode(struct dwc3_meson_g12a *priv)
213 if (priv->otg_phy_mode == USB_DR_MODE_PERIPHERAL) {
214 regmap_update_bits(priv->regmap, USB_R0,
215 USB_R0_U2D_ACT, USB_R0_U2D_ACT);
216 regmap_update_bits(priv->regmap, USB_R0,
217 USB_R0_U2D_SS_SCALEDOWN_MODE_MASK, 0);
218 regmap_update_bits(priv->regmap, USB_R4,
219 USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0);
221 regmap_update_bits(priv->regmap, USB_R0,
223 regmap_update_bits(priv->regmap, USB_R4,
224 USB_R4_P21_SLEEP_M0, 0);
228 static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv)
232 ret = dwc3_meson_g12a_usb2_init(priv);
236 regmap_update_bits(priv->regmap, USB_R1,
237 USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
238 FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20));
240 regmap_update_bits(priv->regmap, USB_R5,
243 regmap_update_bits(priv->regmap, USB_R5,
246 regmap_update_bits(priv->regmap, USB_R5,
247 USB_R5_ID_DIG_TH_MASK,
248 FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff));
250 /* If we have an actual SuperSpeed port, initialize it */
251 if (priv->usb3_ports)
252 dwc3_meson_g12a_usb3_init(priv);
254 dwc3_meson_g12a_usb_init_mode(priv);
259 int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode)
261 struct dwc3_meson_g12a *priv = dev_get_platdata(dev);
266 if (mode != USB_DR_MODE_HOST && mode != USB_DR_MODE_PERIPHERAL)
269 if (!priv->phys[USB2_OTG_PHY].dev)
272 if (mode == priv->otg_mode)
275 if (mode == USB_DR_MODE_HOST)
276 debug("%s: switching to Host Mode\n", __func__);
278 debug("%s: switching to Device Mode\n", __func__);
280 #if CONFIG_IS_ENABLED(DM_REGULATOR)
281 if (priv->vbus_supply) {
282 int ret = regulator_set_enable(priv->vbus_supply,
283 (mode == USB_DR_MODE_PERIPHERAL));
288 priv->otg_phy_mode = mode;
290 dwc3_meson_g12a_usb2_set_mode(priv, USB2_OTG_PHY, mode);
292 dwc3_meson_g12a_usb_init_mode(priv);
297 static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv)
301 for (i = 0 ; i < PHY_COUNT ; ++i) {
302 ret = generic_phy_get_by_name(priv->dev, phy_names[i],
310 if (i == USB3_HOST_PHY)
316 debug("%s: usb2 ports: %d\n", __func__, priv->usb2_ports);
317 debug("%s: usb3 ports: %d\n", __func__, priv->usb3_ports);
322 static int dwc3_meson_g12a_reset_init(struct dwc3_meson_g12a *priv)
326 ret = reset_get_by_index(priv->dev, 0, &priv->reset);
330 ret = reset_assert(&priv->reset);
332 ret |= reset_deassert(&priv->reset);
334 reset_free(&priv->reset);
341 static int dwc3_meson_g12a_clk_init(struct dwc3_meson_g12a *priv)
345 ret = clk_get_by_index(priv->dev, 0, &priv->clk);
349 #if CONFIG_IS_ENABLED(CLK)
350 ret = clk_enable(&priv->clk);
352 clk_free(&priv->clk);
360 static int dwc3_meson_g12a_probe(struct udevice *dev)
362 struct dwc3_meson_g12a *priv = dev_get_platdata(dev);
367 ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
371 ret = dwc3_meson_g12a_clk_init(priv);
375 ret = dwc3_meson_g12a_reset_init(priv);
379 ret = dwc3_meson_g12a_get_phys(priv);
383 #if CONFIG_IS_ENABLED(DM_REGULATOR)
384 ret = device_get_supply_regulator(dev, "vbus-supply",
386 if (ret && ret != -ENOENT) {
387 pr_err("Failed to get PHY regulator\n");
391 if (priv->vbus_supply) {
392 ret = regulator_set_enable(priv->vbus_supply, true);
398 priv->otg_mode = usb_get_dr_mode(dev->node);
400 ret = dwc3_meson_g12a_usb_init(priv);
404 for (i = 0 ; i < PHY_COUNT ; ++i) {
405 if (!priv->phys[i].dev)
408 ret = generic_phy_init(&priv->phys[i]);
413 for (i = 0; i < PHY_COUNT; ++i) {
414 if (!priv->phys[i].dev)
417 ret = generic_phy_power_on(&priv->phys[i]);
425 for (i = 0 ; i < PHY_COUNT ; ++i) {
426 if (!priv->phys[i].dev)
429 generic_phy_exit(&priv->phys[i]);
435 static int dwc3_meson_g12a_remove(struct udevice *dev)
437 struct dwc3_meson_g12a *priv = dev_get_platdata(dev);
440 reset_release_all(&priv->reset, 1);
442 clk_release_all(&priv->clk, 1);
444 for (i = 0; i < PHY_COUNT; ++i) {
445 if (!priv->phys[i].dev)
448 generic_phy_power_off(&priv->phys[i]);
451 for (i = 0 ; i < PHY_COUNT ; ++i) {
452 if (!priv->phys[i].dev)
455 generic_phy_exit(&priv->phys[i]);
458 return dm_scan_fdt_dev(dev);
461 static const struct udevice_id dwc3_meson_g12a_ids[] = {
462 { .compatible = "amlogic,meson-g12a-usb-ctrl" },
466 U_BOOT_DRIVER(dwc3_generic_wrapper) = {
467 .name = "dwc3-meson-g12a",
468 .id = UCLASS_SIMPLE_BUS,
469 .of_match = dwc3_meson_g12a_ids,
470 .probe = dwc3_meson_g12a_probe,
471 .remove = dwc3_meson_g12a_remove,
472 .platdata_auto_alloc_size = sizeof(struct dwc3_meson_g12a),