1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - DesignWare USB3 DRD Controller Core file
5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
13 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
18 #include <dwc3-uboot.h>
19 #include <asm/dma-mapping.h>
20 #include <linux/ioport.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
29 #include "linux-compat.h"
31 static LIST_HEAD(dwc3_list);
32 /* -------------------------------------------------------------------------- */
34 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
38 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
39 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
40 reg |= DWC3_GCTL_PRTCAPDIR(mode);
41 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
45 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
46 * @dwc: pointer to our context structure
48 static int dwc3_core_soft_reset(struct dwc3 *dwc)
52 /* Before Resetting PHY, put Core in Reset */
53 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
54 reg |= DWC3_GCTL_CORESOFTRESET;
55 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
57 /* Assert USB3 PHY reset */
58 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
59 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
60 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
62 /* Assert USB2 PHY reset */
63 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
64 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
65 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
69 /* Clear USB3 PHY reset */
70 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
71 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
72 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
74 /* Clear USB2 PHY reset */
75 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
76 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
77 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
81 /* After PHYs are stable we can take Core out of reset state */
82 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
83 reg &= ~DWC3_GCTL_CORESOFTRESET;
84 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
90 * dwc3_free_one_event_buffer - Frees one event buffer
91 * @dwc: Pointer to our controller context structure
92 * @evt: Pointer to event buffer to be freed
94 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
95 struct dwc3_event_buffer *evt)
97 dma_free_coherent(evt->buf);
101 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
102 * @dwc: Pointer to our controller context structure
103 * @length: size of the event buffer
105 * Returns a pointer to the allocated event buffer structure on success
106 * otherwise ERR_PTR(errno).
108 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
111 struct dwc3_event_buffer *evt;
113 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
115 return ERR_PTR(-ENOMEM);
118 evt->length = length;
119 evt->buf = dma_alloc_coherent(length,
120 (unsigned long *)&evt->dma);
122 return ERR_PTR(-ENOMEM);
124 dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
130 * dwc3_free_event_buffers - frees all allocated event buffers
131 * @dwc: Pointer to our controller context structure
133 static void dwc3_free_event_buffers(struct dwc3 *dwc)
135 struct dwc3_event_buffer *evt;
138 for (i = 0; i < dwc->num_event_buffers; i++) {
139 evt = dwc->ev_buffs[i];
141 dwc3_free_one_event_buffer(dwc, evt);
146 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
147 * @dwc: pointer to our controller context structure
148 * @length: size of event buffer
150 * Returns 0 on success otherwise negative errno. In the error case, dwc
151 * may contain some buffers allocated but not all which were requested.
153 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
158 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
159 dwc->num_event_buffers = num;
161 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
162 sizeof(*dwc->ev_buffs) * num);
166 for (i = 0; i < num; i++) {
167 struct dwc3_event_buffer *evt;
169 evt = dwc3_alloc_one_event_buffer(dwc, length);
171 dev_err(dwc->dev, "can't allocate event buffer\n");
174 dwc->ev_buffs[i] = evt;
181 * dwc3_event_buffers_setup - setup our allocated event buffers
182 * @dwc: pointer to our controller context structure
184 * Returns 0 on success otherwise negative errno.
186 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
188 struct dwc3_event_buffer *evt;
191 for (n = 0; n < dwc->num_event_buffers; n++) {
192 evt = dwc->ev_buffs[n];
193 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
194 evt->buf, (unsigned long long) evt->dma,
199 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
200 lower_32_bits(evt->dma));
201 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
202 upper_32_bits(evt->dma));
203 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
204 DWC3_GEVNTSIZ_SIZE(evt->length));
205 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
211 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
213 struct dwc3_event_buffer *evt;
216 for (n = 0; n < dwc->num_event_buffers; n++) {
217 evt = dwc->ev_buffs[n];
221 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
222 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
223 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
224 | DWC3_GEVNTSIZ_SIZE(0));
225 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
229 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
231 if (!dwc->has_hibernation)
234 if (!dwc->nr_scratch)
237 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
238 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
239 if (!dwc->scratchbuf)
245 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
247 dma_addr_t scratch_addr;
251 if (!dwc->has_hibernation)
254 if (!dwc->nr_scratch)
257 scratch_addr = dma_map_single(dwc->scratchbuf,
258 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
260 if (dma_mapping_error(dwc->dev, scratch_addr)) {
261 dev_err(dwc->dev, "failed to map scratch buffer\n");
266 dwc->scratch_addr = scratch_addr;
268 param = lower_32_bits(scratch_addr);
270 ret = dwc3_send_gadget_generic_command(dwc,
271 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
275 param = upper_32_bits(scratch_addr);
277 ret = dwc3_send_gadget_generic_command(dwc,
278 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
285 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
286 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
292 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
294 if (!dwc->has_hibernation)
297 if (!dwc->nr_scratch)
300 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
301 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
302 kfree(dwc->scratchbuf);
305 static void dwc3_core_num_eps(struct dwc3 *dwc)
307 struct dwc3_hwparams *parms = &dwc->hwparams;
309 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
310 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
312 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
313 dwc->num_in_eps, dwc->num_out_eps);
316 static void dwc3_cache_hwparams(struct dwc3 *dwc)
318 struct dwc3_hwparams *parms = &dwc->hwparams;
320 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
321 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
322 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
323 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
324 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
325 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
326 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
327 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
328 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
332 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
333 * @dwc: Pointer to our controller context structure
335 static void dwc3_phy_setup(struct dwc3 *dwc)
339 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
342 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
343 * to '0' during coreConsultant configuration. So default value
344 * will be '0' when the core is reset. Application needs to set it
345 * to '1' after the core initialization is completed.
347 if (dwc->revision > DWC3_REVISION_194A)
348 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
350 if (dwc->u2ss_inp3_quirk)
351 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
353 if (dwc->req_p1p2p3_quirk)
354 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
356 if (dwc->del_p1p2p3_quirk)
357 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
359 if (dwc->del_phy_power_chg_quirk)
360 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
362 if (dwc->lfps_filter_quirk)
363 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
365 if (dwc->rx_detect_poll_quirk)
366 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
368 if (dwc->tx_de_emphasis_quirk)
369 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
371 if (dwc->dis_u3_susphy_quirk)
372 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
374 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
378 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
381 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
382 * '0' during coreConsultant configuration. So default value will
383 * be '0' when the core is reset. Application needs to set it to
384 * '1' after the core initialization is completed.
386 if (dwc->revision > DWC3_REVISION_194A)
387 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
389 if (dwc->dis_u2_susphy_quirk)
390 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
392 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
398 * dwc3_core_init - Low-level initialization of DWC3 Core
399 * @dwc: Pointer to our controller context structure
401 * Returns 0 on success otherwise negative errno.
403 static int dwc3_core_init(struct dwc3 *dwc)
405 unsigned long timeout;
406 u32 hwparams4 = dwc->hwparams.hwparams4;
410 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
411 /* This should read as U3 followed by revision number */
412 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
413 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
419 /* Handle USB2.0-only core configuration */
420 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
421 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
422 if (dwc->maximum_speed == USB_SPEED_SUPER)
423 dwc->maximum_speed = USB_SPEED_HIGH;
426 /* issue device SoftReset too */
428 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
430 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
431 if (!(reg & DWC3_DCTL_CSFTRST))
436 dev_err(dwc->dev, "Reset Timed Out\n");
441 ret = dwc3_core_soft_reset(dwc);
445 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
446 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
448 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
449 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
451 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
452 * issue which would cause xHCI compliance tests to fail.
454 * Because of that we cannot enable clock gating on such
459 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
462 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
463 dwc->dr_mode == USB_DR_MODE_OTG) &&
464 (dwc->revision >= DWC3_REVISION_210A &&
465 dwc->revision <= DWC3_REVISION_250A))
466 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
468 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
470 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
471 /* enable hibernation here */
472 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
475 * REVISIT Enabling this bit so that host-mode hibernation
476 * will work. Device-mode hibernation is not yet implemented.
478 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
481 dev_dbg(dwc->dev, "No power optimization available\n");
484 /* check if current dwc3 is on simulation board */
485 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
486 dev_dbg(dwc->dev, "it is on FPGA board\n");
490 if(dwc->disable_scramble_quirk && !dwc->is_fpga)
492 "disable_scramble cannot be used on non-FPGA builds\n");
494 if (dwc->disable_scramble_quirk && dwc->is_fpga)
495 reg |= DWC3_GCTL_DISSCRAMBLE;
497 reg &= ~DWC3_GCTL_DISSCRAMBLE;
499 if (dwc->u2exit_lfps_quirk)
500 reg |= DWC3_GCTL_U2EXIT_LFPS;
503 * WORKAROUND: DWC3 revisions <1.90a have a bug
504 * where the device can fail to connect at SuperSpeed
505 * and falls back to high-speed mode which causes
506 * the device to enter a Connect/Disconnect loop
508 if (dwc->revision < DWC3_REVISION_190A)
509 reg |= DWC3_GCTL_U2RSTECN;
511 dwc3_core_num_eps(dwc);
513 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
517 ret = dwc3_alloc_scratch_buffers(dwc);
521 ret = dwc3_setup_scratch_buffers(dwc);
528 dwc3_free_scratch_buffers(dwc);
534 static void dwc3_core_exit(struct dwc3 *dwc)
536 dwc3_free_scratch_buffers(dwc);
539 static int dwc3_core_init_mode(struct dwc3 *dwc)
543 switch (dwc->dr_mode) {
544 case USB_DR_MODE_PERIPHERAL:
545 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
546 ret = dwc3_gadget_init(dwc);
548 dev_err(dev, "failed to initialize gadget\n");
552 case USB_DR_MODE_HOST:
553 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
554 ret = dwc3_host_init(dwc);
556 dev_err(dev, "failed to initialize host\n");
560 case USB_DR_MODE_OTG:
561 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
562 ret = dwc3_host_init(dwc);
564 dev_err(dev, "failed to initialize host\n");
568 ret = dwc3_gadget_init(dwc);
570 dev_err(dev, "failed to initialize gadget\n");
575 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
582 static void dwc3_core_exit_mode(struct dwc3 *dwc)
584 switch (dwc->dr_mode) {
585 case USB_DR_MODE_PERIPHERAL:
586 dwc3_gadget_exit(dwc);
588 case USB_DR_MODE_HOST:
591 case USB_DR_MODE_OTG:
593 dwc3_gadget_exit(dwc);
601 #define DWC3_ALIGN_MASK (16 - 1)
604 * dwc3_uboot_init - dwc3 core uboot initialization code
605 * @dwc3_dev: struct dwc3_device containing initialization data
607 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
608 * kernel driver). Pointer to dwc3_device should be passed containing
609 * base address and other initialization data. Returns '0' on success and
610 * a negative value on failure.
612 * Generally called from board_usb_init() implemented in board file.
614 int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
617 struct device *dev = NULL;
618 u8 lpm_nyet_threshold;
626 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
630 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
633 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
634 DWC3_GLOBALS_REGS_START);
636 /* default to highest possible threshold */
637 lpm_nyet_threshold = 0xff;
639 /* default to -3.5dB de-emphasis */
643 * default to assert utmi_sleep_n and use maximum allowed HIRD
644 * threshold value of 0b1100
648 dwc->maximum_speed = dwc3_dev->maximum_speed;
649 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
650 if (dwc3_dev->lpm_nyet_threshold)
651 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
652 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
653 if (dwc3_dev->hird_threshold)
654 hird_threshold = dwc3_dev->hird_threshold;
656 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
657 dwc->dr_mode = dwc3_dev->dr_mode;
659 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
660 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
661 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
662 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
663 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
664 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
665 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
666 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
667 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
668 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
670 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
671 if (dwc3_dev->tx_de_emphasis)
672 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
674 /* default to superspeed if no maximum_speed passed */
675 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
676 dwc->maximum_speed = USB_SPEED_SUPER;
678 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
679 dwc->tx_de_emphasis = tx_de_emphasis;
681 dwc->hird_threshold = hird_threshold
682 | (dwc->is_utmi_l1_suspend << 4);
684 dwc->index = dwc3_dev->index;
686 dwc3_cache_hwparams(dwc);
688 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
690 dev_err(dwc->dev, "failed to allocate event buffers\n");
694 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
695 dwc->dr_mode = USB_DR_MODE_HOST;
696 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
697 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
699 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
700 dwc->dr_mode = USB_DR_MODE_OTG;
702 ret = dwc3_core_init(dwc);
704 dev_err(dev, "failed to initialize core\n");
708 ret = dwc3_event_buffers_setup(dwc);
710 dev_err(dwc->dev, "failed to setup event buffers\n");
714 ret = dwc3_core_init_mode(dwc);
718 list_add_tail(&dwc->list, &dwc3_list);
723 dwc3_event_buffers_cleanup(dwc);
729 dwc3_free_event_buffers(dwc);
735 * dwc3_uboot_exit - dwc3 core uboot cleanup code
736 * @index: index of this controller
738 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
739 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
740 * should be passed and should match with the index passed in
741 * dwc3_device during init.
743 * Generally called from board file.
745 void dwc3_uboot_exit(int index)
749 list_for_each_entry(dwc, &dwc3_list, list) {
750 if (dwc->index != index)
753 dwc3_core_exit_mode(dwc);
754 dwc3_event_buffers_cleanup(dwc);
755 dwc3_free_event_buffers(dwc);
757 list_del(&dwc->list);
764 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
765 * @index: index of this controller
767 * Invokes dwc3 gadget interrupts.
769 * Generally called from board file.
771 void dwc3_uboot_handle_interrupt(int index)
773 struct dwc3 *dwc = NULL;
775 list_for_each_entry(dwc, &dwc3_list, list) {
776 if (dwc->index != index)
779 dwc3_gadget_uboot_handle_interrupt(dwc);
784 MODULE_ALIAS("platform:dwc3");
785 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
786 MODULE_LICENSE("GPL v2");
787 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");