1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - DesignWare USB3 DRD Controller Core file
5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
13 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
19 #include <dwc3-uboot.h>
20 #include <dm/device_compat.h>
21 #include <dm/devres.h>
22 #include <linux/bug.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/err.h>
26 #include <linux/ioport.h>
28 #include <generic-phy.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
36 #include "linux-compat.h"
38 static LIST_HEAD(dwc3_list);
39 /* -------------------------------------------------------------------------- */
41 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
45 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
46 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
47 reg |= DWC3_GCTL_PRTCAPDIR(mode);
48 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
52 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
53 * @dwc: pointer to our context structure
55 static int dwc3_core_soft_reset(struct dwc3 *dwc)
59 /* Before Resetting PHY, put Core in Reset */
60 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
61 reg |= DWC3_GCTL_CORESOFTRESET;
62 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
64 /* Assert USB3 PHY reset */
65 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
66 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
67 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
69 /* Assert USB2 PHY reset */
70 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
71 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
72 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
76 /* Clear USB3 PHY reset */
77 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
78 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
79 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
81 /* Clear USB2 PHY reset */
82 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
83 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
84 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
88 /* After PHYs are stable we can take Core out of reset state */
89 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
90 reg &= ~DWC3_GCTL_CORESOFTRESET;
91 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
97 * dwc3_free_one_event_buffer - Frees one event buffer
98 * @dwc: Pointer to our controller context structure
99 * @evt: Pointer to event buffer to be freed
101 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
102 struct dwc3_event_buffer *evt)
104 dma_free_coherent(evt->buf);
108 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
109 * @dwc: Pointer to our controller context structure
110 * @length: size of the event buffer
112 * Returns a pointer to the allocated event buffer structure on success
113 * otherwise ERR_PTR(errno).
115 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
118 struct dwc3_event_buffer *evt;
120 evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
123 return ERR_PTR(-ENOMEM);
126 evt->length = length;
127 evt->buf = dma_alloc_coherent(length,
128 (unsigned long *)&evt->dma);
130 return ERR_PTR(-ENOMEM);
132 dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
138 * dwc3_free_event_buffers - frees all allocated event buffers
139 * @dwc: Pointer to our controller context structure
141 static void dwc3_free_event_buffers(struct dwc3 *dwc)
143 struct dwc3_event_buffer *evt;
146 for (i = 0; i < dwc->num_event_buffers; i++) {
147 evt = dwc->ev_buffs[i];
149 dwc3_free_one_event_buffer(dwc, evt);
154 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
155 * @dwc: pointer to our controller context structure
156 * @length: size of event buffer
158 * Returns 0 on success otherwise negative errno. In the error case, dwc
159 * may contain some buffers allocated but not all which were requested.
161 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
166 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
167 dwc->num_event_buffers = num;
169 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
170 sizeof(*dwc->ev_buffs) * num);
174 for (i = 0; i < num; i++) {
175 struct dwc3_event_buffer *evt;
177 evt = dwc3_alloc_one_event_buffer(dwc, length);
179 dev_err(dwc->dev, "can't allocate event buffer\n");
182 dwc->ev_buffs[i] = evt;
189 * dwc3_event_buffers_setup - setup our allocated event buffers
190 * @dwc: pointer to our controller context structure
192 * Returns 0 on success otherwise negative errno.
194 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
196 struct dwc3_event_buffer *evt;
199 for (n = 0; n < dwc->num_event_buffers; n++) {
200 evt = dwc->ev_buffs[n];
201 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
202 evt->buf, (unsigned long long) evt->dma,
207 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
208 lower_32_bits(evt->dma));
209 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
210 upper_32_bits(evt->dma));
211 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
212 DWC3_GEVNTSIZ_SIZE(evt->length));
213 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
219 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
221 struct dwc3_event_buffer *evt;
224 for (n = 0; n < dwc->num_event_buffers; n++) {
225 evt = dwc->ev_buffs[n];
229 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
230 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
231 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
232 | DWC3_GEVNTSIZ_SIZE(0));
233 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
237 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
239 if (!dwc->has_hibernation)
242 if (!dwc->nr_scratch)
245 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
246 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
247 if (!dwc->scratchbuf)
253 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
255 dma_addr_t scratch_addr;
259 if (!dwc->has_hibernation)
262 if (!dwc->nr_scratch)
265 scratch_addr = dma_map_single(dwc->scratchbuf,
266 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
268 if (dma_mapping_error(dwc->dev, scratch_addr)) {
269 dev_err(dwc->dev, "failed to map scratch buffer\n");
274 dwc->scratch_addr = scratch_addr;
276 param = lower_32_bits(scratch_addr);
278 ret = dwc3_send_gadget_generic_command(dwc,
279 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
283 param = upper_32_bits(scratch_addr);
285 ret = dwc3_send_gadget_generic_command(dwc,
286 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
293 dma_unmap_single(scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
300 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
302 if (!dwc->has_hibernation)
305 if (!dwc->nr_scratch)
308 dma_unmap_single(dwc->scratch_addr, dwc->nr_scratch *
309 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
310 kfree(dwc->scratchbuf);
313 static void dwc3_core_num_eps(struct dwc3 *dwc)
315 struct dwc3_hwparams *parms = &dwc->hwparams;
317 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
318 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
320 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
321 dwc->num_in_eps, dwc->num_out_eps);
324 static void dwc3_cache_hwparams(struct dwc3 *dwc)
326 struct dwc3_hwparams *parms = &dwc->hwparams;
328 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
329 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
330 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
331 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
332 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
333 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
334 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
335 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
336 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
339 static void dwc3_hsphy_mode_setup(struct dwc3 *dwc)
341 enum usb_phy_interface hsphy_mode = dwc->hsphy_mode;
344 /* Set dwc3 usb2 phy config */
345 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
347 switch (hsphy_mode) {
348 case USBPHY_INTERFACE_MODE_UTMI:
349 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
350 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
351 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
352 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
354 case USBPHY_INTERFACE_MODE_UTMIW:
355 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
356 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
357 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
358 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
364 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
368 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
369 * @dwc: Pointer to our controller context structure
371 static void dwc3_phy_setup(struct dwc3 *dwc)
375 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
378 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
379 * to '0' during coreConsultant configuration. So default value
380 * will be '0' when the core is reset. Application needs to set it
381 * to '1' after the core initialization is completed.
383 if (dwc->revision > DWC3_REVISION_194A)
384 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
386 if (dwc->u2ss_inp3_quirk)
387 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
389 if (dwc->req_p1p2p3_quirk)
390 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
392 if (dwc->del_p1p2p3_quirk)
393 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
395 if (dwc->del_phy_power_chg_quirk)
396 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
398 if (dwc->lfps_filter_quirk)
399 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
401 if (dwc->rx_detect_poll_quirk)
402 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
404 if (dwc->tx_de_emphasis_quirk)
405 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
407 if (dwc->dis_u3_susphy_quirk)
408 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
410 if (dwc->dis_del_phy_power_chg_quirk)
411 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
413 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
415 dwc3_hsphy_mode_setup(dwc);
419 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
422 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
423 * '0' during coreConsultant configuration. So default value will
424 * be '0' when the core is reset. Application needs to set it to
425 * '1' after the core initialization is completed.
427 if (dwc->revision > DWC3_REVISION_194A)
428 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
430 if (dwc->dis_u2_susphy_quirk)
431 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
433 if (dwc->dis_enblslpm_quirk)
434 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
436 if (dwc->dis_u2_freeclk_exists_quirk)
437 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
439 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
445 * dwc3_core_init - Low-level initialization of DWC3 Core
446 * @dwc: Pointer to our controller context structure
448 * Returns 0 on success otherwise negative errno.
450 static int dwc3_core_init(struct dwc3 *dwc)
452 unsigned long timeout;
453 u32 hwparams4 = dwc->hwparams.hwparams4;
457 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
458 /* This should read as U3 followed by revision number */
459 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
460 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
466 /* Handle USB2.0-only core configuration */
467 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
468 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
469 if (dwc->maximum_speed == USB_SPEED_SUPER)
470 dwc->maximum_speed = USB_SPEED_HIGH;
473 /* issue device SoftReset too */
475 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
477 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
478 if (!(reg & DWC3_DCTL_CSFTRST))
483 dev_err(dwc->dev, "Reset Timed Out\n");
490 ret = dwc3_core_soft_reset(dwc);
494 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
495 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
497 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
498 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
500 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
501 * issue which would cause xHCI compliance tests to fail.
503 * Because of that we cannot enable clock gating on such
508 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
511 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
512 dwc->dr_mode == USB_DR_MODE_OTG) &&
513 (dwc->revision >= DWC3_REVISION_210A &&
514 dwc->revision <= DWC3_REVISION_250A))
515 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
517 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
519 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
520 /* enable hibernation here */
521 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
524 * REVISIT Enabling this bit so that host-mode hibernation
525 * will work. Device-mode hibernation is not yet implemented.
527 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
530 dev_dbg(dwc->dev, "No power optimization available\n");
533 /* check if current dwc3 is on simulation board */
534 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
535 dev_dbg(dwc->dev, "it is on FPGA board\n");
539 if(dwc->disable_scramble_quirk && !dwc->is_fpga)
541 "disable_scramble cannot be used on non-FPGA builds\n");
543 if (dwc->disable_scramble_quirk && dwc->is_fpga)
544 reg |= DWC3_GCTL_DISSCRAMBLE;
546 reg &= ~DWC3_GCTL_DISSCRAMBLE;
548 if (dwc->u2exit_lfps_quirk)
549 reg |= DWC3_GCTL_U2EXIT_LFPS;
552 * WORKAROUND: DWC3 revisions <1.90a have a bug
553 * where the device can fail to connect at SuperSpeed
554 * and falls back to high-speed mode which causes
555 * the device to enter a Connect/Disconnect loop
557 if (dwc->revision < DWC3_REVISION_190A)
558 reg |= DWC3_GCTL_U2RSTECN;
560 dwc3_core_num_eps(dwc);
562 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
564 ret = dwc3_alloc_scratch_buffers(dwc);
568 ret = dwc3_setup_scratch_buffers(dwc);
575 dwc3_free_scratch_buffers(dwc);
581 static void dwc3_core_exit(struct dwc3 *dwc)
583 dwc3_free_scratch_buffers(dwc);
586 static int dwc3_core_init_mode(struct dwc3 *dwc)
590 switch (dwc->dr_mode) {
591 case USB_DR_MODE_PERIPHERAL:
592 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
593 ret = dwc3_gadget_init(dwc);
595 dev_err(dev, "failed to initialize gadget\n");
599 case USB_DR_MODE_HOST:
600 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
601 ret = dwc3_host_init(dwc);
603 dev_err(dev, "failed to initialize host\n");
607 case USB_DR_MODE_OTG:
608 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
609 ret = dwc3_host_init(dwc);
611 dev_err(dev, "failed to initialize host\n");
615 ret = dwc3_gadget_init(dwc);
617 dev_err(dev, "failed to initialize gadget\n");
622 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
629 static void dwc3_gadget_run(struct dwc3 *dwc)
631 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
635 static void dwc3_core_exit_mode(struct dwc3 *dwc)
637 switch (dwc->dr_mode) {
638 case USB_DR_MODE_PERIPHERAL:
639 dwc3_gadget_exit(dwc);
641 case USB_DR_MODE_HOST:
644 case USB_DR_MODE_OTG:
646 dwc3_gadget_exit(dwc);
654 * switch back to peripheral mode
655 * This enables the phy to enter idle and then, if enabled, suspend.
657 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
658 dwc3_gadget_run(dwc);
661 #define DWC3_ALIGN_MASK (16 - 1)
664 * dwc3_uboot_init - dwc3 core uboot initialization code
665 * @dwc3_dev: struct dwc3_device containing initialization data
667 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
668 * kernel driver). Pointer to dwc3_device should be passed containing
669 * base address and other initialization data. Returns '0' on success and
670 * a negative value on failure.
672 * Generally called from board_usb_init() implemented in board file.
674 int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
677 struct device *dev = NULL;
678 u8 lpm_nyet_threshold;
686 mem = devm_kzalloc((struct udevice *)dev,
687 sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
691 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
694 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
695 DWC3_GLOBALS_REGS_START);
697 /* default to highest possible threshold */
698 lpm_nyet_threshold = 0xff;
700 /* default to -3.5dB de-emphasis */
704 * default to assert utmi_sleep_n and use maximum allowed HIRD
705 * threshold value of 0b1100
709 dwc->maximum_speed = dwc3_dev->maximum_speed;
710 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
711 if (dwc3_dev->lpm_nyet_threshold)
712 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
713 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
714 if (dwc3_dev->hird_threshold)
715 hird_threshold = dwc3_dev->hird_threshold;
717 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
718 dwc->dr_mode = dwc3_dev->dr_mode;
720 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
721 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
722 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
723 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
724 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
725 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
726 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
727 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
728 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
729 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
730 dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
731 dwc->dis_tx_ipgap_linecheck_quirk = dwc3_dev->dis_tx_ipgap_linecheck_quirk;
732 dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
733 dwc->dis_u2_freeclk_exists_quirk = dwc3_dev->dis_u2_freeclk_exists_quirk;
735 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
736 if (dwc3_dev->tx_de_emphasis)
737 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
739 /* default to superspeed if no maximum_speed passed */
740 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
741 dwc->maximum_speed = USB_SPEED_SUPER;
743 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
744 dwc->tx_de_emphasis = tx_de_emphasis;
746 dwc->hird_threshold = hird_threshold
747 | (dwc->is_utmi_l1_suspend << 4);
749 dwc->hsphy_mode = dwc3_dev->hsphy_mode;
751 dwc->index = dwc3_dev->index;
753 dwc3_cache_hwparams(dwc);
755 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
757 dev_err(dwc->dev, "failed to allocate event buffers\n");
761 if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
762 dwc->dr_mode = USB_DR_MODE_HOST;
763 else if (!IS_ENABLED(CONFIG_USB_HOST))
764 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
766 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
767 dwc->dr_mode = USB_DR_MODE_OTG;
769 ret = dwc3_core_init(dwc);
771 dev_err(dev, "failed to initialize core\n");
775 ret = dwc3_event_buffers_setup(dwc);
777 dev_err(dwc->dev, "failed to setup event buffers\n");
781 ret = dwc3_core_init_mode(dwc);
785 list_add_tail(&dwc->list, &dwc3_list);
790 dwc3_event_buffers_cleanup(dwc);
796 dwc3_free_event_buffers(dwc);
802 * dwc3_uboot_exit - dwc3 core uboot cleanup code
803 * @index: index of this controller
805 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
806 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
807 * should be passed and should match with the index passed in
808 * dwc3_device during init.
810 * Generally called from board file.
812 void dwc3_uboot_exit(int index)
816 list_for_each_entry(dwc, &dwc3_list, list) {
817 if (dwc->index != index)
820 dwc3_core_exit_mode(dwc);
821 dwc3_event_buffers_cleanup(dwc);
822 dwc3_free_event_buffers(dwc);
824 list_del(&dwc->list);
831 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
832 * @index: index of this controller
834 * Invokes dwc3 gadget interrupts.
836 * Generally called from board file.
838 void dwc3_uboot_handle_interrupt(int index)
840 struct dwc3 *dwc = NULL;
842 list_for_each_entry(dwc, &dwc3_list, list) {
843 if (dwc->index != index)
846 dwc3_gadget_uboot_handle_interrupt(dwc);
851 MODULE_ALIAS("platform:dwc3");
852 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
853 MODULE_LICENSE("GPL v2");
854 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
856 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
857 int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys)
861 ret = generic_phy_get_bulk(dev, phys);
865 ret = generic_phy_init_bulk(phys);
869 ret = generic_phy_power_on_bulk(phys);
871 generic_phy_exit_bulk(phys);
876 int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys)
880 ret = generic_phy_power_off_bulk(phys);
881 ret |= generic_phy_exit_bulk(phys);
886 #if CONFIG_IS_ENABLED(DM_USB)
887 void dwc3_of_parse(struct dwc3 *dwc)
890 struct udevice *dev = dwc->dev;
891 u8 lpm_nyet_threshold;
895 /* default to highest possible threshold */
896 lpm_nyet_threshold = 0xff;
898 /* default to -3.5dB de-emphasis */
902 * default to assert utmi_sleep_n and use maximum allowed HIRD
903 * threshold value of 0b1100
907 dwc->hsphy_mode = usb_get_phy_mode(dev->node);
909 dwc->has_lpm_erratum = dev_read_bool(dev,
910 "snps,has-lpm-erratum");
911 tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
913 lpm_nyet_threshold = *tmp;
915 dwc->is_utmi_l1_suspend = dev_read_bool(dev,
916 "snps,is-utmi-l1-suspend");
917 tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
919 hird_threshold = *tmp;
921 dwc->disable_scramble_quirk = dev_read_bool(dev,
922 "snps,disable_scramble_quirk");
923 dwc->u2exit_lfps_quirk = dev_read_bool(dev,
924 "snps,u2exit_lfps_quirk");
925 dwc->u2ss_inp3_quirk = dev_read_bool(dev,
926 "snps,u2ss_inp3_quirk");
927 dwc->req_p1p2p3_quirk = dev_read_bool(dev,
928 "snps,req_p1p2p3_quirk");
929 dwc->del_p1p2p3_quirk = dev_read_bool(dev,
930 "snps,del_p1p2p3_quirk");
931 dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
932 "snps,del_phy_power_chg_quirk");
933 dwc->lfps_filter_quirk = dev_read_bool(dev,
934 "snps,lfps_filter_quirk");
935 dwc->rx_detect_poll_quirk = dev_read_bool(dev,
936 "snps,rx_detect_poll_quirk");
937 dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
938 "snps,dis_u3_susphy_quirk");
939 dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
940 "snps,dis_u2_susphy_quirk");
941 dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
942 "snps,dis-del-phy-power-chg-quirk");
943 dwc->dis_tx_ipgap_linecheck_quirk = dev_read_bool(dev,
944 "snps,dis-tx-ipgap-linecheck-quirk");
945 dwc->dis_enblslpm_quirk = dev_read_bool(dev,
946 "snps,dis_enblslpm_quirk");
947 dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev,
948 "snps,dis-u2-freeclk-exists-quirk");
949 dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
950 "snps,tx_de_emphasis_quirk");
951 tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
953 tx_de_emphasis = *tmp;
955 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
956 dwc->tx_de_emphasis = tx_de_emphasis;
958 dwc->hird_threshold = hird_threshold
959 | (dwc->is_utmi_l1_suspend << 4);
962 int dwc3_init(struct dwc3 *dwc)
967 dwc3_cache_hwparams(dwc);
969 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
971 dev_err(dwc->dev, "failed to allocate event buffers\n");
975 ret = dwc3_core_init(dwc);
977 dev_err(dev, "failed to initialize core\n");
981 ret = dwc3_event_buffers_setup(dwc);
983 dev_err(dwc->dev, "failed to setup event buffers\n");
987 if (dwc->revision >= DWC3_REVISION_250A) {
988 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
991 * Enable hardware control of sending remote wakeup
992 * in HS when the device is in the L1 state.
994 if (dwc->revision >= DWC3_REVISION_290A)
995 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
997 if (dwc->dis_tx_ipgap_linecheck_quirk)
998 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1000 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1003 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1004 dwc->dr_mode == USB_DR_MODE_OTG) {
1005 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1007 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1009 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1012 ret = dwc3_core_init_mode(dwc);
1019 dwc3_event_buffers_cleanup(dwc);
1022 dwc3_core_exit(dwc);
1025 dwc3_free_event_buffers(dwc);
1030 void dwc3_remove(struct dwc3 *dwc)
1032 dwc3_core_exit_mode(dwc);
1033 dwc3_event_buffers_cleanup(dwc);
1034 dwc3_free_event_buffers(dwc);
1035 dwc3_core_exit(dwc);