1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - DesignWare USB3 DRD Controller Core file
5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
13 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
19 #include <dwc3-uboot.h>
20 #include <asm/dma-mapping.h>
21 #include <linux/ioport.h>
23 #include <generic-phy.h>
24 #include <linux/usb/ch9.h>
25 #include <linux/usb/gadget.h>
31 #include "linux-compat.h"
33 static LIST_HEAD(dwc3_list);
34 /* -------------------------------------------------------------------------- */
36 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
40 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
41 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
42 reg |= DWC3_GCTL_PRTCAPDIR(mode);
43 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
47 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
48 * @dwc: pointer to our context structure
50 static int dwc3_core_soft_reset(struct dwc3 *dwc)
54 /* Before Resetting PHY, put Core in Reset */
55 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
56 reg |= DWC3_GCTL_CORESOFTRESET;
57 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
59 /* Assert USB3 PHY reset */
60 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
61 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
62 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
64 /* Assert USB2 PHY reset */
65 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
66 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
67 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
71 /* Clear USB3 PHY reset */
72 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
73 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
74 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
76 /* Clear USB2 PHY reset */
77 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
78 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
79 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
83 /* After PHYs are stable we can take Core out of reset state */
84 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
85 reg &= ~DWC3_GCTL_CORESOFTRESET;
86 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
92 * dwc3_free_one_event_buffer - Frees one event buffer
93 * @dwc: Pointer to our controller context structure
94 * @evt: Pointer to event buffer to be freed
96 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
97 struct dwc3_event_buffer *evt)
99 dma_free_coherent(evt->buf);
103 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
104 * @dwc: Pointer to our controller context structure
105 * @length: size of the event buffer
107 * Returns a pointer to the allocated event buffer structure on success
108 * otherwise ERR_PTR(errno).
110 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
113 struct dwc3_event_buffer *evt;
115 evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
118 return ERR_PTR(-ENOMEM);
121 evt->length = length;
122 evt->buf = dma_alloc_coherent(length,
123 (unsigned long *)&evt->dma);
125 return ERR_PTR(-ENOMEM);
127 dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
133 * dwc3_free_event_buffers - frees all allocated event buffers
134 * @dwc: Pointer to our controller context structure
136 static void dwc3_free_event_buffers(struct dwc3 *dwc)
138 struct dwc3_event_buffer *evt;
141 for (i = 0; i < dwc->num_event_buffers; i++) {
142 evt = dwc->ev_buffs[i];
144 dwc3_free_one_event_buffer(dwc, evt);
149 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
150 * @dwc: pointer to our controller context structure
151 * @length: size of event buffer
153 * Returns 0 on success otherwise negative errno. In the error case, dwc
154 * may contain some buffers allocated but not all which were requested.
156 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
161 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
162 dwc->num_event_buffers = num;
164 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
165 sizeof(*dwc->ev_buffs) * num);
169 for (i = 0; i < num; i++) {
170 struct dwc3_event_buffer *evt;
172 evt = dwc3_alloc_one_event_buffer(dwc, length);
174 dev_err(dwc->dev, "can't allocate event buffer\n");
177 dwc->ev_buffs[i] = evt;
184 * dwc3_event_buffers_setup - setup our allocated event buffers
185 * @dwc: pointer to our controller context structure
187 * Returns 0 on success otherwise negative errno.
189 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
191 struct dwc3_event_buffer *evt;
194 for (n = 0; n < dwc->num_event_buffers; n++) {
195 evt = dwc->ev_buffs[n];
196 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
197 evt->buf, (unsigned long long) evt->dma,
202 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
203 lower_32_bits(evt->dma));
204 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
205 upper_32_bits(evt->dma));
206 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
207 DWC3_GEVNTSIZ_SIZE(evt->length));
208 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
214 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
216 struct dwc3_event_buffer *evt;
219 for (n = 0; n < dwc->num_event_buffers; n++) {
220 evt = dwc->ev_buffs[n];
224 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
225 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
226 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
227 | DWC3_GEVNTSIZ_SIZE(0));
228 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
232 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
234 if (!dwc->has_hibernation)
237 if (!dwc->nr_scratch)
240 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
241 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
242 if (!dwc->scratchbuf)
248 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
250 dma_addr_t scratch_addr;
254 if (!dwc->has_hibernation)
257 if (!dwc->nr_scratch)
260 scratch_addr = dma_map_single(dwc->scratchbuf,
261 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
263 if (dma_mapping_error(dwc->dev, scratch_addr)) {
264 dev_err(dwc->dev, "failed to map scratch buffer\n");
269 dwc->scratch_addr = scratch_addr;
271 param = lower_32_bits(scratch_addr);
273 ret = dwc3_send_gadget_generic_command(dwc,
274 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
278 param = upper_32_bits(scratch_addr);
280 ret = dwc3_send_gadget_generic_command(dwc,
281 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
288 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
289 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
295 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
297 if (!dwc->has_hibernation)
300 if (!dwc->nr_scratch)
303 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
304 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
305 kfree(dwc->scratchbuf);
308 static void dwc3_core_num_eps(struct dwc3 *dwc)
310 struct dwc3_hwparams *parms = &dwc->hwparams;
312 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
313 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
315 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
316 dwc->num_in_eps, dwc->num_out_eps);
319 static void dwc3_cache_hwparams(struct dwc3 *dwc)
321 struct dwc3_hwparams *parms = &dwc->hwparams;
323 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
324 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
325 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
326 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
327 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
328 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
329 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
330 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
331 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
335 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
336 * @dwc: Pointer to our controller context structure
338 static void dwc3_phy_setup(struct dwc3 *dwc)
342 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
345 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
346 * to '0' during coreConsultant configuration. So default value
347 * will be '0' when the core is reset. Application needs to set it
348 * to '1' after the core initialization is completed.
350 if (dwc->revision > DWC3_REVISION_194A)
351 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
353 if (dwc->u2ss_inp3_quirk)
354 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
356 if (dwc->req_p1p2p3_quirk)
357 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
359 if (dwc->del_p1p2p3_quirk)
360 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
362 if (dwc->del_phy_power_chg_quirk)
363 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
365 if (dwc->lfps_filter_quirk)
366 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
368 if (dwc->rx_detect_poll_quirk)
369 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
371 if (dwc->tx_de_emphasis_quirk)
372 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
374 if (dwc->dis_u3_susphy_quirk)
375 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
377 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
381 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
384 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
385 * '0' during coreConsultant configuration. So default value will
386 * be '0' when the core is reset. Application needs to set it to
387 * '1' after the core initialization is completed.
389 if (dwc->revision > DWC3_REVISION_194A)
390 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
392 if (dwc->dis_u2_susphy_quirk)
393 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
395 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
401 * dwc3_core_init - Low-level initialization of DWC3 Core
402 * @dwc: Pointer to our controller context structure
404 * Returns 0 on success otherwise negative errno.
406 static int dwc3_core_init(struct dwc3 *dwc)
408 unsigned long timeout;
409 u32 hwparams4 = dwc->hwparams.hwparams4;
413 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
414 /* This should read as U3 followed by revision number */
415 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
416 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
422 /* Handle USB2.0-only core configuration */
423 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
424 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
425 if (dwc->maximum_speed == USB_SPEED_SUPER)
426 dwc->maximum_speed = USB_SPEED_HIGH;
429 /* issue device SoftReset too */
431 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
433 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
434 if (!(reg & DWC3_DCTL_CSFTRST))
439 dev_err(dwc->dev, "Reset Timed Out\n");
446 ret = dwc3_core_soft_reset(dwc);
450 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
451 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
453 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
454 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
456 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
457 * issue which would cause xHCI compliance tests to fail.
459 * Because of that we cannot enable clock gating on such
464 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
467 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
468 dwc->dr_mode == USB_DR_MODE_OTG) &&
469 (dwc->revision >= DWC3_REVISION_210A &&
470 dwc->revision <= DWC3_REVISION_250A))
471 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
473 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
475 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
476 /* enable hibernation here */
477 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
480 * REVISIT Enabling this bit so that host-mode hibernation
481 * will work. Device-mode hibernation is not yet implemented.
483 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
486 dev_dbg(dwc->dev, "No power optimization available\n");
489 /* check if current dwc3 is on simulation board */
490 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
491 dev_dbg(dwc->dev, "it is on FPGA board\n");
495 if(dwc->disable_scramble_quirk && !dwc->is_fpga)
497 "disable_scramble cannot be used on non-FPGA builds\n");
499 if (dwc->disable_scramble_quirk && dwc->is_fpga)
500 reg |= DWC3_GCTL_DISSCRAMBLE;
502 reg &= ~DWC3_GCTL_DISSCRAMBLE;
504 if (dwc->u2exit_lfps_quirk)
505 reg |= DWC3_GCTL_U2EXIT_LFPS;
508 * WORKAROUND: DWC3 revisions <1.90a have a bug
509 * where the device can fail to connect at SuperSpeed
510 * and falls back to high-speed mode which causes
511 * the device to enter a Connect/Disconnect loop
513 if (dwc->revision < DWC3_REVISION_190A)
514 reg |= DWC3_GCTL_U2RSTECN;
516 dwc3_core_num_eps(dwc);
518 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
520 ret = dwc3_alloc_scratch_buffers(dwc);
524 ret = dwc3_setup_scratch_buffers(dwc);
531 dwc3_free_scratch_buffers(dwc);
537 static void dwc3_core_exit(struct dwc3 *dwc)
539 dwc3_free_scratch_buffers(dwc);
542 static int dwc3_core_init_mode(struct dwc3 *dwc)
546 switch (dwc->dr_mode) {
547 case USB_DR_MODE_PERIPHERAL:
548 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
549 ret = dwc3_gadget_init(dwc);
551 dev_err(dev, "failed to initialize gadget\n");
555 case USB_DR_MODE_HOST:
556 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
557 ret = dwc3_host_init(dwc);
559 dev_err(dev, "failed to initialize host\n");
563 case USB_DR_MODE_OTG:
564 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
565 ret = dwc3_host_init(dwc);
567 dev_err(dev, "failed to initialize host\n");
571 ret = dwc3_gadget_init(dwc);
573 dev_err(dev, "failed to initialize gadget\n");
578 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
585 static void dwc3_gadget_run(struct dwc3 *dwc)
587 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
591 static void dwc3_core_exit_mode(struct dwc3 *dwc)
593 switch (dwc->dr_mode) {
594 case USB_DR_MODE_PERIPHERAL:
595 dwc3_gadget_exit(dwc);
597 case USB_DR_MODE_HOST:
600 case USB_DR_MODE_OTG:
602 dwc3_gadget_exit(dwc);
610 * switch back to peripheral mode
611 * This enables the phy to enter idle and then, if enabled, suspend.
613 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
614 dwc3_gadget_run(dwc);
617 static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
620 enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode;
623 /* Set dwc3 usb2 phy config */
624 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
626 switch (hsphy_mode) {
627 case USBPHY_INTERFACE_MODE_UTMI:
628 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
629 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
630 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
631 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
633 case USBPHY_INTERFACE_MODE_UTMIW:
634 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
635 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
636 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
637 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
643 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
646 #define DWC3_ALIGN_MASK (16 - 1)
649 * dwc3_uboot_init - dwc3 core uboot initialization code
650 * @dwc3_dev: struct dwc3_device containing initialization data
652 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
653 * kernel driver). Pointer to dwc3_device should be passed containing
654 * base address and other initialization data. Returns '0' on success and
655 * a negative value on failure.
657 * Generally called from board_usb_init() implemented in board file.
659 int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
662 struct device *dev = NULL;
663 u8 lpm_nyet_threshold;
671 mem = devm_kzalloc((struct udevice *)dev,
672 sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
676 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
679 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
680 DWC3_GLOBALS_REGS_START);
682 /* default to highest possible threshold */
683 lpm_nyet_threshold = 0xff;
685 /* default to -3.5dB de-emphasis */
689 * default to assert utmi_sleep_n and use maximum allowed HIRD
690 * threshold value of 0b1100
694 dwc->maximum_speed = dwc3_dev->maximum_speed;
695 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
696 if (dwc3_dev->lpm_nyet_threshold)
697 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
698 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
699 if (dwc3_dev->hird_threshold)
700 hird_threshold = dwc3_dev->hird_threshold;
702 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
703 dwc->dr_mode = dwc3_dev->dr_mode;
705 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
706 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
707 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
708 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
709 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
710 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
711 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
712 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
713 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
714 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
716 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
717 if (dwc3_dev->tx_de_emphasis)
718 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
720 /* default to superspeed if no maximum_speed passed */
721 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
722 dwc->maximum_speed = USB_SPEED_SUPER;
724 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
725 dwc->tx_de_emphasis = tx_de_emphasis;
727 dwc->hird_threshold = hird_threshold
728 | (dwc->is_utmi_l1_suspend << 4);
730 dwc->index = dwc3_dev->index;
732 dwc3_cache_hwparams(dwc);
734 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
736 dev_err(dwc->dev, "failed to allocate event buffers\n");
740 if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
741 dwc->dr_mode = USB_DR_MODE_HOST;
742 else if (!IS_ENABLED(CONFIG_USB_HOST))
743 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
745 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
746 dwc->dr_mode = USB_DR_MODE_OTG;
748 ret = dwc3_core_init(dwc);
750 dev_err(dev, "failed to initialize core\n");
754 dwc3_uboot_hsphy_mode(dwc3_dev, dwc);
756 ret = dwc3_event_buffers_setup(dwc);
758 dev_err(dwc->dev, "failed to setup event buffers\n");
762 ret = dwc3_core_init_mode(dwc);
766 list_add_tail(&dwc->list, &dwc3_list);
771 dwc3_event_buffers_cleanup(dwc);
777 dwc3_free_event_buffers(dwc);
783 * dwc3_uboot_exit - dwc3 core uboot cleanup code
784 * @index: index of this controller
786 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
787 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
788 * should be passed and should match with the index passed in
789 * dwc3_device during init.
791 * Generally called from board file.
793 void dwc3_uboot_exit(int index)
797 list_for_each_entry(dwc, &dwc3_list, list) {
798 if (dwc->index != index)
801 dwc3_core_exit_mode(dwc);
802 dwc3_event_buffers_cleanup(dwc);
803 dwc3_free_event_buffers(dwc);
805 list_del(&dwc->list);
812 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
813 * @index: index of this controller
815 * Invokes dwc3 gadget interrupts.
817 * Generally called from board file.
819 void dwc3_uboot_handle_interrupt(int index)
821 struct dwc3 *dwc = NULL;
823 list_for_each_entry(dwc, &dwc3_list, list) {
824 if (dwc->index != index)
827 dwc3_gadget_uboot_handle_interrupt(dwc);
832 MODULE_ALIAS("platform:dwc3");
833 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
834 MODULE_LICENSE("GPL v2");
835 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
837 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
838 int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys)
841 struct phy *usb_phys;
843 /* Return if no phy declared */
844 if (!dev_read_prop(dev, "phys", NULL))
846 count = dev_count_phandle_with_args(dev, "phys", "#phy-cells");
850 usb_phys = devm_kcalloc(dev, count, sizeof(struct phy),
855 for (i = 0; i < count; i++) {
856 ret = generic_phy_get_by_index(dev, i, &usb_phys[i]);
857 if (ret && ret != -ENOENT) {
858 pr_err("Failed to get USB PHY%d for %s\n",
864 for (i = 0; i < count; i++) {
865 ret = generic_phy_init(&usb_phys[i]);
867 pr_err("Can't init USB PHY%d for %s\n",
873 for (i = 0; i < count; i++) {
874 ret = generic_phy_power_on(&usb_phys[i]);
876 pr_err("Can't power USB PHY%d for %s\n",
878 goto phys_poweron_err;
887 for (i = count - 1; i >= 0; i--)
888 generic_phy_power_off(&usb_phys[i]);
890 for (i = 0; i < count; i++)
891 generic_phy_exit(&usb_phys[i]);
897 generic_phy_exit(&usb_phys[i]);
902 int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys)
906 for (i = 0; i < num_phys; i++) {
907 if (!generic_phy_valid(&usb_phys[i]))
910 ret = generic_phy_power_off(&usb_phys[i]);
911 ret |= generic_phy_exit(&usb_phys[i]);
913 pr_err("Can't shutdown USB PHY%d for %s\n",
922 #if CONFIG_IS_ENABLED(DM_USB)
923 void dwc3_of_parse(struct dwc3 *dwc)
926 struct udevice *dev = dwc->dev;
927 u8 lpm_nyet_threshold;
931 /* default to highest possible threshold */
932 lpm_nyet_threshold = 0xff;
934 /* default to -3.5dB de-emphasis */
938 * default to assert utmi_sleep_n and use maximum allowed HIRD
939 * threshold value of 0b1100
943 dwc->has_lpm_erratum = dev_read_bool(dev,
944 "snps,has-lpm-erratum");
945 tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
947 lpm_nyet_threshold = *tmp;
949 dwc->is_utmi_l1_suspend = dev_read_bool(dev,
950 "snps,is-utmi-l1-suspend");
951 tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
953 hird_threshold = *tmp;
955 dwc->disable_scramble_quirk = dev_read_bool(dev,
956 "snps,disable_scramble_quirk");
957 dwc->u2exit_lfps_quirk = dev_read_bool(dev,
958 "snps,u2exit_lfps_quirk");
959 dwc->u2ss_inp3_quirk = dev_read_bool(dev,
960 "snps,u2ss_inp3_quirk");
961 dwc->req_p1p2p3_quirk = dev_read_bool(dev,
962 "snps,req_p1p2p3_quirk");
963 dwc->del_p1p2p3_quirk = dev_read_bool(dev,
964 "snps,del_p1p2p3_quirk");
965 dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
966 "snps,del_phy_power_chg_quirk");
967 dwc->lfps_filter_quirk = dev_read_bool(dev,
968 "snps,lfps_filter_quirk");
969 dwc->rx_detect_poll_quirk = dev_read_bool(dev,
970 "snps,rx_detect_poll_quirk");
971 dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
972 "snps,dis_u3_susphy_quirk");
973 dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
974 "snps,dis_u2_susphy_quirk");
975 dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
976 "snps,tx_de_emphasis_quirk");
977 tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
979 tx_de_emphasis = *tmp;
981 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
982 dwc->tx_de_emphasis = tx_de_emphasis;
984 dwc->hird_threshold = hird_threshold
985 | (dwc->is_utmi_l1_suspend << 4);
988 int dwc3_init(struct dwc3 *dwc)
992 dwc3_cache_hwparams(dwc);
994 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
996 dev_err(dwc->dev, "failed to allocate event buffers\n");
1000 ret = dwc3_core_init(dwc);
1002 dev_err(dev, "failed to initialize core\n");
1006 ret = dwc3_event_buffers_setup(dwc);
1008 dev_err(dwc->dev, "failed to setup event buffers\n");
1012 ret = dwc3_core_init_mode(dwc);
1019 dwc3_event_buffers_cleanup(dwc);
1022 dwc3_core_exit(dwc);
1025 dwc3_free_event_buffers(dwc);
1030 void dwc3_remove(struct dwc3 *dwc)
1032 dwc3_core_exit_mode(dwc);
1033 dwc3_event_buffers_cleanup(dwc);
1034 dwc3_free_event_buffers(dwc);
1035 dwc3_core_exit(dwc);