1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - DesignWare USB3 DRD Controller Core file
5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
13 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
19 #include <dwc3-uboot.h>
20 #include <dm/device_compat.h>
21 #include <dm/devres.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/err.h>
24 #include <linux/ioport.h>
26 #include <generic-phy.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
34 #include "linux-compat.h"
36 static LIST_HEAD(dwc3_list);
37 /* -------------------------------------------------------------------------- */
39 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
43 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
44 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
45 reg |= DWC3_GCTL_PRTCAPDIR(mode);
46 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
50 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
51 * @dwc: pointer to our context structure
53 static int dwc3_core_soft_reset(struct dwc3 *dwc)
57 /* Before Resetting PHY, put Core in Reset */
58 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
59 reg |= DWC3_GCTL_CORESOFTRESET;
60 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
62 /* Assert USB3 PHY reset */
63 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
64 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
65 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
67 /* Assert USB2 PHY reset */
68 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
69 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
70 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
74 /* Clear USB3 PHY reset */
75 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
76 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
77 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
79 /* Clear USB2 PHY reset */
80 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
81 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
82 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
86 /* After PHYs are stable we can take Core out of reset state */
87 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
88 reg &= ~DWC3_GCTL_CORESOFTRESET;
89 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
95 * dwc3_free_one_event_buffer - Frees one event buffer
96 * @dwc: Pointer to our controller context structure
97 * @evt: Pointer to event buffer to be freed
99 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
100 struct dwc3_event_buffer *evt)
102 dma_free_coherent(evt->buf);
106 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
107 * @dwc: Pointer to our controller context structure
108 * @length: size of the event buffer
110 * Returns a pointer to the allocated event buffer structure on success
111 * otherwise ERR_PTR(errno).
113 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
116 struct dwc3_event_buffer *evt;
118 evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
121 return ERR_PTR(-ENOMEM);
124 evt->length = length;
125 evt->buf = dma_alloc_coherent(length,
126 (unsigned long *)&evt->dma);
128 return ERR_PTR(-ENOMEM);
130 dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
136 * dwc3_free_event_buffers - frees all allocated event buffers
137 * @dwc: Pointer to our controller context structure
139 static void dwc3_free_event_buffers(struct dwc3 *dwc)
141 struct dwc3_event_buffer *evt;
144 for (i = 0; i < dwc->num_event_buffers; i++) {
145 evt = dwc->ev_buffs[i];
147 dwc3_free_one_event_buffer(dwc, evt);
152 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
153 * @dwc: pointer to our controller context structure
154 * @length: size of event buffer
156 * Returns 0 on success otherwise negative errno. In the error case, dwc
157 * may contain some buffers allocated but not all which were requested.
159 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
164 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
165 dwc->num_event_buffers = num;
167 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
168 sizeof(*dwc->ev_buffs) * num);
172 for (i = 0; i < num; i++) {
173 struct dwc3_event_buffer *evt;
175 evt = dwc3_alloc_one_event_buffer(dwc, length);
177 dev_err(dwc->dev, "can't allocate event buffer\n");
180 dwc->ev_buffs[i] = evt;
187 * dwc3_event_buffers_setup - setup our allocated event buffers
188 * @dwc: pointer to our controller context structure
190 * Returns 0 on success otherwise negative errno.
192 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
194 struct dwc3_event_buffer *evt;
197 for (n = 0; n < dwc->num_event_buffers; n++) {
198 evt = dwc->ev_buffs[n];
199 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
200 evt->buf, (unsigned long long) evt->dma,
205 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
206 lower_32_bits(evt->dma));
207 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
208 upper_32_bits(evt->dma));
209 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
210 DWC3_GEVNTSIZ_SIZE(evt->length));
211 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
217 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
219 struct dwc3_event_buffer *evt;
222 for (n = 0; n < dwc->num_event_buffers; n++) {
223 evt = dwc->ev_buffs[n];
227 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
228 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
229 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
230 | DWC3_GEVNTSIZ_SIZE(0));
231 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
235 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
237 if (!dwc->has_hibernation)
240 if (!dwc->nr_scratch)
243 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
244 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
245 if (!dwc->scratchbuf)
251 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
253 dma_addr_t scratch_addr;
257 if (!dwc->has_hibernation)
260 if (!dwc->nr_scratch)
263 scratch_addr = dma_map_single(dwc->scratchbuf,
264 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
266 if (dma_mapping_error(dwc->dev, scratch_addr)) {
267 dev_err(dwc->dev, "failed to map scratch buffer\n");
272 dwc->scratch_addr = scratch_addr;
274 param = lower_32_bits(scratch_addr);
276 ret = dwc3_send_gadget_generic_command(dwc,
277 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
281 param = upper_32_bits(scratch_addr);
283 ret = dwc3_send_gadget_generic_command(dwc,
284 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
291 dma_unmap_single(scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
298 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
300 if (!dwc->has_hibernation)
303 if (!dwc->nr_scratch)
306 dma_unmap_single(dwc->scratch_addr, dwc->nr_scratch *
307 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
308 kfree(dwc->scratchbuf);
311 static void dwc3_core_num_eps(struct dwc3 *dwc)
313 struct dwc3_hwparams *parms = &dwc->hwparams;
315 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
316 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
318 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
319 dwc->num_in_eps, dwc->num_out_eps);
322 static void dwc3_cache_hwparams(struct dwc3 *dwc)
324 struct dwc3_hwparams *parms = &dwc->hwparams;
326 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
327 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
328 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
329 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
330 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
331 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
332 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
333 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
334 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
338 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
339 * @dwc: Pointer to our controller context structure
341 static void dwc3_phy_setup(struct dwc3 *dwc)
345 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
348 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
349 * to '0' during coreConsultant configuration. So default value
350 * will be '0' when the core is reset. Application needs to set it
351 * to '1' after the core initialization is completed.
353 if (dwc->revision > DWC3_REVISION_194A)
354 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
356 if (dwc->u2ss_inp3_quirk)
357 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
359 if (dwc->req_p1p2p3_quirk)
360 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
362 if (dwc->del_p1p2p3_quirk)
363 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
365 if (dwc->del_phy_power_chg_quirk)
366 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
368 if (dwc->lfps_filter_quirk)
369 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
371 if (dwc->rx_detect_poll_quirk)
372 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
374 if (dwc->tx_de_emphasis_quirk)
375 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
377 if (dwc->dis_u3_susphy_quirk)
378 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
380 if (dwc->dis_del_phy_power_chg_quirk)
381 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
383 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
387 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
390 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
391 * '0' during coreConsultant configuration. So default value will
392 * be '0' when the core is reset. Application needs to set it to
393 * '1' after the core initialization is completed.
395 if (dwc->revision > DWC3_REVISION_194A)
396 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
398 if (dwc->dis_u2_susphy_quirk)
399 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
401 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
407 * dwc3_core_init - Low-level initialization of DWC3 Core
408 * @dwc: Pointer to our controller context structure
410 * Returns 0 on success otherwise negative errno.
412 static int dwc3_core_init(struct dwc3 *dwc)
414 unsigned long timeout;
415 u32 hwparams4 = dwc->hwparams.hwparams4;
419 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
420 /* This should read as U3 followed by revision number */
421 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
422 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
428 /* Handle USB2.0-only core configuration */
429 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
430 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
431 if (dwc->maximum_speed == USB_SPEED_SUPER)
432 dwc->maximum_speed = USB_SPEED_HIGH;
435 /* issue device SoftReset too */
437 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
439 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
440 if (!(reg & DWC3_DCTL_CSFTRST))
445 dev_err(dwc->dev, "Reset Timed Out\n");
452 ret = dwc3_core_soft_reset(dwc);
456 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
457 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
459 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
460 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
462 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
463 * issue which would cause xHCI compliance tests to fail.
465 * Because of that we cannot enable clock gating on such
470 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
473 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
474 dwc->dr_mode == USB_DR_MODE_OTG) &&
475 (dwc->revision >= DWC3_REVISION_210A &&
476 dwc->revision <= DWC3_REVISION_250A))
477 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
479 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
481 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
482 /* enable hibernation here */
483 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
486 * REVISIT Enabling this bit so that host-mode hibernation
487 * will work. Device-mode hibernation is not yet implemented.
489 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
492 dev_dbg(dwc->dev, "No power optimization available\n");
495 /* check if current dwc3 is on simulation board */
496 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
497 dev_dbg(dwc->dev, "it is on FPGA board\n");
501 if(dwc->disable_scramble_quirk && !dwc->is_fpga)
503 "disable_scramble cannot be used on non-FPGA builds\n");
505 if (dwc->disable_scramble_quirk && dwc->is_fpga)
506 reg |= DWC3_GCTL_DISSCRAMBLE;
508 reg &= ~DWC3_GCTL_DISSCRAMBLE;
510 if (dwc->u2exit_lfps_quirk)
511 reg |= DWC3_GCTL_U2EXIT_LFPS;
514 * WORKAROUND: DWC3 revisions <1.90a have a bug
515 * where the device can fail to connect at SuperSpeed
516 * and falls back to high-speed mode which causes
517 * the device to enter a Connect/Disconnect loop
519 if (dwc->revision < DWC3_REVISION_190A)
520 reg |= DWC3_GCTL_U2RSTECN;
522 dwc3_core_num_eps(dwc);
524 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
526 ret = dwc3_alloc_scratch_buffers(dwc);
530 ret = dwc3_setup_scratch_buffers(dwc);
537 dwc3_free_scratch_buffers(dwc);
543 static void dwc3_core_exit(struct dwc3 *dwc)
545 dwc3_free_scratch_buffers(dwc);
548 static int dwc3_core_init_mode(struct dwc3 *dwc)
552 switch (dwc->dr_mode) {
553 case USB_DR_MODE_PERIPHERAL:
554 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
555 ret = dwc3_gadget_init(dwc);
557 dev_err(dev, "failed to initialize gadget\n");
561 case USB_DR_MODE_HOST:
562 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
563 ret = dwc3_host_init(dwc);
565 dev_err(dev, "failed to initialize host\n");
569 case USB_DR_MODE_OTG:
570 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
571 ret = dwc3_host_init(dwc);
573 dev_err(dev, "failed to initialize host\n");
577 ret = dwc3_gadget_init(dwc);
579 dev_err(dev, "failed to initialize gadget\n");
584 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
591 static void dwc3_gadget_run(struct dwc3 *dwc)
593 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
597 static void dwc3_core_exit_mode(struct dwc3 *dwc)
599 switch (dwc->dr_mode) {
600 case USB_DR_MODE_PERIPHERAL:
601 dwc3_gadget_exit(dwc);
603 case USB_DR_MODE_HOST:
606 case USB_DR_MODE_OTG:
608 dwc3_gadget_exit(dwc);
616 * switch back to peripheral mode
617 * This enables the phy to enter idle and then, if enabled, suspend.
619 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
620 dwc3_gadget_run(dwc);
623 static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
626 enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode;
629 /* Set dwc3 usb2 phy config */
630 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
632 switch (hsphy_mode) {
633 case USBPHY_INTERFACE_MODE_UTMI:
634 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
635 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
636 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
637 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
639 case USBPHY_INTERFACE_MODE_UTMIW:
640 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
641 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
642 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
643 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
649 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
652 #define DWC3_ALIGN_MASK (16 - 1)
655 * dwc3_uboot_init - dwc3 core uboot initialization code
656 * @dwc3_dev: struct dwc3_device containing initialization data
658 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
659 * kernel driver). Pointer to dwc3_device should be passed containing
660 * base address and other initialization data. Returns '0' on success and
661 * a negative value on failure.
663 * Generally called from board_usb_init() implemented in board file.
665 int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
668 struct device *dev = NULL;
669 u8 lpm_nyet_threshold;
677 mem = devm_kzalloc((struct udevice *)dev,
678 sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
682 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
685 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
686 DWC3_GLOBALS_REGS_START);
688 /* default to highest possible threshold */
689 lpm_nyet_threshold = 0xff;
691 /* default to -3.5dB de-emphasis */
695 * default to assert utmi_sleep_n and use maximum allowed HIRD
696 * threshold value of 0b1100
700 dwc->maximum_speed = dwc3_dev->maximum_speed;
701 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
702 if (dwc3_dev->lpm_nyet_threshold)
703 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
704 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
705 if (dwc3_dev->hird_threshold)
706 hird_threshold = dwc3_dev->hird_threshold;
708 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
709 dwc->dr_mode = dwc3_dev->dr_mode;
711 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
712 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
713 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
714 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
715 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
716 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
717 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
718 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
719 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
720 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
721 dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
723 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
724 if (dwc3_dev->tx_de_emphasis)
725 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
727 /* default to superspeed if no maximum_speed passed */
728 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
729 dwc->maximum_speed = USB_SPEED_SUPER;
731 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
732 dwc->tx_de_emphasis = tx_de_emphasis;
734 dwc->hird_threshold = hird_threshold
735 | (dwc->is_utmi_l1_suspend << 4);
737 dwc->index = dwc3_dev->index;
739 dwc3_cache_hwparams(dwc);
741 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
743 dev_err(dwc->dev, "failed to allocate event buffers\n");
747 if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
748 dwc->dr_mode = USB_DR_MODE_HOST;
749 else if (!IS_ENABLED(CONFIG_USB_HOST))
750 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
752 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
753 dwc->dr_mode = USB_DR_MODE_OTG;
755 ret = dwc3_core_init(dwc);
757 dev_err(dev, "failed to initialize core\n");
761 dwc3_uboot_hsphy_mode(dwc3_dev, dwc);
763 ret = dwc3_event_buffers_setup(dwc);
765 dev_err(dwc->dev, "failed to setup event buffers\n");
769 ret = dwc3_core_init_mode(dwc);
773 list_add_tail(&dwc->list, &dwc3_list);
778 dwc3_event_buffers_cleanup(dwc);
784 dwc3_free_event_buffers(dwc);
790 * dwc3_uboot_exit - dwc3 core uboot cleanup code
791 * @index: index of this controller
793 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
794 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
795 * should be passed and should match with the index passed in
796 * dwc3_device during init.
798 * Generally called from board file.
800 void dwc3_uboot_exit(int index)
804 list_for_each_entry(dwc, &dwc3_list, list) {
805 if (dwc->index != index)
808 dwc3_core_exit_mode(dwc);
809 dwc3_event_buffers_cleanup(dwc);
810 dwc3_free_event_buffers(dwc);
812 list_del(&dwc->list);
819 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
820 * @index: index of this controller
822 * Invokes dwc3 gadget interrupts.
824 * Generally called from board file.
826 void dwc3_uboot_handle_interrupt(int index)
828 struct dwc3 *dwc = NULL;
830 list_for_each_entry(dwc, &dwc3_list, list) {
831 if (dwc->index != index)
834 dwc3_gadget_uboot_handle_interrupt(dwc);
839 MODULE_ALIAS("platform:dwc3");
840 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
841 MODULE_LICENSE("GPL v2");
842 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
844 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
845 int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys)
849 ret = generic_phy_get_bulk(dev, phys);
853 ret = generic_phy_init_bulk(phys);
857 ret = generic_phy_power_on_bulk(phys);
859 generic_phy_exit_bulk(phys);
864 int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys)
868 ret = generic_phy_power_off_bulk(phys);
869 ret |= generic_phy_exit_bulk(phys);
874 #if CONFIG_IS_ENABLED(DM_USB)
875 void dwc3_of_parse(struct dwc3 *dwc)
878 struct udevice *dev = dwc->dev;
879 u8 lpm_nyet_threshold;
883 /* default to highest possible threshold */
884 lpm_nyet_threshold = 0xff;
886 /* default to -3.5dB de-emphasis */
890 * default to assert utmi_sleep_n and use maximum allowed HIRD
891 * threshold value of 0b1100
895 dwc->has_lpm_erratum = dev_read_bool(dev,
896 "snps,has-lpm-erratum");
897 tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
899 lpm_nyet_threshold = *tmp;
901 dwc->is_utmi_l1_suspend = dev_read_bool(dev,
902 "snps,is-utmi-l1-suspend");
903 tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
905 hird_threshold = *tmp;
907 dwc->disable_scramble_quirk = dev_read_bool(dev,
908 "snps,disable_scramble_quirk");
909 dwc->u2exit_lfps_quirk = dev_read_bool(dev,
910 "snps,u2exit_lfps_quirk");
911 dwc->u2ss_inp3_quirk = dev_read_bool(dev,
912 "snps,u2ss_inp3_quirk");
913 dwc->req_p1p2p3_quirk = dev_read_bool(dev,
914 "snps,req_p1p2p3_quirk");
915 dwc->del_p1p2p3_quirk = dev_read_bool(dev,
916 "snps,del_p1p2p3_quirk");
917 dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
918 "snps,del_phy_power_chg_quirk");
919 dwc->lfps_filter_quirk = dev_read_bool(dev,
920 "snps,lfps_filter_quirk");
921 dwc->rx_detect_poll_quirk = dev_read_bool(dev,
922 "snps,rx_detect_poll_quirk");
923 dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
924 "snps,dis_u3_susphy_quirk");
925 dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
926 "snps,dis_u2_susphy_quirk");
927 dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
928 "snps,dis-del-phy-power-chg-quirk");
929 dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
930 "snps,tx_de_emphasis_quirk");
931 tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
933 tx_de_emphasis = *tmp;
935 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
936 dwc->tx_de_emphasis = tx_de_emphasis;
938 dwc->hird_threshold = hird_threshold
939 | (dwc->is_utmi_l1_suspend << 4);
942 int dwc3_init(struct dwc3 *dwc)
946 dwc3_cache_hwparams(dwc);
948 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
950 dev_err(dwc->dev, "failed to allocate event buffers\n");
954 ret = dwc3_core_init(dwc);
956 dev_err(dev, "failed to initialize core\n");
960 ret = dwc3_event_buffers_setup(dwc);
962 dev_err(dwc->dev, "failed to setup event buffers\n");
966 ret = dwc3_core_init_mode(dwc);
973 dwc3_event_buffers_cleanup(dwc);
979 dwc3_free_event_buffers(dwc);
984 void dwc3_remove(struct dwc3 *dwc)
986 dwc3_core_exit_mode(dwc);
987 dwc3_event_buffers_cleanup(dwc);
988 dwc3_free_event_buffers(dwc);