drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/acpi.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/reset.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32 #include <linux/usb/of.h>
  33 #include <linux/usb/otg.h>
  34
  35 #include "core.h"
  36 #include "gadget.h"
  37 #include "io.h"
  38
  39 #include "debug.h"
  40
  41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  42
  43 /**
  44  * dwc3_get_dr_mode - Validates and sets dr_mode
  45  * @dwc: pointer to our context structure
  46  */
  47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  48 {
  49         enum usb_dr_mode mode;
  50         struct device *dev = dwc->dev;
  51         unsigned int hw_mode;
  52
  53         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  54                 dwc->dr_mode = USB_DR_MODE_OTG;
  55
  56         mode = dwc->dr_mode;
  57         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  58
  59         switch (hw_mode) {
  60         case DWC3_GHWPARAMS0_MODE_GADGET:
  61                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  62                         dev_err(dev,
  63                                 "Controller does not support host mode.\n");
  64                         return -EINVAL;
  65                 }
  66                 mode = USB_DR_MODE_PERIPHERAL;
  67                 break;
  68         case DWC3_GHWPARAMS0_MODE_HOST:
  69                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  70                         dev_err(dev,
  71                                 "Controller does not support device mode.\n");
  72                         return -EINVAL;
  73                 }
  74                 mode = USB_DR_MODE_HOST;
  75                 break;
  76         default:
  77                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  78                         mode = USB_DR_MODE_HOST;
  79                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  80                         mode = USB_DR_MODE_PERIPHERAL;
  81
  82                 /*
  83                  * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
  84                  * mode. If the controller supports DRD but the dr_mode is not
  85                  * specified or set to OTG, then set the mode to peripheral.
  86                  */
  87                 if (mode == USB_DR_MODE_OTG &&
  88                     dwc->revision >= DWC3_REVISION_330A)
  89                         mode = USB_DR_MODE_PERIPHERAL;
  90         }
  91
  92         if (mode != dwc->dr_mode) {
  93                 dev_warn(dev,
  94                          "Configuration mismatch. dr_mode forced to %s\n",
  95                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
  96
  97                 dwc->dr_mode = mode;
  98         }
  99
 100         return 0;
 101 }
 102
 103 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 104 {
 105         u32 reg;
 106
 107         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 108         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 109         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 110         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 111
 112         dwc->current_dr_role = mode;
 113 }
 114
 115 static void __dwc3_set_mode(struct work_struct *work)
 116 {
 117         struct dwc3 *dwc = work_to_dwc(work);
 118         unsigned long flags;
 119         int ret;
 120
 121         if (dwc->dr_mode != USB_DR_MODE_OTG)
 122                 return;
 123
 124         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 125                 dwc3_otg_update(dwc, 0);
 126
 127         if (!dwc->desired_dr_role)
 128                 return;
 129
 130         if (dwc->desired_dr_role == dwc->current_dr_role)
 131                 return;
 132
 133         if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 134                 return;
 135
 136         switch (dwc->current_dr_role) {
 137         case DWC3_GCTL_PRTCAP_HOST:
 138                 dwc3_host_exit(dwc);
 139                 break;
 140         case DWC3_GCTL_PRTCAP_DEVICE:
 141                 dwc3_gadget_exit(dwc);
 142                 dwc3_event_buffers_cleanup(dwc);
 143                 break;
 144         case DWC3_GCTL_PRTCAP_OTG:
 145                 dwc3_otg_exit(dwc);
 146                 spin_lock_irqsave(&dwc->lock, flags);
 147                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 148                 spin_unlock_irqrestore(&dwc->lock, flags);
 149                 dwc3_otg_update(dwc, 1);
 150                 break;
 151         default:
 152                 break;
 153         }
 154
 155         spin_lock_irqsave(&dwc->lock, flags);
 156
 157         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 158
 159         spin_unlock_irqrestore(&dwc->lock, flags);
 160
 161         switch (dwc->desired_dr_role) {
 162         case DWC3_GCTL_PRTCAP_HOST:
 163                 ret = dwc3_host_init(dwc);
 164                 if (ret) {
 165                         dev_err(dwc->dev, "failed to initialize host\n");
 166                 } else {
 167                         if (dwc->usb2_phy)
 168                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 169                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 170                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 171                         phy_calibrate(dwc->usb2_generic_phy);
 172                 }
 173                 break;
 174         case DWC3_GCTL_PRTCAP_DEVICE:
 175                 dwc3_event_buffers_setup(dwc);
 176
 177                 if (dwc->usb2_phy)
 178                         otg_set_vbus(dwc->usb2_phy->otg, false);
 179                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 180                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 181
 182                 ret = dwc3_gadget_init(dwc);
 183                 if (ret)
 184                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 185                 break;
 186         case DWC3_GCTL_PRTCAP_OTG:
 187                 dwc3_otg_init(dwc);
 188                 dwc3_otg_update(dwc, 0);
 189                 break;
 190         default:
 191                 break;
 192         }
 193
 194 }
 195
 196 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 197 {
 198         unsigned long flags;
 199
 200         spin_lock_irqsave(&dwc->lock, flags);
 201         dwc->desired_dr_role = mode;
 202         spin_unlock_irqrestore(&dwc->lock, flags);
 203
 204         queue_work(system_freezable_wq, &dwc->drd_work);
 205 }
 206
 207 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 208 {
 209         struct dwc3             *dwc = dep->dwc;
 210         u32                     reg;
 211
 212         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 213                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 214                         DWC3_GDBGFIFOSPACE_TYPE(type));
 215
 216         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 217
 218         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 219 }
 220
 221 /**
 222  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 223  * @dwc: pointer to our context structure
 224  */
 225 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 226 {
 227         u32             reg;
 228         int             retries = 1000;
 229         int             ret;
 230
 231         usb_phy_init(dwc->usb2_phy);
 232         usb_phy_init(dwc->usb3_phy);
 233         ret = phy_init(dwc->usb2_generic_phy);
 234         if (ret < 0)
 235                 return ret;
 236
 237         ret = phy_init(dwc->usb3_generic_phy);
 238         if (ret < 0) {
 239                 phy_exit(dwc->usb2_generic_phy);
 240                 return ret;
 241         }
 242
 243         /*
 244          * We're resetting only the device side because, if we're in host mode,
 245          * XHCI driver will reset the host block. If dwc3 was configured for
 246          * host-only mode, then we can return early.
 247          */
 248         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 249                 return 0;
 250
 251         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 252         reg |= DWC3_DCTL_CSFTRST;
 253         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 254
 255         do {
 256                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 257                 if (!(reg & DWC3_DCTL_CSFTRST))
 258                         goto done;
 259
 260                 udelay(1);
 261         } while (--retries);
 262
 263         phy_exit(dwc->usb3_generic_phy);
 264         phy_exit(dwc->usb2_generic_phy);
 265
 266         return -ETIMEDOUT;
 267
 268 done:
 269         /*
 270          * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
 271          * we must wait at least 50ms before accessing the PHY domain
 272          * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
 273          */
 274         if (dwc3_is_usb31(dwc))
 275                 msleep(50);
 276
 277         return 0;
 278 }
 279
 280 static const struct clk_bulk_data dwc3_core_clks[] = {
 281         { .id = "ref" },
 282         { .id = "bus_early" },
 283         { .id = "suspend" },
 284 };
 285
 286 /*
 287  * dwc3_frame_length_adjustment - Adjusts frame length if required
 288  * @dwc3: Pointer to our controller context structure
 289  */
 290 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 291 {
 292         u32 reg;
 293         u32 dft;
 294
 295         if (dwc->revision < DWC3_REVISION_250A)
 296                 return;
 297
 298         if (dwc->fladj == 0)
 299                 return;
 300
 301         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 302         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 303         if (dft != dwc->fladj) {
 304                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 305                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 306                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 307         }
 308 }
 309
 310 /**
 311  * dwc3_free_one_event_buffer - Frees one event buffer
 312  * @dwc: Pointer to our controller context structure
 313  * @evt: Pointer to event buffer to be freed
 314  */
 315 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 316                 struct dwc3_event_buffer *evt)
 317 {
 318         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 319 }
 320
 321 /**
 322  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 323  * @dwc: Pointer to our controller context structure
 324  * @length: size of the event buffer
 325  *
 326  * Returns a pointer to the allocated event buffer structure on success
 327  * otherwise ERR_PTR(errno).
 328  */
 329 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 330                 unsigned length)
 331 {
 332         struct dwc3_event_buffer        *evt;
 333
 334         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 335         if (!evt)
 336                 return ERR_PTR(-ENOMEM);
 337
 338         evt->dwc        = dwc;
 339         evt->length     = length;
 340         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 341         if (!evt->cache)
 342                 return ERR_PTR(-ENOMEM);
 343
 344         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 345                         &evt->dma, GFP_KERNEL);
 346         if (!evt->buf)
 347                 return ERR_PTR(-ENOMEM);
 348
 349         return evt;
 350 }
 351
 352 /**
 353  * dwc3_free_event_buffers - frees all allocated event buffers
 354  * @dwc: Pointer to our controller context structure
 355  */
 356 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 357 {
 358         struct dwc3_event_buffer        *evt;
 359
 360         evt = dwc->ev_buf;
 361         if (evt)
 362                 dwc3_free_one_event_buffer(dwc, evt);
 363 }
 364
 365 /**
 366  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 367  * @dwc: pointer to our controller context structure
 368  * @length: size of event buffer
 369  *
 370  * Returns 0 on success otherwise negative errno. In the error case, dwc
 371  * may contain some buffers allocated but not all which were requested.
 372  */
 373 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 374 {
 375         struct dwc3_event_buffer *evt;
 376
 377         evt = dwc3_alloc_one_event_buffer(dwc, length);
 378         if (IS_ERR(evt)) {
 379                 dev_err(dwc->dev, "can't allocate event buffer\n");
 380                 return PTR_ERR(evt);
 381         }
 382         dwc->ev_buf = evt;
 383
 384         return 0;
 385 }
 386
 387 /**
 388  * dwc3_event_buffers_setup - setup our allocated event buffers
 389  * @dwc: pointer to our controller context structure
 390  *
 391  * Returns 0 on success otherwise negative errno.
 392  */
 393 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 394 {
 395         struct dwc3_event_buffer        *evt;
 396
 397         evt = dwc->ev_buf;
 398         evt->lpos = 0;
 399         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 400                         lower_32_bits(evt->dma));
 401         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 402                         upper_32_bits(evt->dma));
 403         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 404                         DWC3_GEVNTSIZ_SIZE(evt->length));
 405         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 406
 407         return 0;
 408 }
 409
 410 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 411 {
 412         struct dwc3_event_buffer        *evt;
 413
 414         evt = dwc->ev_buf;
 415
 416         evt->lpos = 0;
 417
 418         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 419         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 420         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 421                         | DWC3_GEVNTSIZ_SIZE(0));
 422         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 423 }
 424
 425 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 426 {
 427         if (!dwc->has_hibernation)
 428                 return 0;
 429
 430         if (!dwc->nr_scratch)
 431                 return 0;
 432
 433         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 434                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 435         if (!dwc->scratchbuf)
 436                 return -ENOMEM;
 437
 438         return 0;
 439 }
 440
 441 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 442 {
 443         dma_addr_t scratch_addr;
 444         u32 param;
 445         int ret;
 446
 447         if (!dwc->has_hibernation)
 448                 return 0;
 449
 450         if (!dwc->nr_scratch)
 451                 return 0;
 452
 453          /* should never fall here */
 454         if (!WARN_ON(dwc->scratchbuf))
 455                 return 0;
 456
 457         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 458                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 459                         DMA_BIDIRECTIONAL);
 460         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 461                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 462                 ret = -EFAULT;
 463                 goto err0;
 464         }
 465
 466         dwc->scratch_addr = scratch_addr;
 467
 468         param = lower_32_bits(scratch_addr);
 469
 470         ret = dwc3_send_gadget_generic_command(dwc,
 471                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 472         if (ret < 0)
 473                 goto err1;
 474
 475         param = upper_32_bits(scratch_addr);
 476
 477         ret = dwc3_send_gadget_generic_command(dwc,
 478                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 479         if (ret < 0)
 480                 goto err1;
 481
 482         return 0;
 483
 484 err1:
 485         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 486                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 487
 488 err0:
 489         return ret;
 490 }
 491
 492 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 493 {
 494         if (!dwc->has_hibernation)
 495                 return;
 496
 497         if (!dwc->nr_scratch)
 498                 return;
 499
 500          /* should never fall here */
 501         if (!WARN_ON(dwc->scratchbuf))
 502                 return;
 503
 504         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 505                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 506         kfree(dwc->scratchbuf);
 507 }
 508
 509 static void dwc3_core_num_eps(struct dwc3 *dwc)
 510 {
 511         struct dwc3_hwparams    *parms = &dwc->hwparams;
 512
 513         dwc->num_eps = DWC3_NUM_EPS(parms);
 514 }
 515
 516 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 517 {
 518         struct dwc3_hwparams    *parms = &dwc->hwparams;
 519
 520         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 521         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 522         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 523         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 524         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 525         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 526         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 527         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 528         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 529 }
 530
 531 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 532 {
 533         int intf;
 534         int ret = 0;
 535
 536         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 537
 538         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 539             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 540              dwc->hsphy_interface &&
 541              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 542                 ret = dwc3_ulpi_init(dwc);
 543
 544         return ret;
 545 }
 546
 547 /**
 548  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 549  * @dwc: Pointer to our controller context structure
 550  *
 551  * Returns 0 on success. The USB PHY interfaces are configured but not
 552  * initialized. The PHY interfaces and the PHYs get initialized together with
 553  * the core in dwc3_core_init.
 554  */
 555 static int dwc3_phy_setup(struct dwc3 *dwc)
 556 {
 557         u32 reg;
 558
 559         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 560
 561         /*
 562          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 563          * PHYs. Also, this bit is not supposed to be used in normal operation.
 564          */
 565         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 566
 567         /*
 568          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 569          * to '0' during coreConsultant configuration. So default value
 570          * will be '0' when the core is reset. Application needs to set it
 571          * to '1' after the core initialization is completed.
 572          */
 573         if (dwc->revision > DWC3_REVISION_194A)
 574                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 575
 576         if (dwc->u2ss_inp3_quirk)
 577                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 578
 579         if (dwc->dis_rxdet_inp3_quirk)
 580                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 581
 582         if (dwc->req_p1p2p3_quirk)
 583                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 584
 585         if (dwc->del_p1p2p3_quirk)
 586                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 587
 588         if (dwc->del_phy_power_chg_quirk)
 589                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 590
 591         if (dwc->lfps_filter_quirk)
 592                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 593
 594         if (dwc->rx_detect_poll_quirk)
 595                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 596
 597         if (dwc->tx_de_emphasis_quirk)
 598                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 599
 600         if (dwc->dis_u3_susphy_quirk)
 601                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 602
 603         if (dwc->dis_del_phy_power_chg_quirk)
 604                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 605
 606         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 607
 608         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 609
 610         /* Select the HS PHY interface */
 611         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 612         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 613                 if (dwc->hsphy_interface &&
 614                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 615                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 616                         break;
 617                 } else if (dwc->hsphy_interface &&
 618                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 619                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 620                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 621                 } else {
 622                         /* Relying on default value. */
 623                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 624                                 break;
 625                 }
 626                 /* FALLTHROUGH */
 627         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 628                 /* FALLTHROUGH */
 629         default:
 630                 break;
 631         }
 632
 633         switch (dwc->hsphy_mode) {
 634         case USBPHY_INTERFACE_MODE_UTMI:
 635                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 636                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 637                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 638                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 639                 break;
 640         case USBPHY_INTERFACE_MODE_UTMIW:
 641                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 642                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 643                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 644                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 645                 break;
 646         default:
 647                 break;
 648         }
 649
 650         /*
 651          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 652          * '0' during coreConsultant configuration. So default value will
 653          * be '0' when the core is reset. Application needs to set it to
 654          * '1' after the core initialization is completed.
 655          */
 656         if (dwc->revision > DWC3_REVISION_194A)
 657                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 658
 659         if (dwc->dis_u2_susphy_quirk)
 660                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 661
 662         if (dwc->dis_enblslpm_quirk)
 663                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 664         else
 665                 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 666
 667         if (dwc->dis_u2_freeclk_exists_quirk)
 668                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 669
 670         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 671
 672         return 0;
 673 }
 674
 675 static void dwc3_core_exit(struct dwc3 *dwc)
 676 {
 677         dwc3_event_buffers_cleanup(dwc);
 678
 679         usb_phy_shutdown(dwc->usb2_phy);
 680         usb_phy_shutdown(dwc->usb3_phy);
 681         phy_exit(dwc->usb2_generic_phy);
 682         phy_exit(dwc->usb3_generic_phy);
 683
 684         usb_phy_set_suspend(dwc->usb2_phy, 1);
 685         usb_phy_set_suspend(dwc->usb3_phy, 1);
 686         phy_power_off(dwc->usb2_generic_phy);
 687         phy_power_off(dwc->usb3_generic_phy);
 688         clk_bulk_disable(dwc->num_clks, dwc->clks);
 689         clk_bulk_unprepare(dwc->num_clks, dwc->clks);
 690         reset_control_assert(dwc->reset);
 691 }
 692
 693 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 694 {
 695         u32 reg;
 696
 697         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 698
 699         /* This should read as U3 followed by revision number */
 700         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 701                 /* Detected DWC_usb3 IP */
 702                 dwc->revision = reg;
 703         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 704                 /* Detected DWC_usb31 IP */
 705                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 706                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 707                 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
 708         } else {
 709                 return false;
 710         }
 711
 712         return true;
 713 }
 714
 715 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 716 {
 717         u32 hwparams4 = dwc->hwparams.hwparams4;
 718         u32 reg;
 719
 720         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 721         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 722
 723         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 724         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 725                 /**
 726                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 727                  * issue which would cause xHCI compliance tests to fail.
 728                  *
 729                  * Because of that we cannot enable clock gating on such
 730                  * configurations.
 731                  *
 732                  * Refers to:
 733                  *
 734                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 735                  * SOF/ITP Mode Used
 736                  */
 737                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 738                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 739                                 (dwc->revision >= DWC3_REVISION_210A &&
 740                                 dwc->revision <= DWC3_REVISION_250A))
 741                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 742                 else
 743                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 744                 break;
 745         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 746                 /* enable hibernation here */
 747                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 748
 749                 /*
 750                  * REVISIT Enabling this bit so that host-mode hibernation
 751                  * will work. Device-mode hibernation is not yet implemented.
 752                  */
 753                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 754                 break;
 755         default:
 756                 /* nothing */
 757                 break;
 758         }
 759
 760         /* check if current dwc3 is on simulation board */
 761         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 762                 dev_info(dwc->dev, "Running with FPGA optimizations\n");
 763                 dwc->is_fpga = true;
 764         }
 765
 766         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 767                         "disable_scramble cannot be used on non-FPGA builds\n");
 768
 769         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 770                 reg |= DWC3_GCTL_DISSCRAMBLE;
 771         else
 772                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 773
 774         if (dwc->u2exit_lfps_quirk)
 775                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 776
 777         /*
 778          * WORKAROUND: DWC3 revisions <1.90a have a bug
 779          * where the device can fail to connect at SuperSpeed
 780          * and falls back to high-speed mode which causes
 781          * the device to enter a Connect/Disconnect loop
 782          */
 783         if (dwc->revision < DWC3_REVISION_190A)
 784                 reg |= DWC3_GCTL_U2RSTECN;
 785
 786         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 787 }
 788
 789 static int dwc3_core_get_phy(struct dwc3 *dwc);
 790 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 791
 792 /* set global incr burst type configuration registers */
 793 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 794 {
 795         struct device *dev = dwc->dev;
 796         /* incrx_mode : for INCR burst type. */
 797         bool incrx_mode;
 798         /* incrx_size : for size of INCRX burst. */
 799         u32 incrx_size;
 800         u32 *vals;
 801         u32 cfg;
 802         int ntype;
 803         int ret;
 804         int i;
 805
 806         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 807
 808         /*
 809          * Handle property "snps,incr-burst-type-adjustment".
 810          * Get the number of value from this property:
 811          * result <= 0, means this property is not supported.
 812          * result = 1, means INCRx burst mode supported.
 813          * result > 1, means undefined length burst mode supported.
 814          */
 815         ntype = device_property_read_u32_array(dev,
 816                         "snps,incr-burst-type-adjustment", NULL, 0);
 817         if (ntype <= 0)
 818                 return;
 819
 820         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 821         if (!vals) {
 822                 dev_err(dev, "Error to get memory\n");
 823                 return;
 824         }
 825
 826         /* Get INCR burst type, and parse it */
 827         ret = device_property_read_u32_array(dev,
 828                         "snps,incr-burst-type-adjustment", vals, ntype);
 829         if (ret) {
 830                 kfree(vals);
 831                 dev_err(dev, "Error to get property\n");
 832                 return;
 833         }
 834
 835         incrx_size = *vals;
 836
 837         if (ntype > 1) {
 838                 /* INCRX (undefined length) burst mode */
 839                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
 840                 for (i = 1; i < ntype; i++) {
 841                         if (vals[i] > incrx_size)
 842                                 incrx_size = vals[i];
 843                 }
 844         } else {
 845                 /* INCRX burst mode */
 846                 incrx_mode = INCRX_BURST_MODE;
 847         }
 848
 849         kfree(vals);
 850
 851         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 852         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 853         if (incrx_mode)
 854                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
 855         switch (incrx_size) {
 856         case 256:
 857                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
 858                 break;
 859         case 128:
 860                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
 861                 break;
 862         case 64:
 863                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
 864                 break;
 865         case 32:
 866                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
 867                 break;
 868         case 16:
 869                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
 870                 break;
 871         case 8:
 872                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
 873                 break;
 874         case 4:
 875                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
 876                 break;
 877         case 1:
 878                 break;
 879         default:
 880                 dev_err(dev, "Invalid property\n");
 881                 break;
 882         }
 883
 884         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 885 }
 886
 887 /**
 888  * dwc3_core_init - Low-level initialization of DWC3 Core
 889  * @dwc: Pointer to our controller context structure
 890  *
 891  * Returns 0 on success otherwise negative errno.
 892  */
 893 static int dwc3_core_init(struct dwc3 *dwc)
 894 {
 895         u32                     reg;
 896         int                     ret;
 897
 898         /*
 899          * Write Linux Version Code to our GUID register so it's easy to figure
 900          * out which kernel version a bug was found.
 901          */
 902         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 903
 904         /* Handle USB2.0-only core configuration */
 905         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 906                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 907                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 908                         dwc->maximum_speed = USB_SPEED_HIGH;
 909         }
 910
 911         ret = dwc3_phy_setup(dwc);
 912         if (ret)
 913                 goto err0;
 914
 915         if (!dwc->ulpi_ready) {
 916                 ret = dwc3_core_ulpi_init(dwc);
 917                 if (ret)
 918                         goto err0;
 919                 dwc->ulpi_ready = true;
 920         }
 921
 922         if (!dwc->phys_ready) {
 923                 ret = dwc3_core_get_phy(dwc);
 924                 if (ret)
 925                         goto err0a;
 926                 dwc->phys_ready = true;
 927         }
 928
 929         ret = dwc3_core_soft_reset(dwc);
 930         if (ret)
 931                 goto err0a;
 932
 933         dwc3_core_setup_global_control(dwc);
 934         dwc3_core_num_eps(dwc);
 935
 936         ret = dwc3_setup_scratch_buffers(dwc);
 937         if (ret)
 938                 goto err1;
 939
 940         /* Adjust Frame Length */
 941         dwc3_frame_length_adjustment(dwc);
 942
 943         dwc3_set_incr_burst_type(dwc);
 944
 945         usb_phy_set_suspend(dwc->usb2_phy, 0);
 946         usb_phy_set_suspend(dwc->usb3_phy, 0);
 947         ret = phy_power_on(dwc->usb2_generic_phy);
 948         if (ret < 0)
 949                 goto err2;
 950
 951         ret = phy_power_on(dwc->usb3_generic_phy);
 952         if (ret < 0)
 953                 goto err3;
 954
 955         ret = dwc3_event_buffers_setup(dwc);
 956         if (ret) {
 957                 dev_err(dwc->dev, "failed to setup event buffers\n");
 958                 goto err4;
 959         }
 960
 961         /*
 962          * ENDXFER polling is available on version 3.10a and later of
 963          * the DWC_usb3 controller. It is NOT available in the
 964          * DWC_usb31 controller.
 965          */
 966         if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
 967                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
 968                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
 969                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
 970         }
 971
 972         if (dwc->revision >= DWC3_REVISION_250A) {
 973                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
 974
 975                 /*
 976                  * Enable hardware control of sending remote wakeup
 977                  * in HS when the device is in the L1 state.
 978                  */
 979                 if (dwc->revision >= DWC3_REVISION_290A)
 980                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
 981
 982                 if (dwc->dis_tx_ipgap_linecheck_quirk)
 983                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
 984
 985                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
 986         }
 987
 988         if (dwc->dr_mode == USB_DR_MODE_HOST ||
 989             dwc->dr_mode == USB_DR_MODE_OTG) {
 990                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
 991
 992                 /*
 993                  * Enable Auto retry Feature to make the controller operating in
 994                  * Host mode on seeing transaction errors(CRC errors or internal
 995                  * overrun scenerios) on IN transfers to reply to the device
 996                  * with a non-terminating retry ACK (i.e, an ACK transcation
 997                  * packet with Retry=1 & Nump != 0)
 998                  */
 999                 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1000
1001                 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1002         }
1003
1004         /*
1005          * Must config both number of packets and max burst settings to enable
1006          * RX and/or TX threshold.
1007          */
1008         if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
1009                 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1010                 u8 rx_maxburst = dwc->rx_max_burst_prd;
1011                 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1012                 u8 tx_maxburst = dwc->tx_max_burst_prd;
1013
1014                 if (rx_thr_num && rx_maxburst) {
1015                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1016                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1017
1018                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1019                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1020
1021                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1022                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1023
1024                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1025                 }
1026
1027                 if (tx_thr_num && tx_maxburst) {
1028                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1029                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1030
1031                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1032                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1033
1034                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1035                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1036
1037                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1038                 }
1039         }
1040
1041         return 0;
1042
1043 err4:
1044         phy_power_off(dwc->usb3_generic_phy);
1045
1046 err3:
1047         phy_power_off(dwc->usb2_generic_phy);
1048
1049 err2:
1050         usb_phy_set_suspend(dwc->usb2_phy, 1);
1051         usb_phy_set_suspend(dwc->usb3_phy, 1);
1052
1053 err1:
1054         usb_phy_shutdown(dwc->usb2_phy);
1055         usb_phy_shutdown(dwc->usb3_phy);
1056         phy_exit(dwc->usb2_generic_phy);
1057         phy_exit(dwc->usb3_generic_phy);
1058
1059 err0a:
1060         dwc3_ulpi_exit(dwc);
1061
1062 err0:
1063         return ret;
1064 }
1065
1066 static int dwc3_core_get_phy(struct dwc3 *dwc)
1067 {
1068         struct device           *dev = dwc->dev;
1069         struct device_node      *node = dev->of_node;
1070         int ret;
1071
1072         if (node) {
1073                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1074                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1075         } else {
1076                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1077                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1078         }
1079
1080         if (IS_ERR(dwc->usb2_phy)) {
1081                 ret = PTR_ERR(dwc->usb2_phy);
1082                 if (ret == -ENXIO || ret == -ENODEV) {
1083                         dwc->usb2_phy = NULL;
1084                 } else if (ret == -EPROBE_DEFER) {
1085                         return ret;
1086                 } else {
1087                         dev_err(dev, "no usb2 phy configured\n");
1088                         return ret;
1089                 }
1090         }
1091
1092         if (IS_ERR(dwc->usb3_phy)) {
1093                 ret = PTR_ERR(dwc->usb3_phy);
1094                 if (ret == -ENXIO || ret == -ENODEV) {
1095                         dwc->usb3_phy = NULL;
1096                 } else if (ret == -EPROBE_DEFER) {
1097                         return ret;
1098                 } else {
1099                         dev_err(dev, "no usb3 phy configured\n");
1100                         return ret;
1101                 }
1102         }
1103
1104         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1105         if (IS_ERR(dwc->usb2_generic_phy)) {
1106                 ret = PTR_ERR(dwc->usb2_generic_phy);
1107                 if (ret == -ENOSYS || ret == -ENODEV) {
1108                         dwc->usb2_generic_phy = NULL;
1109                 } else if (ret == -EPROBE_DEFER) {
1110                         return ret;
1111                 } else {
1112                         dev_err(dev, "no usb2 phy configured\n");
1113                         return ret;
1114                 }
1115         }
1116
1117         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1118         if (IS_ERR(dwc->usb3_generic_phy)) {
1119                 ret = PTR_ERR(dwc->usb3_generic_phy);
1120                 if (ret == -ENOSYS || ret == -ENODEV) {
1121                         dwc->usb3_generic_phy = NULL;
1122                 } else if (ret == -EPROBE_DEFER) {
1123                         return ret;
1124                 } else {
1125                         dev_err(dev, "no usb3 phy configured\n");
1126                         return ret;
1127                 }
1128         }
1129
1130         return 0;
1131 }
1132
1133 static int dwc3_core_init_mode(struct dwc3 *dwc)
1134 {
1135         struct device *dev = dwc->dev;
1136         int ret;
1137
1138         switch (dwc->dr_mode) {
1139         case USB_DR_MODE_PERIPHERAL:
1140                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1141
1142                 if (dwc->usb2_phy)
1143                         otg_set_vbus(dwc->usb2_phy->otg, false);
1144                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1145                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1146
1147                 ret = dwc3_gadget_init(dwc);
1148                 if (ret) {
1149                         if (ret != -EPROBE_DEFER)
1150                                 dev_err(dev, "failed to initialize gadget\n");
1151                         return ret;
1152                 }
1153                 break;
1154         case USB_DR_MODE_HOST:
1155                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1156
1157                 if (dwc->usb2_phy)
1158                         otg_set_vbus(dwc->usb2_phy->otg, true);
1159                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1160                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1161
1162                 ret = dwc3_host_init(dwc);
1163                 if (ret) {
1164                         if (ret != -EPROBE_DEFER)
1165                                 dev_err(dev, "failed to initialize host\n");
1166                         return ret;
1167                 }
1168                 phy_calibrate(dwc->usb2_generic_phy);
1169                 break;
1170         case USB_DR_MODE_OTG:
1171                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1172                 ret = dwc3_drd_init(dwc);
1173                 if (ret) {
1174                         if (ret != -EPROBE_DEFER)
1175                                 dev_err(dev, "failed to initialize dual-role\n");
1176                         return ret;
1177                 }
1178                 break;
1179         default:
1180                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1181                 return -EINVAL;
1182         }
1183
1184         return 0;
1185 }
1186
1187 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1188 {
1189         switch (dwc->dr_mode) {
1190         case USB_DR_MODE_PERIPHERAL:
1191                 dwc3_gadget_exit(dwc);
1192                 break;
1193         case USB_DR_MODE_HOST:
1194                 dwc3_host_exit(dwc);
1195                 break;
1196         case USB_DR_MODE_OTG:
1197                 dwc3_drd_exit(dwc);
1198                 break;
1199         default:
1200                 /* do nothing */
1201                 break;
1202         }
1203 }
1204
1205 static void dwc3_get_properties(struct dwc3 *dwc)
1206 {
1207         struct device           *dev = dwc->dev;
1208         u8                      lpm_nyet_threshold;
1209         u8                      tx_de_emphasis;
1210         u8                      hird_threshold;
1211         u8                      rx_thr_num_pkt_prd;
1212         u8                      rx_max_burst_prd;
1213         u8                      tx_thr_num_pkt_prd;
1214         u8                      tx_max_burst_prd;
1215
1216         /* default to highest possible threshold */
1217         lpm_nyet_threshold = 0xf;
1218
1219         /* default to -3.5dB de-emphasis */
1220         tx_de_emphasis = 1;
1221
1222         /*
1223          * default to assert utmi_sleep_n and use maximum allowed HIRD
1224          * threshold value of 0b1100
1225          */
1226         hird_threshold = 12;
1227
1228         dwc->maximum_speed = usb_get_maximum_speed(dev);
1229         dwc->dr_mode = usb_get_dr_mode(dev);
1230         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1231
1232         dwc->sysdev_is_parent = device_property_read_bool(dev,
1233                                 "linux,sysdev_is_parent");
1234         if (dwc->sysdev_is_parent)
1235                 dwc->sysdev = dwc->dev->parent;
1236         else
1237                 dwc->sysdev = dwc->dev;
1238
1239         dwc->has_lpm_erratum = device_property_read_bool(dev,
1240                                 "snps,has-lpm-erratum");
1241         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1242                                 &lpm_nyet_threshold);
1243         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1244                                 "snps,is-utmi-l1-suspend");
1245         device_property_read_u8(dev, "snps,hird-threshold",
1246                                 &hird_threshold);
1247         dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1248                                 "snps,dis-start-transfer-quirk");
1249         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1250                                 "snps,usb3_lpm_capable");
1251         dwc->usb2_lpm_disable = device_property_read_bool(dev,
1252                                 "snps,usb2-lpm-disable");
1253         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1254                                 &rx_thr_num_pkt_prd);
1255         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1256                                 &rx_max_burst_prd);
1257         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1258                                 &tx_thr_num_pkt_prd);
1259         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1260                                 &tx_max_burst_prd);
1261
1262         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1263                                 "snps,disable_scramble_quirk");
1264         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1265                                 "snps,u2exit_lfps_quirk");
1266         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1267                                 "snps,u2ss_inp3_quirk");
1268         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1269                                 "snps,req_p1p2p3_quirk");
1270         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1271                                 "snps,del_p1p2p3_quirk");
1272         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1273                                 "snps,del_phy_power_chg_quirk");
1274         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1275                                 "snps,lfps_filter_quirk");
1276         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1277                                 "snps,rx_detect_poll_quirk");
1278         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1279                                 "snps,dis_u3_susphy_quirk");
1280         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1281                                 "snps,dis_u2_susphy_quirk");
1282         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1283                                 "snps,dis_enblslpm_quirk");
1284         dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1285                                 "snps,dis-u1-entry-quirk");
1286         dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1287                                 "snps,dis-u2-entry-quirk");
1288         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1289                                 "snps,dis_rxdet_inp3_quirk");
1290         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1291                                 "snps,dis-u2-freeclk-exists-quirk");
1292         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1293                                 "snps,dis-del-phy-power-chg-quirk");
1294         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1295                                 "snps,dis-tx-ipgap-linecheck-quirk");
1296
1297         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1298                                 "snps,tx_de_emphasis_quirk");
1299         device_property_read_u8(dev, "snps,tx_de_emphasis",
1300                                 &tx_de_emphasis);
1301         device_property_read_string(dev, "snps,hsphy_interface",
1302                                     &dwc->hsphy_interface);
1303         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1304                                  &dwc->fladj);
1305
1306         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1307                                 "snps,dis_metastability_quirk");
1308
1309         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1310         dwc->tx_de_emphasis = tx_de_emphasis;
1311
1312         dwc->hird_threshold = hird_threshold
1313                 | (dwc->is_utmi_l1_suspend << 4);
1314
1315         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1316         dwc->rx_max_burst_prd = rx_max_burst_prd;
1317
1318         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1319         dwc->tx_max_burst_prd = tx_max_burst_prd;
1320
1321         dwc->imod_interval = 0;
1322 }
1323
1324 /* check whether the core supports IMOD */
1325 bool dwc3_has_imod(struct dwc3 *dwc)
1326 {
1327         return ((dwc3_is_usb3(dwc) &&
1328                  dwc->revision >= DWC3_REVISION_300A) ||
1329                 (dwc3_is_usb31(dwc) &&
1330                  dwc->revision >= DWC3_USB31_REVISION_120A));
1331 }
1332
1333 static void dwc3_check_params(struct dwc3 *dwc)
1334 {
1335         struct device *dev = dwc->dev;
1336
1337         /* Check for proper value of imod_interval */
1338         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1339                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1340                 dwc->imod_interval = 0;
1341         }
1342
1343         /*
1344          * Workaround for STAR 9000961433 which affects only version
1345          * 3.00a of the DWC_usb3 core. This prevents the controller
1346          * interrupt from being masked while handling events. IMOD
1347          * allows us to work around this issue. Enable it for the
1348          * affected version.
1349          */
1350         if (!dwc->imod_interval &&
1351             (dwc->revision == DWC3_REVISION_300A))
1352                 dwc->imod_interval = 1;
1353
1354         /* Check the maximum_speed parameter */
1355         switch (dwc->maximum_speed) {
1356         case USB_SPEED_LOW:
1357         case USB_SPEED_FULL:
1358         case USB_SPEED_HIGH:
1359         case USB_SPEED_SUPER:
1360         case USB_SPEED_SUPER_PLUS:
1361                 break;
1362         default:
1363                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1364                         dwc->maximum_speed);
1365                 /* fall through */
1366         case USB_SPEED_UNKNOWN:
1367                 /* default to superspeed */
1368                 dwc->maximum_speed = USB_SPEED_SUPER;
1369
1370                 /*
1371                  * default to superspeed plus if we are capable.
1372                  */
1373                 if (dwc3_is_usb31(dwc) &&
1374                     (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1375                      DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1376                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1377
1378                 break;
1379         }
1380 }
1381
1382 static int dwc3_probe(struct platform_device *pdev)
1383 {
1384         struct device           *dev = &pdev->dev;
1385         struct resource         *res, dwc_res;
1386         struct dwc3             *dwc;
1387
1388         int                     ret;
1389
1390         void __iomem            *regs;
1391
1392         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1393         if (!dwc)
1394                 return -ENOMEM;
1395
1396         dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks),
1397                                  GFP_KERNEL);
1398         if (!dwc->clks)
1399                 return -ENOMEM;
1400
1401         dwc->dev = dev;
1402
1403         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1404         if (!res) {
1405                 dev_err(dev, "missing memory resource\n");
1406                 return -ENODEV;
1407         }
1408
1409         dwc->xhci_resources[0].start = res->start;
1410         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1411                                         DWC3_XHCI_REGS_END;
1412         dwc->xhci_resources[0].flags = res->flags;
1413         dwc->xhci_resources[0].name = res->name;
1414
1415         /*
1416          * Request memory region but exclude xHCI regs,
1417          * since it will be requested by the xhci-plat driver.
1418          */
1419         dwc_res = *res;
1420         dwc_res.start += DWC3_GLOBALS_REGS_START;
1421
1422         regs = devm_ioremap_resource(dev, &dwc_res);
1423         if (IS_ERR(regs))
1424                 return PTR_ERR(regs);
1425
1426         dwc->regs       = regs;
1427         dwc->regs_size  = resource_size(&dwc_res);
1428
1429         dwc3_get_properties(dwc);
1430
1431         dwc->reset = devm_reset_control_get_optional_shared(dev, NULL);
1432         if (IS_ERR(dwc->reset))
1433                 return PTR_ERR(dwc->reset);
1434
1435         if (dev->of_node) {
1436                 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
1437
1438                 ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks);
1439                 if (ret == -EPROBE_DEFER)
1440                         return ret;
1441                 /*
1442                  * Clocks are optional, but new DT platforms should support all
1443                  * clocks as required by the DT-binding.
1444                  */
1445                 if (ret)
1446                         dwc->num_clks = 0;
1447         }
1448
1449         ret = reset_control_deassert(dwc->reset);
1450         if (ret)
1451                 goto put_clks;
1452
1453         ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1454         if (ret)
1455                 goto assert_reset;
1456
1457         ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1458         if (ret)
1459                 goto unprepare_clks;
1460
1461         if (!dwc3_core_is_valid(dwc)) {
1462                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1463                 ret = -ENODEV;
1464                 goto disable_clks;
1465         }
1466
1467         platform_set_drvdata(pdev, dwc);
1468         dwc3_cache_hwparams(dwc);
1469
1470         spin_lock_init(&dwc->lock);
1471
1472         pm_runtime_set_active(dev);
1473         pm_runtime_use_autosuspend(dev);
1474         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1475         pm_runtime_enable(dev);
1476         ret = pm_runtime_get_sync(dev);
1477         if (ret < 0)
1478                 goto err1;
1479
1480         pm_runtime_forbid(dev);
1481
1482         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1483         if (ret) {
1484                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1485                 ret = -ENOMEM;
1486                 goto err2;
1487         }
1488
1489         ret = dwc3_get_dr_mode(dwc);
1490         if (ret)
1491                 goto err3;
1492
1493         ret = dwc3_alloc_scratch_buffers(dwc);
1494         if (ret)
1495                 goto err3;
1496
1497         ret = dwc3_core_init(dwc);
1498         if (ret) {
1499                 if (ret != -EPROBE_DEFER)
1500                         dev_err(dev, "failed to initialize core: %d\n", ret);
1501                 goto err4;
1502         }
1503
1504         dwc3_check_params(dwc);
1505
1506         ret = dwc3_core_init_mode(dwc);
1507         if (ret)
1508                 goto err5;
1509
1510         dwc3_debugfs_init(dwc);
1511         pm_runtime_put(dev);
1512
1513         return 0;
1514
1515 err5:
1516         dwc3_event_buffers_cleanup(dwc);
1517         dwc3_ulpi_exit(dwc);
1518
1519 err4:
1520         dwc3_free_scratch_buffers(dwc);
1521
1522 err3:
1523         dwc3_free_event_buffers(dwc);
1524
1525 err2:
1526         pm_runtime_allow(&pdev->dev);
1527
1528 err1:
1529         pm_runtime_put_sync(&pdev->dev);
1530         pm_runtime_disable(&pdev->dev);
1531
1532 disable_clks:
1533         clk_bulk_disable(dwc->num_clks, dwc->clks);
1534 unprepare_clks:
1535         clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1536 assert_reset:
1537         reset_control_assert(dwc->reset);
1538 put_clks:
1539         clk_bulk_put(dwc->num_clks, dwc->clks);
1540
1541         return ret;
1542 }
1543
1544 static int dwc3_remove(struct platform_device *pdev)
1545 {
1546         struct dwc3     *dwc = platform_get_drvdata(pdev);
1547
1548         pm_runtime_get_sync(&pdev->dev);
1549
1550         dwc3_debugfs_exit(dwc);
1551         dwc3_core_exit_mode(dwc);
1552
1553         dwc3_core_exit(dwc);
1554         dwc3_ulpi_exit(dwc);
1555
1556         pm_runtime_put_sync(&pdev->dev);
1557         pm_runtime_allow(&pdev->dev);
1558         pm_runtime_disable(&pdev->dev);
1559
1560         dwc3_free_event_buffers(dwc);
1561         dwc3_free_scratch_buffers(dwc);
1562         clk_bulk_put(dwc->num_clks, dwc->clks);
1563
1564         return 0;
1565 }
1566
1567 #ifdef CONFIG_PM
1568 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1569 {
1570         int ret;
1571
1572         ret = reset_control_deassert(dwc->reset);
1573         if (ret)
1574                 return ret;
1575
1576         ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1577         if (ret)
1578                 goto assert_reset;
1579
1580         ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1581         if (ret)
1582                 goto unprepare_clks;
1583
1584         ret = dwc3_core_init(dwc);
1585         if (ret)
1586                 goto disable_clks;
1587
1588         return 0;
1589
1590 disable_clks:
1591         clk_bulk_disable(dwc->num_clks, dwc->clks);
1592 unprepare_clks:
1593         clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1594 assert_reset:
1595         reset_control_assert(dwc->reset);
1596
1597         return ret;
1598 }
1599
1600 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1601 {
1602         unsigned long   flags;
1603         u32 reg;
1604
1605         switch (dwc->current_dr_role) {
1606         case DWC3_GCTL_PRTCAP_DEVICE:
1607                 spin_lock_irqsave(&dwc->lock, flags);
1608                 dwc3_gadget_suspend(dwc);
1609                 spin_unlock_irqrestore(&dwc->lock, flags);
1610                 synchronize_irq(dwc->irq_gadget);
1611                 dwc3_core_exit(dwc);
1612                 break;
1613         case DWC3_GCTL_PRTCAP_HOST:
1614                 if (!PMSG_IS_AUTO(msg)) {
1615                         dwc3_core_exit(dwc);
1616                         break;
1617                 }
1618
1619                 /* Let controller to suspend HSPHY before PHY driver suspends */
1620                 if (dwc->dis_u2_susphy_quirk ||
1621                     dwc->dis_enblslpm_quirk) {
1622                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1623                         reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1624                                 DWC3_GUSB2PHYCFG_SUSPHY;
1625                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1626
1627                         /* Give some time for USB2 PHY to suspend */
1628                         usleep_range(5000, 6000);
1629                 }
1630
1631                 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1632                 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1633                 break;
1634         case DWC3_GCTL_PRTCAP_OTG:
1635                 /* do nothing during runtime_suspend */
1636                 if (PMSG_IS_AUTO(msg))
1637                         break;
1638
1639                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1640                         spin_lock_irqsave(&dwc->lock, flags);
1641                         dwc3_gadget_suspend(dwc);
1642                         spin_unlock_irqrestore(&dwc->lock, flags);
1643                         synchronize_irq(dwc->irq_gadget);
1644                 }
1645
1646                 dwc3_otg_exit(dwc);
1647                 dwc3_core_exit(dwc);
1648                 break;
1649         default:
1650                 /* do nothing */
1651                 break;
1652         }
1653
1654         return 0;
1655 }
1656
1657 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1658 {
1659         unsigned long   flags;
1660         int             ret;
1661         u32             reg;
1662
1663         switch (dwc->current_dr_role) {
1664         case DWC3_GCTL_PRTCAP_DEVICE:
1665                 ret = dwc3_core_init_for_resume(dwc);
1666                 if (ret)
1667                         return ret;
1668
1669                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1670                 spin_lock_irqsave(&dwc->lock, flags);
1671                 dwc3_gadget_resume(dwc);
1672                 spin_unlock_irqrestore(&dwc->lock, flags);
1673                 break;
1674         case DWC3_GCTL_PRTCAP_HOST:
1675                 if (!PMSG_IS_AUTO(msg)) {
1676                         ret = dwc3_core_init_for_resume(dwc);
1677                         if (ret)
1678                                 return ret;
1679                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1680                         break;
1681                 }
1682                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1683                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1684                 if (dwc->dis_u2_susphy_quirk)
1685                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1686
1687                 if (dwc->dis_enblslpm_quirk)
1688                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1689
1690                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1691
1692                 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1693                 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1694                 break;
1695         case DWC3_GCTL_PRTCAP_OTG:
1696                 /* nothing to do on runtime_resume */
1697                 if (PMSG_IS_AUTO(msg))
1698                         break;
1699
1700                 ret = dwc3_core_init(dwc);
1701                 if (ret)
1702                         return ret;
1703
1704                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1705
1706                 dwc3_otg_init(dwc);
1707                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1708                         dwc3_otg_host_init(dwc);
1709                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1710                         spin_lock_irqsave(&dwc->lock, flags);
1711                         dwc3_gadget_resume(dwc);
1712                         spin_unlock_irqrestore(&dwc->lock, flags);
1713                 }
1714
1715                 break;
1716         default:
1717                 /* do nothing */
1718                 break;
1719         }
1720
1721         return 0;
1722 }
1723
1724 static int dwc3_runtime_checks(struct dwc3 *dwc)
1725 {
1726         switch (dwc->current_dr_role) {
1727         case DWC3_GCTL_PRTCAP_DEVICE:
1728                 if (dwc->connected)
1729                         return -EBUSY;
1730                 break;
1731         case DWC3_GCTL_PRTCAP_HOST:
1732         default:
1733                 /* do nothing */
1734                 break;
1735         }
1736
1737         return 0;
1738 }
1739
1740 static int dwc3_runtime_suspend(struct device *dev)
1741 {
1742         struct dwc3     *dwc = dev_get_drvdata(dev);
1743         int             ret;
1744
1745         if (dwc3_runtime_checks(dwc))
1746                 return -EBUSY;
1747
1748         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1749         if (ret)
1750                 return ret;
1751
1752         device_init_wakeup(dev, true);
1753
1754         return 0;
1755 }
1756
1757 static int dwc3_runtime_resume(struct device *dev)
1758 {
1759         struct dwc3     *dwc = dev_get_drvdata(dev);
1760         int             ret;
1761
1762         device_init_wakeup(dev, false);
1763
1764         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1765         if (ret)
1766                 return ret;
1767
1768         switch (dwc->current_dr_role) {
1769         case DWC3_GCTL_PRTCAP_DEVICE:
1770                 dwc3_gadget_process_pending_events(dwc);
1771                 break;
1772         case DWC3_GCTL_PRTCAP_HOST:
1773         default:
1774                 /* do nothing */
1775                 break;
1776         }
1777
1778         pm_runtime_mark_last_busy(dev);
1779
1780         return 0;
1781 }
1782
1783 static int dwc3_runtime_idle(struct device *dev)
1784 {
1785         struct dwc3     *dwc = dev_get_drvdata(dev);
1786
1787         switch (dwc->current_dr_role) {
1788         case DWC3_GCTL_PRTCAP_DEVICE:
1789                 if (dwc3_runtime_checks(dwc))
1790                         return -EBUSY;
1791                 break;
1792         case DWC3_GCTL_PRTCAP_HOST:
1793         default:
1794                 /* do nothing */
1795                 break;
1796         }
1797
1798         pm_runtime_mark_last_busy(dev);
1799         pm_runtime_autosuspend(dev);
1800
1801         return 0;
1802 }
1803 #endif /* CONFIG_PM */
1804
1805 #ifdef CONFIG_PM_SLEEP
1806 static int dwc3_suspend(struct device *dev)
1807 {
1808         struct dwc3     *dwc = dev_get_drvdata(dev);
1809         int             ret;
1810
1811         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1812         if (ret)
1813                 return ret;
1814
1815         pinctrl_pm_select_sleep_state(dev);
1816
1817         return 0;
1818 }
1819
1820 static int dwc3_resume(struct device *dev)
1821 {
1822         struct dwc3     *dwc = dev_get_drvdata(dev);
1823         int             ret;
1824
1825         pinctrl_pm_select_default_state(dev);
1826
1827         ret = dwc3_resume_common(dwc, PMSG_RESUME);
1828         if (ret)
1829                 return ret;
1830
1831         pm_runtime_disable(dev);
1832         pm_runtime_set_active(dev);
1833         pm_runtime_enable(dev);
1834
1835         return 0;
1836 }
1837 #endif /* CONFIG_PM_SLEEP */
1838
1839 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1840         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1841         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1842                         dwc3_runtime_idle)
1843 };
1844
1845 #ifdef CONFIG_OF
1846 static const struct of_device_id of_dwc3_match[] = {
1847         {
1848                 .compatible = "snps,dwc3"
1849         },
1850         {
1851                 .compatible = "synopsys,dwc3"
1852         },
1853         { },
1854 };
1855 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1856 #endif
1857
1858 #ifdef CONFIG_ACPI
1859
1860 #define ACPI_ID_INTEL_BSW       "808622B7"
1861
1862 static const struct acpi_device_id dwc3_acpi_match[] = {
1863         { ACPI_ID_INTEL_BSW, 0 },
1864         { },
1865 };
1866 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1867 #endif
1868
1869 static struct platform_driver dwc3_driver = {
1870         .probe          = dwc3_probe,
1871         .remove         = dwc3_remove,
1872         .driver         = {
1873                 .name   = "dwc3",
1874                 .of_match_table = of_match_ptr(of_dwc3_match),
1875                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1876                 .pm     = &dwc3_dev_pm_ops,
1877         },
1878 };
1879
1880 module_platform_driver(dwc3_driver);
1881
1882 MODULE_ALIAS("platform:dwc3");
1883 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1884 MODULE_LICENSE("GPL v2");
1885 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");