1 // SPDX-License-Identifier: GPL-2.0+
3 * ufs.c - Universal Flash Subsystem (UFS) driver
5 * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported
8 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
15 #include <dm/device-internal.h>
20 #include <asm/dma-mapping.h>
24 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
27 /* maximum number of link-startup retries */
28 #define DME_LINKSTARTUP_RETRIES 3
30 /* maximum number of retries for a general UIC command */
31 #define UFS_UIC_COMMAND_RETRIES 3
33 /* Query request retries */
34 #define QUERY_REQ_RETRIES 3
35 /* Query request timeout */
36 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
38 /* maximum timeout in ms for a general UIC command */
39 #define UFS_UIC_CMD_TIMEOUT 1000
40 /* NOP OUT retries waiting for NOP IN response */
41 #define NOP_OUT_RETRIES 10
42 /* Timeout after 30 msecs if NOP OUT hangs without response */
43 #define NOP_OUT_TIMEOUT 30 /* msecs */
45 /* Only use one Task Tag for all requests */
48 /* Expose the flag value from utp_upiu_query.value */
49 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
51 #define MAX_PRDT_ENTRY 262144
53 /* maximum bytes per request */
54 #define UFS_MAX_BYTES (128 * 256 * 1024)
56 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba);
57 static inline void ufshcd_hba_stop(struct ufs_hba *hba);
58 static int ufshcd_hba_enable(struct ufs_hba *hba);
61 * ufshcd_wait_for_register - wait for register value to change
63 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
64 u32 val, unsigned long timeout_ms)
67 unsigned long start = get_timer(0);
69 /* ignore bits that we don't intend to wait on */
72 while ((ufshcd_readl(hba, reg) & mask) != val) {
73 if (get_timer(start) > timeout_ms) {
74 if ((ufshcd_readl(hba, reg) & mask) != val)
84 * ufshcd_init_pwr_info - setting the POR (power on reset)
85 * values in hba power info
87 static void ufshcd_init_pwr_info(struct ufs_hba *hba)
89 hba->pwr_info.gear_rx = UFS_PWM_G1;
90 hba->pwr_info.gear_tx = UFS_PWM_G1;
91 hba->pwr_info.lane_rx = 1;
92 hba->pwr_info.lane_tx = 1;
93 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
94 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
95 hba->pwr_info.hs_rate = 0;
99 * ufshcd_print_pwr_info - print power params as saved in hba
102 static void ufshcd_print_pwr_info(struct ufs_hba *hba)
104 static const char * const names[] = {
114 dev_err(hba->dev, "[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
115 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
116 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
117 names[hba->pwr_info.pwr_rx],
118 names[hba->pwr_info.pwr_tx],
119 hba->pwr_info.hs_rate);
123 * ufshcd_ready_for_uic_cmd - Check if controller is ready
124 * to accept UIC commands
126 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
128 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
135 * ufshcd_get_uic_cmd_result - Get the UIC command result
137 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
139 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
140 MASK_UIC_COMMAND_RESULT;
144 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
146 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
148 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
152 * ufshcd_is_device_present - Check if any device connected to
153 * the host controller
155 static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
157 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
158 DEVICE_PRESENT) ? true : false;
162 * ufshcd_send_uic_cmd - UFS Interconnect layer command API
165 static int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
167 unsigned long start = 0;
169 u32 enabled_intr_status;
171 if (!ufshcd_ready_for_uic_cmd(hba)) {
173 "Controller not ready to accept UIC commands\n");
177 debug("sending uic command:%d\n", uic_cmd->command);
180 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
181 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
182 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
185 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
188 start = get_timer(0);
190 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
191 enabled_intr_status = intr_status & hba->intr_mask;
192 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
194 if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) {
196 "Timedout waiting for UIC response\n");
201 if (enabled_intr_status & UFSHCD_ERROR_MASK) {
202 dev_err(hba->dev, "Error in status:%08x\n",
203 enabled_intr_status);
207 } while (!(enabled_intr_status & UFSHCD_UIC_MASK));
209 uic_cmd->argument2 = ufshcd_get_uic_cmd_result(hba);
210 uic_cmd->argument3 = ufshcd_get_dme_attr_val(hba);
212 debug("Sent successfully\n");
218 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
221 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, u8 attr_set,
222 u32 mib_val, u8 peer)
224 struct uic_command uic_cmd = {0};
225 static const char *const action[] = {
229 const char *set = action[!!peer];
231 int retries = UFS_UIC_COMMAND_RETRIES;
233 uic_cmd.command = peer ?
234 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
235 uic_cmd.argument1 = attr_sel;
236 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
237 uic_cmd.argument3 = mib_val;
240 /* for peer attributes we retry upon failure */
241 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
243 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
244 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
245 } while (ret && peer && --retries);
248 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
249 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
250 UFS_UIC_COMMAND_RETRIES - retries);
256 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
259 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
260 u32 *mib_val, u8 peer)
262 struct uic_command uic_cmd = {0};
263 static const char *const action[] = {
267 const char *get = action[!!peer];
269 int retries = UFS_UIC_COMMAND_RETRIES;
271 uic_cmd.command = peer ?
272 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
273 uic_cmd.argument1 = attr_sel;
276 /* for peer attributes we retry upon failure */
277 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
279 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
280 get, UIC_GET_ATTR_ID(attr_sel), ret);
281 } while (ret && peer && --retries);
284 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
285 get, UIC_GET_ATTR_ID(attr_sel),
286 UFS_UIC_COMMAND_RETRIES - retries);
289 *mib_val = uic_cmd.argument3;
294 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
296 u32 tx_lanes, i, err = 0;
299 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
302 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
304 for (i = 0; i < tx_lanes; i++) {
306 err = ufshcd_dme_set(hba,
307 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
308 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
311 err = ufshcd_dme_peer_set(hba,
312 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
313 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
316 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
317 __func__, peer, i, err);
325 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
327 return ufshcd_disable_tx_lcc(hba, true);
331 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
334 static int ufshcd_dme_link_startup(struct ufs_hba *hba)
336 struct uic_command uic_cmd = {0};
339 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
341 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
344 "dme-link-startup: error code %d\n", ret);
349 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
352 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
354 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
358 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
360 static inline int ufshcd_get_lists_status(u32 reg)
362 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
366 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
367 * When run-stop registers are set to 1, it indicates the
368 * host controller that it can process the requests
370 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
372 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
373 REG_UTP_TASK_REQ_LIST_RUN_STOP);
374 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
375 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
379 * ufshcd_enable_intr - enable interrupts
381 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
383 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
386 if (hba->version == UFSHCI_VERSION_10) {
387 rw = set & INTERRUPT_MASK_RW_VER_10;
388 set = rw | ((set ^ intrs) & intrs);
393 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
395 hba->intr_mask = set;
399 * ufshcd_make_hba_operational - Make UFS controller operational
401 * To bring UFS host controller to operational state,
402 * 1. Enable required interrupts
403 * 2. Configure interrupt aggregation
404 * 3. Program UTRL and UTMRL base address
405 * 4. Configure run-stop-registers
408 static int ufshcd_make_hba_operational(struct ufs_hba *hba)
413 /* Enable required interrupts */
414 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
416 /* Disable interrupt aggregation */
417 ufshcd_disable_intr_aggr(hba);
419 /* Configure UTRL and UTMRL base address registers */
420 ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utrdl),
421 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
422 ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utrdl),
423 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
424 ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utmrdl),
425 REG_UTP_TASK_REQ_LIST_BASE_L);
426 ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl),
427 REG_UTP_TASK_REQ_LIST_BASE_H);
430 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
432 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
433 if (!(ufshcd_get_lists_status(reg))) {
434 ufshcd_enable_run_stop_reg(hba);
437 "Host controller not ready to process requests");
447 * ufshcd_link_startup - Initialize unipro link startup
449 static int ufshcd_link_startup(struct ufs_hba *hba)
452 int retries = DME_LINKSTARTUP_RETRIES;
453 bool link_startup_again = true;
457 ufshcd_ops_link_startup_notify(hba, PRE_CHANGE);
459 ret = ufshcd_dme_link_startup(hba);
461 /* check if device is detected by inter-connect layer */
462 if (!ret && !ufshcd_is_device_present(hba)) {
463 dev_err(hba->dev, "%s: Device not present\n", __func__);
469 * DME link lost indication is only received when link is up,
470 * but we can't be sure if the link is up until link startup
471 * succeeds. So reset the local Uni-Pro and try again.
473 if (ret && ufshcd_hba_enable(hba))
475 } while (ret && retries--);
478 /* failed to get the link up... retire */
481 if (link_startup_again) {
482 link_startup_again = false;
483 retries = DME_LINKSTARTUP_RETRIES;
487 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
488 ufshcd_init_pwr_info(hba);
490 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
491 ret = ufshcd_disable_device_tx_lcc(hba);
496 /* Include any host controller configuration via UIC commands */
497 ret = ufshcd_ops_link_startup_notify(hba, POST_CHANGE);
501 ret = ufshcd_make_hba_operational(hba);
504 dev_err(hba->dev, "link startup failed %d\n", ret);
510 * ufshcd_hba_stop - Send controller to reset state
512 static inline void ufshcd_hba_stop(struct ufs_hba *hba)
516 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
517 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
518 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
521 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
525 * ufshcd_is_hba_active - Get controller state
527 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
529 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
534 * ufshcd_hba_start - Start controller initialization sequence
536 static inline void ufshcd_hba_start(struct ufs_hba *hba)
538 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
542 * ufshcd_hba_enable - initialize the controller
544 static int ufshcd_hba_enable(struct ufs_hba *hba)
548 if (!ufshcd_is_hba_active(hba))
549 /* change controller state to "reset state" */
550 ufshcd_hba_stop(hba);
552 ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE);
554 /* start controller initialization sequence */
555 ufshcd_hba_start(hba);
558 * To initialize a UFS host controller HCE bit must be set to 1.
559 * During initialization the HCE bit value changes from 1->0->1.
560 * When the host controller completes initialization sequence
561 * it sets the value of HCE bit to 1. The same HCE bit is read back
562 * to check if the controller has completed initialization sequence.
563 * So without this delay the value HCE = 1, set in the previous
564 * instruction might be read back.
565 * This delay can be changed based on the controller.
569 /* wait for the host controller to complete initialization */
571 while (ufshcd_is_hba_active(hba)) {
575 dev_err(hba->dev, "Controller enable failed\n");
581 /* enable UIC related interrupts */
582 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
584 ufshcd_ops_hce_enable_notify(hba, POST_CHANGE);
590 * ufshcd_host_memory_configure - configure local reference block with
593 static void ufshcd_host_memory_configure(struct ufs_hba *hba)
595 struct utp_transfer_req_desc *utrdlp;
596 dma_addr_t cmd_desc_dma_addr;
601 cmd_desc_dma_addr = (dma_addr_t)hba->ucdl;
603 utrdlp->command_desc_base_addr_lo =
604 cpu_to_le32(lower_32_bits(cmd_desc_dma_addr));
605 utrdlp->command_desc_base_addr_hi =
606 cpu_to_le32(upper_32_bits(cmd_desc_dma_addr));
608 response_offset = offsetof(struct utp_transfer_cmd_desc, response_upiu);
609 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
611 utrdlp->response_upiu_offset = cpu_to_le16(response_offset >> 2);
612 utrdlp->prd_table_offset = cpu_to_le16(prdt_offset >> 2);
613 utrdlp->response_upiu_length = cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
615 hba->ucd_req_ptr = (struct utp_upiu_req *)hba->ucdl;
617 (struct utp_upiu_rsp *)&hba->ucdl->response_upiu;
619 (struct ufshcd_sg_entry *)&hba->ucdl->prd_table;
623 * ufshcd_memory_alloc - allocate memory for host memory space data structures
625 static int ufshcd_memory_alloc(struct ufs_hba *hba)
627 /* Allocate one Transfer Request Descriptor
628 * Should be aligned to 1k boundary.
630 hba->utrdl = memalign(1024, sizeof(struct utp_transfer_req_desc));
632 dev_err(hba->dev, "Transfer Descriptor memory allocation failed\n");
636 /* Allocate one Command Descriptor
637 * Should be aligned to 1k boundary.
639 hba->ucdl = memalign(1024, sizeof(struct utp_transfer_cmd_desc));
641 dev_err(hba->dev, "Command descriptor memory allocation failed\n");
649 * ufshcd_get_intr_mask - Get the interrupt bit mask
651 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
655 switch (hba->version) {
656 case UFSHCI_VERSION_10:
657 intr_mask = INTERRUPT_MASK_ALL_VER_10;
659 case UFSHCI_VERSION_11:
660 case UFSHCI_VERSION_20:
661 intr_mask = INTERRUPT_MASK_ALL_VER_11;
663 case UFSHCI_VERSION_21:
665 intr_mask = INTERRUPT_MASK_ALL_VER_21;
673 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
675 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
677 return ufshcd_readl(hba, REG_UFS_VERSION);
681 * ufshcd_get_upmcrs - Get the power mode change request status
683 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
685 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
689 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
690 * descriptor according to request
692 static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc,
694 enum dma_data_direction cmd_dir)
699 if (cmd_dir == DMA_FROM_DEVICE) {
700 data_direction = UTP_DEVICE_TO_HOST;
701 *upiu_flags = UPIU_CMD_FLAGS_READ;
702 } else if (cmd_dir == DMA_TO_DEVICE) {
703 data_direction = UTP_HOST_TO_DEVICE;
704 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
706 data_direction = UTP_NO_DATA_TRANSFER;
707 *upiu_flags = UPIU_CMD_FLAGS_NONE;
710 dword_0 = data_direction | (0x1 << UPIU_COMMAND_TYPE_OFFSET);
712 /* Enable Interrupt for command */
713 dword_0 |= UTP_REQ_DESC_INT_CMD;
715 /* Transfer request descriptor header fields */
716 req_desc->header.dword_0 = cpu_to_le32(dword_0);
717 /* dword_1 is reserved, hence it is set to 0 */
718 req_desc->header.dword_1 = 0;
720 * assigning invalid value for command status. Controller
721 * updates OCS on command completion, with the command
724 req_desc->header.dword_2 =
725 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
726 /* dword_3 is reserved, hence it is set to 0 */
727 req_desc->header.dword_3 = 0;
729 req_desc->prd_table_length = 0;
732 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
735 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
736 struct ufs_query *query = &hba->dev_cmd.query;
737 u16 len = be16_to_cpu(query->request.upiu_req.length);
739 /* Query request header */
740 ucd_req_ptr->header.dword_0 =
741 UPIU_HEADER_DWORD(UPIU_TRANSACTION_QUERY_REQ,
742 upiu_flags, 0, TASK_TAG);
743 ucd_req_ptr->header.dword_1 =
744 UPIU_HEADER_DWORD(0, query->request.query_func,
747 /* Data segment length only need for WRITE_DESC */
748 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
749 ucd_req_ptr->header.dword_2 =
750 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
752 ucd_req_ptr->header.dword_2 = 0;
754 /* Copy the Query Request buffer as is */
755 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, QUERY_OSF_SIZE);
757 /* Copy the Descriptor */
758 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
759 memcpy(ucd_req_ptr + 1, query->descriptor, len);
761 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
764 static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba)
766 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
768 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
770 /* command descriptor fields */
771 ucd_req_ptr->header.dword_0 =
772 UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT, 0, 0, 0x1f);
773 /* clear rest of the fields of basic header */
774 ucd_req_ptr->header.dword_1 = 0;
775 ucd_req_ptr->header.dword_2 = 0;
777 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
781 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
782 * for Device Management Purposes
784 static int ufshcd_comp_devman_upiu(struct ufs_hba *hba,
785 enum dev_cmd_type cmd_type)
789 struct utp_transfer_req_desc *req_desc = hba->utrdl;
791 hba->dev_cmd.type = cmd_type;
793 ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, DMA_NONE);
795 case DEV_CMD_TYPE_QUERY:
796 ufshcd_prepare_utp_query_req_upiu(hba, upiu_flags);
798 case DEV_CMD_TYPE_NOP:
799 ufshcd_prepare_utp_nop_upiu(hba);
808 static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
812 u32 enabled_intr_status;
814 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
816 start = get_timer(0);
818 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
819 enabled_intr_status = intr_status & hba->intr_mask;
820 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
822 if (get_timer(start) > QUERY_REQ_TIMEOUT) {
824 "Timedout waiting for UTP response\n");
829 if (enabled_intr_status & UFSHCD_ERROR_MASK) {
830 dev_err(hba->dev, "Error in status:%08x\n",
831 enabled_intr_status);
835 } while (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL));
841 * ufshcd_get_req_rsp - returns the TR response transaction type
843 static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
845 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
849 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
852 static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba)
854 return le32_to_cpu(hba->utrdl->header.dword_2) & MASK_OCS;
857 static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
859 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
862 static int ufshcd_check_query_response(struct ufs_hba *hba)
864 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
866 /* Get the UPIU response */
867 query_res->response = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr) >>
868 UPIU_RSP_CODE_OFFSET;
869 return query_res->response;
873 * ufshcd_copy_query_response() - Copy the Query Response and the data
876 static int ufshcd_copy_query_response(struct ufs_hba *hba)
878 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
880 memcpy(&query_res->upiu_res, &hba->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
882 /* Get the descriptor */
883 if (hba->dev_cmd.query.descriptor &&
884 hba->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
885 u8 *descp = (u8 *)hba->ucd_rsp_ptr +
886 GENERAL_UPIU_REQUEST_SIZE;
890 /* data segment length */
891 resp_len = be32_to_cpu(hba->ucd_rsp_ptr->header.dword_2) &
892 MASK_QUERY_DATA_SEG_LEN;
894 be16_to_cpu(hba->dev_cmd.query.request.upiu_req.length);
895 if (likely(buf_len >= resp_len)) {
896 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
899 "%s: Response size is bigger than buffer",
909 * ufshcd_exec_dev_cmd - API for sending device management requests
911 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, enum dev_cmd_type cmd_type,
917 err = ufshcd_comp_devman_upiu(hba, cmd_type);
921 err = ufshcd_send_command(hba, TASK_TAG);
925 err = ufshcd_get_tr_ocs(hba);
927 dev_err(hba->dev, "Error in OCS:%d\n", err);
931 resp = ufshcd_get_req_rsp(hba->ucd_rsp_ptr);
933 case UPIU_TRANSACTION_NOP_IN:
935 case UPIU_TRANSACTION_QUERY_RSP:
936 err = ufshcd_check_query_response(hba);
938 err = ufshcd_copy_query_response(hba);
940 case UPIU_TRANSACTION_REJECT_UPIU:
941 /* TODO: handle Reject UPIU Response */
943 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
948 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
956 * ufshcd_init_query() - init the query response and request parameters
958 static inline void ufshcd_init_query(struct ufs_hba *hba,
959 struct ufs_query_req **request,
960 struct ufs_query_res **response,
961 enum query_opcode opcode,
962 u8 idn, u8 index, u8 selector)
964 *request = &hba->dev_cmd.query.request;
965 *response = &hba->dev_cmd.query.response;
966 memset(*request, 0, sizeof(struct ufs_query_req));
967 memset(*response, 0, sizeof(struct ufs_query_res));
968 (*request)->upiu_req.opcode = opcode;
969 (*request)->upiu_req.idn = idn;
970 (*request)->upiu_req.index = index;
971 (*request)->upiu_req.selector = selector;
975 * ufshcd_query_flag() - API function for sending flag query requests
977 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
978 enum flag_idn idn, bool *flag_res)
980 struct ufs_query_req *request = NULL;
981 struct ufs_query_res *response = NULL;
982 int err, index = 0, selector = 0;
983 int timeout = QUERY_REQ_TIMEOUT;
985 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
989 case UPIU_QUERY_OPCODE_SET_FLAG:
990 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
991 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
992 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
994 case UPIU_QUERY_OPCODE_READ_FLAG:
995 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
998 dev_err(hba->dev, "%s: Invalid argument for read request\n",
1006 "%s: Expected query flag opcode but got = %d\n",
1012 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
1016 "%s: Sending flag query for idn %d failed, err = %d\n",
1017 __func__, idn, err);
1022 *flag_res = (be32_to_cpu(response->upiu_res.value) &
1023 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
1029 static int ufshcd_query_flag_retry(struct ufs_hba *hba,
1030 enum query_opcode opcode,
1031 enum flag_idn idn, bool *flag_res)
1036 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
1037 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
1040 "%s: failed with error %d, retries %d\n",
1041 __func__, ret, retries);
1048 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
1049 __func__, opcode, idn, ret, retries);
1053 static int __ufshcd_query_descriptor(struct ufs_hba *hba,
1054 enum query_opcode opcode,
1055 enum desc_idn idn, u8 index, u8 selector,
1056 u8 *desc_buf, int *buf_len)
1058 struct ufs_query_req *request = NULL;
1059 struct ufs_query_res *response = NULL;
1063 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
1069 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
1070 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
1071 __func__, *buf_len);
1076 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1078 hba->dev_cmd.query.descriptor = desc_buf;
1079 request->upiu_req.length = cpu_to_be16(*buf_len);
1082 case UPIU_QUERY_OPCODE_WRITE_DESC:
1083 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1085 case UPIU_QUERY_OPCODE_READ_DESC:
1086 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1089 dev_err(hba->dev, "%s: Expected query descriptor opcode but got = 0x%.2x\n",
1095 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
1098 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
1099 __func__, opcode, idn, index, err);
1103 hba->dev_cmd.query.descriptor = NULL;
1104 *buf_len = be16_to_cpu(response->upiu_res.length);
1111 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
1113 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode,
1114 enum desc_idn idn, u8 index, u8 selector,
1115 u8 *desc_buf, int *buf_len)
1120 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
1121 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
1122 selector, desc_buf, buf_len);
1123 if (!err || err == -EINVAL)
1131 * ufshcd_read_desc_length - read the specified descriptor length from header
1133 static int ufshcd_read_desc_length(struct ufs_hba *hba, enum desc_idn desc_id,
1134 int desc_index, int *desc_length)
1137 u8 header[QUERY_DESC_HDR_SIZE];
1138 int header_len = QUERY_DESC_HDR_SIZE;
1140 if (desc_id >= QUERY_DESC_IDN_MAX)
1143 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
1144 desc_id, desc_index, 0, header,
1148 dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
1151 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
1152 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
1153 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
1158 *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
1163 static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
1167 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
1168 &hba->desc_size.dev_desc);
1170 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
1172 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
1173 &hba->desc_size.pwr_desc);
1175 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
1177 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
1178 &hba->desc_size.interc_desc);
1180 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
1182 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
1183 &hba->desc_size.conf_desc);
1185 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
1187 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
1188 &hba->desc_size.unit_desc);
1190 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
1192 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
1193 &hba->desc_size.geom_desc);
1195 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
1197 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
1198 &hba->desc_size.hlth_desc);
1200 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
1204 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
1207 int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
1211 case QUERY_DESC_IDN_DEVICE:
1212 *desc_len = hba->desc_size.dev_desc;
1214 case QUERY_DESC_IDN_POWER:
1215 *desc_len = hba->desc_size.pwr_desc;
1217 case QUERY_DESC_IDN_GEOMETRY:
1218 *desc_len = hba->desc_size.geom_desc;
1220 case QUERY_DESC_IDN_CONFIGURATION:
1221 *desc_len = hba->desc_size.conf_desc;
1223 case QUERY_DESC_IDN_UNIT:
1224 *desc_len = hba->desc_size.unit_desc;
1226 case QUERY_DESC_IDN_INTERCONNECT:
1227 *desc_len = hba->desc_size.interc_desc;
1229 case QUERY_DESC_IDN_STRING:
1230 *desc_len = QUERY_DESC_MAX_SIZE;
1232 case QUERY_DESC_IDN_HEALTH:
1233 *desc_len = hba->desc_size.hlth_desc;
1235 case QUERY_DESC_IDN_RFU_0:
1236 case QUERY_DESC_IDN_RFU_1:
1245 EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
1248 * ufshcd_read_desc_param - read the specified descriptor parameter
1251 int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id,
1252 int desc_index, u8 param_offset, u8 *param_read_buf,
1258 bool is_kmalloc = true;
1261 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
1264 /* Get the max length of descriptor from structure filled up at probe
1267 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
1270 if (ret || !buff_len) {
1271 dev_err(hba->dev, "%s: Failed to get full descriptor length",
1276 /* Check whether we need temp memory */
1277 if (param_offset != 0 || param_size < buff_len) {
1278 desc_buf = kmalloc(buff_len, GFP_KERNEL);
1282 desc_buf = param_read_buf;
1286 /* Request for full descriptor */
1287 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
1288 desc_id, desc_index, 0, desc_buf,
1292 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
1293 __func__, desc_id, desc_index, param_offset, ret);
1298 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
1299 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
1300 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
1305 /* Check wherher we will not copy more data, than available */
1306 if (is_kmalloc && param_size > buff_len)
1307 param_size = buff_len;
1310 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
1317 /* replace non-printable or non-ASCII characters with spaces */
1318 static inline void ufshcd_remove_non_printable(uint8_t *val)
1323 if (*val < 0x20 || *val > 0x7e)
1328 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
1329 * state) and waits for it to take effect.
1332 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
1334 unsigned long start = 0;
1338 ret = ufshcd_send_uic_cmd(hba, cmd);
1341 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
1342 cmd->command, cmd->argument3, ret);
1347 start = get_timer(0);
1349 status = ufshcd_get_upmcrs(hba);
1350 if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) {
1352 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
1353 cmd->command, status);
1354 ret = (status != PWR_OK) ? status : -1;
1357 } while (status != PWR_LOCAL);
1363 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode change
1364 * using DME_SET primitives.
1366 static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
1368 struct uic_command uic_cmd = {0};
1371 uic_cmd.command = UIC_CMD_DME_SET;
1372 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
1373 uic_cmd.argument3 = mode;
1374 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
1380 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba,
1381 struct scsi_cmd *pccb, u32 upiu_flags)
1383 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
1384 unsigned int cdb_len;
1386 /* command descriptor fields */
1387 ucd_req_ptr->header.dword_0 =
1388 UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND, upiu_flags,
1389 pccb->lun, TASK_TAG);
1390 ucd_req_ptr->header.dword_1 =
1391 UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
1393 /* Total EHS length and Data segment length will be zero */
1394 ucd_req_ptr->header.dword_2 = 0;
1396 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(pccb->datalen);
1398 cdb_len = min_t(unsigned short, pccb->cmdlen, UFS_CDB_SIZE);
1399 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
1400 memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len);
1402 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
1405 static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry,
1406 unsigned char *buf, ulong len)
1408 entry->size = cpu_to_le32(len) | GENMASK(1, 0);
1409 entry->base_addr = cpu_to_le32(lower_32_bits((unsigned long)buf));
1410 entry->upper_addr = cpu_to_le32(upper_32_bits((unsigned long)buf));
1413 static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb)
1415 struct utp_transfer_req_desc *req_desc = hba->utrdl;
1416 struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr;
1417 ulong datalen = pccb->datalen;
1423 req_desc->prd_table_length = 0;
1427 table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY);
1431 prepare_prdt_desc(&prd_table[table_length - i - 1], buf,
1432 MAX_PRDT_ENTRY - 1);
1433 buf += MAX_PRDT_ENTRY;
1434 datalen -= MAX_PRDT_ENTRY;
1437 prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1);
1439 req_desc->prd_table_length = table_length;
1442 static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb)
1444 struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent);
1445 struct utp_transfer_req_desc *req_desc = hba->utrdl;
1447 int ocs, result = 0;
1450 ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, pccb->dma_dir);
1451 ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags);
1452 prepare_prdt_table(hba, pccb);
1454 ufshcd_send_command(hba, TASK_TAG);
1456 ocs = ufshcd_get_tr_ocs(hba);
1459 result = ufshcd_get_req_rsp(hba->ucd_rsp_ptr);
1461 case UPIU_TRANSACTION_RESPONSE:
1462 result = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr);
1464 scsi_status = result & MASK_SCSI_STATUS;
1469 case UPIU_TRANSACTION_REJECT_UPIU:
1470 /* TODO: handle Reject UPIU Response */
1472 "Reject UPIU not fully implemented\n");
1476 "Unexpected request response code = %x\n",
1482 dev_err(hba->dev, "OCS error from controller = %x\n", ocs);
1489 static inline int ufshcd_read_desc(struct ufs_hba *hba, enum desc_idn desc_id,
1490 int desc_index, u8 *buf, u32 size)
1492 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
1495 static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
1497 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
1501 * ufshcd_read_string_desc - read string descriptor
1504 int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
1505 u8 *buf, u32 size, bool ascii)
1509 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING, desc_index, buf,
1513 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
1514 __func__, QUERY_REQ_RETRIES, err);
1525 /* remove header and divide by 2 to move from UTF16 to UTF8 */
1526 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
1527 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
1528 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
1534 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
1541 * the descriptor contains string in UTF16 format
1542 * we need to convert to utf-8 so it can be displayed
1544 utf16_to_utf8(buff_ascii,
1545 (uint16_t *)&buf[QUERY_DESC_HDR_SIZE], ascii_len);
1547 /* replace non-printable or non-ASCII characters with spaces */
1548 for (i = 0; i < ascii_len; i++)
1549 ufshcd_remove_non_printable(&buff_ascii[i]);
1551 memset(buf + QUERY_DESC_HDR_SIZE, 0,
1552 size - QUERY_DESC_HDR_SIZE);
1553 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
1554 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
1561 static int ufs_get_device_desc(struct ufs_hba *hba,
1562 struct ufs_dev_desc *dev_desc)
1569 buff_len = max_t(size_t, hba->desc_size.dev_desc,
1570 QUERY_DESC_MAX_SIZE + 1);
1571 desc_buf = kmalloc(buff_len, GFP_KERNEL);
1577 err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
1579 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
1585 * getting vendor (manufacturerID) and Bank Index in big endian
1588 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
1589 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
1591 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
1593 /* Zero-pad entire buffer for string termination. */
1594 memset(desc_buf, 0, buff_len);
1596 err = ufshcd_read_string_desc(hba, model_index, desc_buf,
1597 QUERY_DESC_MAX_SIZE, true/*ASCII*/);
1599 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
1604 desc_buf[QUERY_DESC_MAX_SIZE] = '\0';
1605 strlcpy(dev_desc->model, (char *)(desc_buf + QUERY_DESC_HDR_SIZE),
1606 min_t(u8, desc_buf[QUERY_DESC_LENGTH_OFFSET],
1609 /* Null terminate the model string */
1610 dev_desc->model[MAX_MODEL_LEN] = '\0';
1618 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
1620 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
1622 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
1624 if (hba->max_pwr_info.is_valid)
1627 pwr_info->pwr_tx = FAST_MODE;
1628 pwr_info->pwr_rx = FAST_MODE;
1629 pwr_info->hs_rate = PA_HS_MODE_B;
1631 /* Get the connected lane count */
1632 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
1633 &pwr_info->lane_rx);
1634 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
1635 &pwr_info->lane_tx);
1637 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
1638 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
1639 __func__, pwr_info->lane_rx, pwr_info->lane_tx);
1644 * First, get the maximum gears of HS speed.
1645 * If a zero value, it means there is no HSGEAR capability.
1646 * Then, get the maximum gears of PWM speed.
1648 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
1649 if (!pwr_info->gear_rx) {
1650 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
1651 &pwr_info->gear_rx);
1652 if (!pwr_info->gear_rx) {
1653 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
1654 __func__, pwr_info->gear_rx);
1657 pwr_info->pwr_rx = SLOW_MODE;
1660 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
1661 &pwr_info->gear_tx);
1662 if (!pwr_info->gear_tx) {
1663 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
1664 &pwr_info->gear_tx);
1665 if (!pwr_info->gear_tx) {
1666 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
1667 __func__, pwr_info->gear_tx);
1670 pwr_info->pwr_tx = SLOW_MODE;
1673 hba->max_pwr_info.is_valid = true;
1677 static int ufshcd_change_power_mode(struct ufs_hba *hba,
1678 struct ufs_pa_layer_attr *pwr_mode)
1682 /* if already configured to the requested pwr_mode */
1683 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
1684 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
1685 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
1686 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
1687 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
1688 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
1689 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
1690 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
1695 * Configure attributes for power mode change with below.
1696 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
1697 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
1700 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
1701 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
1703 if (pwr_mode->pwr_rx == FASTAUTO_MODE || pwr_mode->pwr_rx == FAST_MODE)
1704 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
1706 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
1708 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
1709 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
1711 if (pwr_mode->pwr_tx == FASTAUTO_MODE || pwr_mode->pwr_tx == FAST_MODE)
1712 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
1714 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
1716 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
1717 pwr_mode->pwr_tx == FASTAUTO_MODE ||
1718 pwr_mode->pwr_rx == FAST_MODE ||
1719 pwr_mode->pwr_tx == FAST_MODE)
1720 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
1723 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 |
1728 "%s: power mode change failed %d\n", __func__, ret);
1733 /* Copy new Power Mode to power info */
1734 memcpy(&hba->pwr_info, pwr_mode, sizeof(struct ufs_pa_layer_attr));
1740 * ufshcd_verify_dev_init() - Verify device initialization
1743 static int ufshcd_verify_dev_init(struct ufs_hba *hba)
1748 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
1749 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
1751 if (!err || err == -ETIMEDOUT)
1754 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
1758 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
1764 * ufshcd_complete_dev_init() - checks device readiness
1766 static int ufshcd_complete_dev_init(struct ufs_hba *hba)
1772 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
1773 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
1776 "%s setting fDeviceInit flag failed with error %d\n",
1781 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
1782 for (i = 0; i < 1000 && !err && flag_res; i++)
1783 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
1784 QUERY_FLAG_IDN_FDEVICEINIT,
1789 "%s reading fDeviceInit flag failed with error %d\n",
1793 "%s fDeviceInit was not cleared by the device\n",
1800 static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
1802 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
1803 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
1804 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
1805 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
1806 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
1807 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
1808 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
1811 int ufs_start(struct ufs_hba *hba)
1813 struct ufs_dev_desc card = {0};
1816 ret = ufshcd_link_startup(hba);
1820 ret = ufshcd_verify_dev_init(hba);
1824 ret = ufshcd_complete_dev_init(hba);
1828 /* Init check for device descriptor sizes */
1829 ufshcd_init_desc_sizes(hba);
1831 ret = ufs_get_device_desc(hba, &card);
1833 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
1839 if (ufshcd_get_max_pwr_mode(hba)) {
1841 "%s: Failed getting max supported power mode\n",
1844 ret = ufshcd_change_power_mode(hba, &hba->max_pwr_info.info);
1846 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
1852 printf("Device at %s up at:", hba->dev->name);
1853 ufshcd_print_pwr_info(hba);
1859 int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
1861 struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev);
1862 struct scsi_platdata *scsi_plat;
1863 struct udevice *scsi_dev;
1866 device_find_first_child(ufs_dev, &scsi_dev);
1870 scsi_plat = dev_get_uclass_platdata(scsi_dev);
1871 scsi_plat->max_id = UFSHCD_MAX_ID;
1872 scsi_plat->max_lun = UFS_MAX_LUNS;
1873 scsi_plat->max_bytes_per_req = UFS_MAX_BYTES;
1877 hba->mmio_base = (void *)dev_read_addr(ufs_dev);
1879 /* Set descriptor lengths to specification defaults */
1880 ufshcd_def_desc_sizes(hba);
1882 ufshcd_ops_init(hba);
1884 /* Read capabilties registers */
1885 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
1887 /* Get UFS version supported by the controller */
1888 hba->version = ufshcd_get_ufs_version(hba);
1889 if (hba->version != UFSHCI_VERSION_10 &&
1890 hba->version != UFSHCI_VERSION_11 &&
1891 hba->version != UFSHCI_VERSION_20 &&
1892 hba->version != UFSHCI_VERSION_21)
1893 dev_err(hba->dev, "invalid UFS version 0x%x\n",
1896 /* Get Interrupt bit mask per version */
1897 hba->intr_mask = ufshcd_get_intr_mask(hba);
1899 /* Allocate memory for host memory space */
1900 err = ufshcd_memory_alloc(hba);
1902 dev_err(hba->dev, "Memory allocation failed\n");
1906 /* Configure Local data structures */
1907 ufshcd_host_memory_configure(hba);
1910 * In order to avoid any spurious interrupt immediately after
1911 * registering UFS controller interrupt handler, clear any pending UFS
1912 * interrupt status and disable all the UFS interrupts.
1914 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
1915 REG_INTERRUPT_STATUS);
1916 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
1918 err = ufshcd_hba_enable(hba);
1920 dev_err(hba->dev, "Host controller enable failed\n");
1924 err = ufs_start(hba);
1931 int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp)
1933 int ret = device_bind_driver(ufs_dev, "ufs_scsi", "ufs_scsi",
1939 static struct scsi_ops ufs_ops = {
1940 .exec = ufs_scsi_exec,
1943 int ufs_probe_dev(int index)
1945 struct udevice *dev;
1947 return uclass_get_device(UCLASS_UFS, index, &dev);
1952 struct udevice *dev;
1956 ret = uclass_get_device(UCLASS_UFS, i, &dev);
1964 U_BOOT_DRIVER(ufs_scsi) = {