1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
9 * based off of the old drivers/char/sh-sci.c by:
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #include <linux/clk.h>
25 #include <linux/console.h>
26 #include <linux/ctype.h>
27 #include <linux/cpufreq.h>
28 #include <linux/delay.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/err.h>
32 #include <linux/errno.h>
33 #include <linux/init.h>
34 #include <linux/interrupt.h>
35 #include <linux/ioport.h>
36 #include <linux/ktime.h>
37 #include <linux/major.h>
38 #include <linux/module.h>
41 #include <linux/of_device.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/scatterlist.h>
45 #include <linux/serial.h>
46 #include <linux/serial_sci.h>
47 #include <linux/sh_dma.h>
48 #include <linux/slab.h>
49 #include <linux/string.h>
50 #include <linux/sysrq.h>
51 #include <linux/timer.h>
52 #include <linux/tty.h>
53 #include <linux/tty_flip.h>
56 #include <asm/sh_bios.h>
59 #include "serial_mctrl_gpio.h"
62 /* Offsets into the sci_port->irqs array */
72 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
75 #define SCIx_IRQ_IS_MUXED(port) \
76 ((port)->irqs[SCIx_ERI_IRQ] == \
77 (port)->irqs[SCIx_RXI_IRQ]) || \
78 ((port)->irqs[SCIx_ERI_IRQ] && \
79 ((port)->irqs[SCIx_RXI_IRQ] < 0))
82 SCI_FCK, /* Functional Clock */
83 SCI_SCK, /* Optional External Clock */
84 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
85 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
89 /* Bit x set means sampling rate x + 1 is supported */
90 #define SCI_SR(x) BIT((x) - 1)
91 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
93 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
94 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
95 SCI_SR(19) | SCI_SR(27)
97 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
98 #define max_sr(_port) fls((_port)->sampling_rate_mask)
100 /* Iterate over all supported sampling rates, from high to low */
101 #define for_each_sr(_sr, _port) \
102 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
103 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
105 struct plat_sci_reg {
109 struct sci_port_params {
110 const struct plat_sci_reg regs[SCIx_NR_REGS];
111 unsigned int fifosize;
112 unsigned int overrun_reg;
113 unsigned int overrun_mask;
114 unsigned int sampling_rate_mask;
115 unsigned int error_mask;
116 unsigned int error_clear;
120 struct uart_port port;
122 /* Platform configuration */
123 const struct sci_port_params *params;
124 const struct plat_sci_port *cfg;
125 unsigned int sampling_rate_mask;
126 resource_size_t reg_size;
127 struct mctrl_gpios *gpios;
130 struct clk *clks[SCI_NUM_CLKS];
131 unsigned long clk_rates[SCI_NUM_CLKS];
133 int irqs[SCIx_NR_IRQS];
134 char *irqstr[SCIx_NR_IRQS];
136 struct dma_chan *chan_tx;
137 struct dma_chan *chan_rx;
139 #ifdef CONFIG_SERIAL_SH_SCI_DMA
140 struct dma_chan *chan_tx_saved;
141 struct dma_chan *chan_rx_saved;
142 dma_cookie_t cookie_tx;
143 dma_cookie_t cookie_rx[2];
144 dma_cookie_t active_rx;
145 dma_addr_t tx_dma_addr;
146 unsigned int tx_dma_len;
147 struct scatterlist sg_rx[2];
150 struct work_struct work_tx;
151 struct hrtimer rx_timer;
152 unsigned int rx_timeout; /* microseconds */
154 unsigned int rx_frame;
156 struct timer_list rx_fifo_timer;
164 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
166 static struct sci_port sci_ports[SCI_NPORTS];
167 static unsigned long sci_ports_in_use;
168 static struct uart_driver sci_uart_driver;
170 static inline struct sci_port *
171 to_sci_port(struct uart_port *uart)
173 return container_of(uart, struct sci_port, port);
176 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
178 * Common SCI definitions, dependent on the port's regshift
181 [SCIx_SCI_REGTYPE] = {
183 [SCSMR] = { 0x00, 8 },
184 [SCBRR] = { 0x01, 8 },
185 [SCSCR] = { 0x02, 8 },
186 [SCxTDR] = { 0x03, 8 },
187 [SCxSR] = { 0x04, 8 },
188 [SCxRDR] = { 0x05, 8 },
191 .overrun_reg = SCxSR,
192 .overrun_mask = SCI_ORER,
193 .sampling_rate_mask = SCI_SR(32),
194 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
195 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
199 * Common definitions for legacy IrDA ports.
201 [SCIx_IRDA_REGTYPE] = {
203 [SCSMR] = { 0x00, 8 },
204 [SCBRR] = { 0x02, 8 },
205 [SCSCR] = { 0x04, 8 },
206 [SCxTDR] = { 0x06, 8 },
207 [SCxSR] = { 0x08, 16 },
208 [SCxRDR] = { 0x0a, 8 },
209 [SCFCR] = { 0x0c, 8 },
210 [SCFDR] = { 0x0e, 16 },
213 .overrun_reg = SCxSR,
214 .overrun_mask = SCI_ORER,
215 .sampling_rate_mask = SCI_SR(32),
216 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
217 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
221 * Common SCIFA definitions.
223 [SCIx_SCIFA_REGTYPE] = {
225 [SCSMR] = { 0x00, 16 },
226 [SCBRR] = { 0x04, 8 },
227 [SCSCR] = { 0x08, 16 },
228 [SCxTDR] = { 0x20, 8 },
229 [SCxSR] = { 0x14, 16 },
230 [SCxRDR] = { 0x24, 8 },
231 [SCFCR] = { 0x18, 16 },
232 [SCFDR] = { 0x1c, 16 },
233 [SCPCR] = { 0x30, 16 },
234 [SCPDR] = { 0x34, 16 },
237 .overrun_reg = SCxSR,
238 .overrun_mask = SCIFA_ORER,
239 .sampling_rate_mask = SCI_SR_SCIFAB,
240 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
241 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
245 * Common SCIFB definitions.
247 [SCIx_SCIFB_REGTYPE] = {
249 [SCSMR] = { 0x00, 16 },
250 [SCBRR] = { 0x04, 8 },
251 [SCSCR] = { 0x08, 16 },
252 [SCxTDR] = { 0x40, 8 },
253 [SCxSR] = { 0x14, 16 },
254 [SCxRDR] = { 0x60, 8 },
255 [SCFCR] = { 0x18, 16 },
256 [SCTFDR] = { 0x38, 16 },
257 [SCRFDR] = { 0x3c, 16 },
258 [SCPCR] = { 0x30, 16 },
259 [SCPDR] = { 0x34, 16 },
262 .overrun_reg = SCxSR,
263 .overrun_mask = SCIFA_ORER,
264 .sampling_rate_mask = SCI_SR_SCIFAB,
265 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
266 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
270 * Common SH-2(A) SCIF definitions for ports with FIFO data
273 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
275 [SCSMR] = { 0x00, 16 },
276 [SCBRR] = { 0x04, 8 },
277 [SCSCR] = { 0x08, 16 },
278 [SCxTDR] = { 0x0c, 8 },
279 [SCxSR] = { 0x10, 16 },
280 [SCxRDR] = { 0x14, 8 },
281 [SCFCR] = { 0x18, 16 },
282 [SCFDR] = { 0x1c, 16 },
283 [SCSPTR] = { 0x20, 16 },
284 [SCLSR] = { 0x24, 16 },
287 .overrun_reg = SCLSR,
288 .overrun_mask = SCLSR_ORER,
289 .sampling_rate_mask = SCI_SR(32),
290 .error_mask = SCIF_DEFAULT_ERROR_MASK,
291 .error_clear = SCIF_ERROR_CLEAR,
295 * The "SCIFA" that is in RZ/T and RZ/A2.
296 * It looks like a normal SCIF with FIFO data, but with a
297 * compressed address space. Also, the break out of interrupts
298 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
300 [SCIx_RZ_SCIFA_REGTYPE] = {
302 [SCSMR] = { 0x00, 16 },
303 [SCBRR] = { 0x02, 8 },
304 [SCSCR] = { 0x04, 16 },
305 [SCxTDR] = { 0x06, 8 },
306 [SCxSR] = { 0x08, 16 },
307 [SCxRDR] = { 0x0A, 8 },
308 [SCFCR] = { 0x0C, 16 },
309 [SCFDR] = { 0x0E, 16 },
310 [SCSPTR] = { 0x10, 16 },
311 [SCLSR] = { 0x12, 16 },
314 .overrun_reg = SCLSR,
315 .overrun_mask = SCLSR_ORER,
316 .sampling_rate_mask = SCI_SR(32),
317 .error_mask = SCIF_DEFAULT_ERROR_MASK,
318 .error_clear = SCIF_ERROR_CLEAR,
322 * Common SH-3 SCIF definitions.
324 [SCIx_SH3_SCIF_REGTYPE] = {
326 [SCSMR] = { 0x00, 8 },
327 [SCBRR] = { 0x02, 8 },
328 [SCSCR] = { 0x04, 8 },
329 [SCxTDR] = { 0x06, 8 },
330 [SCxSR] = { 0x08, 16 },
331 [SCxRDR] = { 0x0a, 8 },
332 [SCFCR] = { 0x0c, 8 },
333 [SCFDR] = { 0x0e, 16 },
336 .overrun_reg = SCLSR,
337 .overrun_mask = SCLSR_ORER,
338 .sampling_rate_mask = SCI_SR(32),
339 .error_mask = SCIF_DEFAULT_ERROR_MASK,
340 .error_clear = SCIF_ERROR_CLEAR,
344 * Common SH-4(A) SCIF(B) definitions.
346 [SCIx_SH4_SCIF_REGTYPE] = {
348 [SCSMR] = { 0x00, 16 },
349 [SCBRR] = { 0x04, 8 },
350 [SCSCR] = { 0x08, 16 },
351 [SCxTDR] = { 0x0c, 8 },
352 [SCxSR] = { 0x10, 16 },
353 [SCxRDR] = { 0x14, 8 },
354 [SCFCR] = { 0x18, 16 },
355 [SCFDR] = { 0x1c, 16 },
356 [SCSPTR] = { 0x20, 16 },
357 [SCLSR] = { 0x24, 16 },
360 .overrun_reg = SCLSR,
361 .overrun_mask = SCLSR_ORER,
362 .sampling_rate_mask = SCI_SR(32),
363 .error_mask = SCIF_DEFAULT_ERROR_MASK,
364 .error_clear = SCIF_ERROR_CLEAR,
368 * Common SCIF definitions for ports with a Baud Rate Generator for
369 * External Clock (BRG).
371 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
373 [SCSMR] = { 0x00, 16 },
374 [SCBRR] = { 0x04, 8 },
375 [SCSCR] = { 0x08, 16 },
376 [SCxTDR] = { 0x0c, 8 },
377 [SCxSR] = { 0x10, 16 },
378 [SCxRDR] = { 0x14, 8 },
379 [SCFCR] = { 0x18, 16 },
380 [SCFDR] = { 0x1c, 16 },
381 [SCSPTR] = { 0x20, 16 },
382 [SCLSR] = { 0x24, 16 },
383 [SCDL] = { 0x30, 16 },
384 [SCCKS] = { 0x34, 16 },
387 .overrun_reg = SCLSR,
388 .overrun_mask = SCLSR_ORER,
389 .sampling_rate_mask = SCI_SR(32),
390 .error_mask = SCIF_DEFAULT_ERROR_MASK,
391 .error_clear = SCIF_ERROR_CLEAR,
395 * Common HSCIF definitions.
397 [SCIx_HSCIF_REGTYPE] = {
399 [SCSMR] = { 0x00, 16 },
400 [SCBRR] = { 0x04, 8 },
401 [SCSCR] = { 0x08, 16 },
402 [SCxTDR] = { 0x0c, 8 },
403 [SCxSR] = { 0x10, 16 },
404 [SCxRDR] = { 0x14, 8 },
405 [SCFCR] = { 0x18, 16 },
406 [SCFDR] = { 0x1c, 16 },
407 [SCSPTR] = { 0x20, 16 },
408 [SCLSR] = { 0x24, 16 },
409 [HSSRR] = { 0x40, 16 },
410 [SCDL] = { 0x30, 16 },
411 [SCCKS] = { 0x34, 16 },
412 [HSRTRGR] = { 0x54, 16 },
413 [HSTTRGR] = { 0x58, 16 },
416 .overrun_reg = SCLSR,
417 .overrun_mask = SCLSR_ORER,
418 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
419 .error_mask = SCIF_DEFAULT_ERROR_MASK,
420 .error_clear = SCIF_ERROR_CLEAR,
424 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
429 [SCSMR] = { 0x00, 16 },
430 [SCBRR] = { 0x04, 8 },
431 [SCSCR] = { 0x08, 16 },
432 [SCxTDR] = { 0x0c, 8 },
433 [SCxSR] = { 0x10, 16 },
434 [SCxRDR] = { 0x14, 8 },
435 [SCFCR] = { 0x18, 16 },
436 [SCFDR] = { 0x1c, 16 },
437 [SCLSR] = { 0x24, 16 },
440 .overrun_reg = SCLSR,
441 .overrun_mask = SCLSR_ORER,
442 .sampling_rate_mask = SCI_SR(32),
443 .error_mask = SCIF_DEFAULT_ERROR_MASK,
444 .error_clear = SCIF_ERROR_CLEAR,
448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
453 [SCSMR] = { 0x00, 16 },
454 [SCBRR] = { 0x04, 8 },
455 [SCSCR] = { 0x08, 16 },
456 [SCxTDR] = { 0x0c, 8 },
457 [SCxSR] = { 0x10, 16 },
458 [SCxRDR] = { 0x14, 8 },
459 [SCFCR] = { 0x18, 16 },
460 [SCFDR] = { 0x1c, 16 },
461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
462 [SCRFDR] = { 0x20, 16 },
463 [SCSPTR] = { 0x24, 16 },
464 [SCLSR] = { 0x28, 16 },
467 .overrun_reg = SCLSR,
468 .overrun_mask = SCLSR_ORER,
469 .sampling_rate_mask = SCI_SR(32),
470 .error_mask = SCIF_DEFAULT_ERROR_MASK,
471 .error_clear = SCIF_ERROR_CLEAR,
475 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
478 [SCIx_SH7705_SCIF_REGTYPE] = {
480 [SCSMR] = { 0x00, 16 },
481 [SCBRR] = { 0x04, 8 },
482 [SCSCR] = { 0x08, 16 },
483 [SCxTDR] = { 0x20, 8 },
484 [SCxSR] = { 0x14, 16 },
485 [SCxRDR] = { 0x24, 8 },
486 [SCFCR] = { 0x18, 16 },
487 [SCFDR] = { 0x1c, 16 },
490 .overrun_reg = SCxSR,
491 .overrun_mask = SCIFA_ORER,
492 .sampling_rate_mask = SCI_SR(16),
493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
498 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
501 * The "offset" here is rather misleading, in that it refers to an enum
502 * value relative to the port mapping rather than the fixed offset
503 * itself, which needs to be manually retrieved from the platform's
504 * register map for the given port.
506 static unsigned int sci_serial_in(struct uart_port *p, int offset)
508 const struct plat_sci_reg *reg = sci_getreg(p, offset);
511 return ioread8(p->membase + (reg->offset << p->regshift));
512 else if (reg->size == 16)
513 return ioread16(p->membase + (reg->offset << p->regshift));
515 WARN(1, "Invalid register access\n");
520 static void sci_serial_out(struct uart_port *p, int offset, int value)
522 const struct plat_sci_reg *reg = sci_getreg(p, offset);
525 iowrite8(value, p->membase + (reg->offset << p->regshift));
526 else if (reg->size == 16)
527 iowrite16(value, p->membase + (reg->offset << p->regshift));
529 WARN(1, "Invalid register access\n");
532 static void sci_port_enable(struct sci_port *sci_port)
536 if (!sci_port->port.dev)
539 pm_runtime_get_sync(sci_port->port.dev);
541 for (i = 0; i < SCI_NUM_CLKS; i++) {
542 clk_prepare_enable(sci_port->clks[i]);
543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
548 static void sci_port_disable(struct sci_port *sci_port)
552 if (!sci_port->port.dev)
555 for (i = SCI_NUM_CLKS; i-- > 0; )
556 clk_disable_unprepare(sci_port->clks[i]);
558 pm_runtime_put_sync(sci_port->port.dev);
561 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
564 * Not all ports (such as SCIFA) will support REIE. Rather than
565 * special-casing the port type, we check the port initialization
566 * IRQ enable mask to see whether the IRQ is desired at all. If
567 * it's unset, it's logically inferred that there's no point in
570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
573 static void sci_start_tx(struct uart_port *port)
575 struct sci_port *s = to_sci_port(port);
578 #ifdef CONFIG_SERIAL_SH_SCI_DMA
579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
580 u16 new, scr = serial_port_in(port, SCSCR);
582 new = scr | SCSCR_TDRQE;
584 new = scr & ~SCSCR_TDRQE;
586 serial_port_out(port, SCSCR, new);
589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
590 dma_submit_error(s->cookie_tx)) {
592 schedule_work(&s->work_tx);
596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
598 ctrl = serial_port_in(port, SCSCR);
599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
603 static void sci_stop_tx(struct uart_port *port)
607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
608 ctrl = serial_port_in(port, SCSCR);
610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
611 ctrl &= ~SCSCR_TDRQE;
615 serial_port_out(port, SCSCR, ctrl);
618 static void sci_start_rx(struct uart_port *port)
622 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
625 ctrl &= ~SCSCR_RDRQE;
627 serial_port_out(port, SCSCR, ctrl);
630 static void sci_stop_rx(struct uart_port *port)
634 ctrl = serial_port_in(port, SCSCR);
636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
637 ctrl &= ~SCSCR_RDRQE;
639 ctrl &= ~port_rx_irq_mask(port);
641 serial_port_out(port, SCSCR, ctrl);
644 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
646 if (port->type == PORT_SCI) {
647 /* Just store the mask */
648 serial_port_out(port, SCxSR, mask);
649 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
650 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
651 /* Only clear the status bits we want to clear */
652 serial_port_out(port, SCxSR,
653 serial_port_in(port, SCxSR) & mask);
655 /* Store the mask, clear parity/framing errors */
656 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
660 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
661 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
663 #ifdef CONFIG_CONSOLE_POLL
664 static int sci_poll_get_char(struct uart_port *port)
666 unsigned short status;
670 status = serial_port_in(port, SCxSR);
671 if (status & SCxSR_ERRORS(port)) {
672 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
678 if (!(status & SCxSR_RDxF(port)))
681 c = serial_port_in(port, SCxRDR);
684 serial_port_in(port, SCxSR);
685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
691 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
693 unsigned short status;
696 status = serial_port_in(port, SCxSR);
697 } while (!(status & SCxSR_TDxE(port)));
699 serial_port_out(port, SCxTDR, c);
700 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
702 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
703 CONFIG_SERIAL_SH_SCI_EARLYCON */
705 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
707 struct sci_port *s = to_sci_port(port);
710 * Use port-specific handler if provided.
712 if (s->cfg->ops && s->cfg->ops->init_pins) {
713 s->cfg->ops->init_pins(port, cflag);
717 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
718 u16 data = serial_port_in(port, SCPDR);
719 u16 ctrl = serial_port_in(port, SCPCR);
721 /* Enable RXD and TXD pin functions */
722 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
723 if (to_sci_port(port)->has_rtscts) {
724 /* RTS# is output, active low, unless autorts */
725 if (!(port->mctrl & TIOCM_RTS)) {
728 } else if (!s->autorts) {
732 /* Enable RTS# pin function */
735 /* Enable CTS# pin function */
738 serial_port_out(port, SCPDR, data);
739 serial_port_out(port, SCPCR, ctrl);
740 } else if (sci_getreg(port, SCSPTR)->size) {
741 u16 status = serial_port_in(port, SCSPTR);
743 /* RTS# is always output; and active low, unless autorts */
744 status |= SCSPTR_RTSIO;
745 if (!(port->mctrl & TIOCM_RTS))
746 status |= SCSPTR_RTSDT;
747 else if (!s->autorts)
748 status &= ~SCSPTR_RTSDT;
749 /* CTS# and SCK are inputs */
750 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
751 serial_port_out(port, SCSPTR, status);
755 static int sci_txfill(struct uart_port *port)
757 struct sci_port *s = to_sci_port(port);
758 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
759 const struct plat_sci_reg *reg;
761 reg = sci_getreg(port, SCTFDR);
763 return serial_port_in(port, SCTFDR) & fifo_mask;
765 reg = sci_getreg(port, SCFDR);
767 return serial_port_in(port, SCFDR) >> 8;
769 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
772 static int sci_txroom(struct uart_port *port)
774 return port->fifosize - sci_txfill(port);
777 static int sci_rxfill(struct uart_port *port)
779 struct sci_port *s = to_sci_port(port);
780 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
781 const struct plat_sci_reg *reg;
783 reg = sci_getreg(port, SCRFDR);
785 return serial_port_in(port, SCRFDR) & fifo_mask;
787 reg = sci_getreg(port, SCFDR);
789 return serial_port_in(port, SCFDR) & fifo_mask;
791 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
794 /* ********************************************************************** *
795 * the interrupt related routines *
796 * ********************************************************************** */
798 static void sci_transmit_chars(struct uart_port *port)
800 struct circ_buf *xmit = &port->state->xmit;
801 unsigned int stopped = uart_tx_stopped(port);
802 unsigned short status;
806 status = serial_port_in(port, SCxSR);
807 if (!(status & SCxSR_TDxE(port))) {
808 ctrl = serial_port_in(port, SCSCR);
809 if (uart_circ_empty(xmit))
813 serial_port_out(port, SCSCR, ctrl);
817 count = sci_txroom(port);
825 } else if (!uart_circ_empty(xmit) && !stopped) {
826 c = xmit->buf[xmit->tail];
827 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
832 serial_port_out(port, SCxTDR, c);
835 } while (--count > 0);
837 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
839 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
840 uart_write_wakeup(port);
841 if (uart_circ_empty(xmit))
846 /* On SH3, SCIF may read end-of-break as a space->mark char */
847 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
849 static void sci_receive_chars(struct uart_port *port)
851 struct tty_port *tport = &port->state->port;
852 int i, count, copied = 0;
853 unsigned short status;
856 status = serial_port_in(port, SCxSR);
857 if (!(status & SCxSR_RDxF(port)))
861 /* Don't copy more bytes than there is room for in the buffer */
862 count = tty_buffer_request_room(tport, sci_rxfill(port));
864 /* If for any reason we can't copy more data, we're done! */
868 if (port->type == PORT_SCI) {
869 char c = serial_port_in(port, SCxRDR);
870 if (uart_handle_sysrq_char(port, c))
873 tty_insert_flip_char(tport, c, TTY_NORMAL);
875 for (i = 0; i < count; i++) {
876 char c = serial_port_in(port, SCxRDR);
878 status = serial_port_in(port, SCxSR);
879 if (uart_handle_sysrq_char(port, c)) {
884 /* Store data and status */
885 if (status & SCxSR_FER(port)) {
887 port->icount.frame++;
888 dev_notice(port->dev, "frame error\n");
889 } else if (status & SCxSR_PER(port)) {
891 port->icount.parity++;
892 dev_notice(port->dev, "parity error\n");
896 tty_insert_flip_char(tport, c, flag);
900 serial_port_in(port, SCxSR); /* dummy read */
901 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
904 port->icount.rx += count;
908 /* Tell the rest of the system the news. New characters! */
909 tty_flip_buffer_push(tport);
911 /* TTY buffers full; read from RX reg to prevent lockup */
912 serial_port_in(port, SCxRDR);
913 serial_port_in(port, SCxSR); /* dummy read */
914 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
918 static int sci_handle_errors(struct uart_port *port)
921 unsigned short status = serial_port_in(port, SCxSR);
922 struct tty_port *tport = &port->state->port;
923 struct sci_port *s = to_sci_port(port);
925 /* Handle overruns */
926 if (status & s->params->overrun_mask) {
927 port->icount.overrun++;
930 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
933 dev_notice(port->dev, "overrun error\n");
936 if (status & SCxSR_FER(port)) {
938 port->icount.frame++;
940 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
943 dev_notice(port->dev, "frame error\n");
946 if (status & SCxSR_PER(port)) {
948 port->icount.parity++;
950 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
953 dev_notice(port->dev, "parity error\n");
957 tty_flip_buffer_push(tport);
962 static int sci_handle_fifo_overrun(struct uart_port *port)
964 struct tty_port *tport = &port->state->port;
965 struct sci_port *s = to_sci_port(port);
966 const struct plat_sci_reg *reg;
970 reg = sci_getreg(port, s->params->overrun_reg);
974 status = serial_port_in(port, s->params->overrun_reg);
975 if (status & s->params->overrun_mask) {
976 status &= ~s->params->overrun_mask;
977 serial_port_out(port, s->params->overrun_reg, status);
979 port->icount.overrun++;
981 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
982 tty_flip_buffer_push(tport);
984 dev_dbg(port->dev, "overrun error\n");
991 static int sci_handle_breaks(struct uart_port *port)
994 unsigned short status = serial_port_in(port, SCxSR);
995 struct tty_port *tport = &port->state->port;
997 if (uart_handle_break(port))
1000 if (status & SCxSR_BRK(port)) {
1003 /* Notify of BREAK */
1004 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1007 dev_dbg(port->dev, "BREAK detected\n");
1011 tty_flip_buffer_push(tport);
1013 copied += sci_handle_fifo_overrun(port);
1018 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1024 if (rx_trig >= port->fifosize)
1025 rx_trig = port->fifosize;
1027 /* HSCIF can be set to an arbitrary level. */
1028 if (sci_getreg(port, HSRTRGR)->size) {
1029 serial_port_out(port, HSRTRGR, rx_trig);
1033 switch (port->type) {
1038 } else if (rx_trig < 8) {
1041 } else if (rx_trig < 14) {
1045 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1054 } else if (rx_trig < 32) {
1057 } else if (rx_trig < 48) {
1061 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1066 WARN(1, "unknown FIFO configuration");
1070 serial_port_out(port, SCFCR,
1071 (serial_port_in(port, SCFCR) &
1072 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1077 static int scif_rtrg_enabled(struct uart_port *port)
1079 if (sci_getreg(port, HSRTRGR)->size)
1080 return serial_port_in(port, HSRTRGR) != 0;
1082 return (serial_port_in(port, SCFCR) &
1083 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1086 static void rx_fifo_timer_fn(struct timer_list *t)
1088 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1089 struct uart_port *port = &s->port;
1091 dev_dbg(port->dev, "Rx timed out\n");
1092 scif_set_rtrg(port, 1);
1095 static ssize_t rx_trigger_show(struct device *dev,
1096 struct device_attribute *attr,
1099 struct uart_port *port = dev_get_drvdata(dev);
1100 struct sci_port *sci = to_sci_port(port);
1102 return sprintf(buf, "%d\n", sci->rx_trigger);
1105 static ssize_t rx_trigger_store(struct device *dev,
1106 struct device_attribute *attr,
1110 struct uart_port *port = dev_get_drvdata(dev);
1111 struct sci_port *sci = to_sci_port(port);
1115 ret = kstrtol(buf, 0, &r);
1119 sci->rx_trigger = scif_set_rtrg(port, r);
1120 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1121 scif_set_rtrg(port, 1);
1126 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1128 static ssize_t rx_fifo_timeout_show(struct device *dev,
1129 struct device_attribute *attr,
1132 struct uart_port *port = dev_get_drvdata(dev);
1133 struct sci_port *sci = to_sci_port(port);
1136 if (port->type == PORT_HSCIF)
1137 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1139 v = sci->rx_fifo_timeout;
1141 return sprintf(buf, "%d\n", v);
1144 static ssize_t rx_fifo_timeout_store(struct device *dev,
1145 struct device_attribute *attr,
1149 struct uart_port *port = dev_get_drvdata(dev);
1150 struct sci_port *sci = to_sci_port(port);
1154 ret = kstrtol(buf, 0, &r);
1158 if (port->type == PORT_HSCIF) {
1161 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1163 sci->rx_fifo_timeout = r;
1164 scif_set_rtrg(port, 1);
1166 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1172 static DEVICE_ATTR_RW(rx_fifo_timeout);
1175 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1176 static void sci_dma_tx_complete(void *arg)
1178 struct sci_port *s = arg;
1179 struct uart_port *port = &s->port;
1180 struct circ_buf *xmit = &port->state->xmit;
1181 unsigned long flags;
1183 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1185 spin_lock_irqsave(&port->lock, flags);
1187 xmit->tail += s->tx_dma_len;
1188 xmit->tail &= UART_XMIT_SIZE - 1;
1190 port->icount.tx += s->tx_dma_len;
1192 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1193 uart_write_wakeup(port);
1195 if (!uart_circ_empty(xmit)) {
1197 schedule_work(&s->work_tx);
1199 s->cookie_tx = -EINVAL;
1200 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1201 u16 ctrl = serial_port_in(port, SCSCR);
1202 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1206 spin_unlock_irqrestore(&port->lock, flags);
1209 /* Locking: called with port lock held */
1210 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1212 struct uart_port *port = &s->port;
1213 struct tty_port *tport = &port->state->port;
1216 copied = tty_insert_flip_string(tport, buf, count);
1218 port->icount.buf_overrun++;
1220 port->icount.rx += copied;
1225 static int sci_dma_rx_find_active(struct sci_port *s)
1229 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1230 if (s->active_rx == s->cookie_rx[i])
1236 static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1241 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1242 s->cookie_rx[i] = -EINVAL;
1246 static void sci_dma_rx_release(struct sci_port *s)
1248 struct dma_chan *chan = s->chan_rx_saved;
1250 s->chan_rx_saved = NULL;
1251 sci_dma_rx_chan_invalidate(s);
1252 dmaengine_terminate_sync(chan);
1253 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1254 sg_dma_address(&s->sg_rx[0]));
1255 dma_release_channel(chan);
1258 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1260 long sec = usec / 1000000;
1261 long nsec = (usec % 1000000) * 1000;
1262 ktime_t t = ktime_set(sec, nsec);
1264 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1267 static void sci_dma_rx_reenable_irq(struct sci_port *s)
1269 struct uart_port *port = &s->port;
1272 /* Direct new serial port interrupts back to CPU */
1273 scr = serial_port_in(port, SCSCR);
1274 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1275 scr &= ~SCSCR_RDRQE;
1276 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1278 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1281 static void sci_dma_rx_complete(void *arg)
1283 struct sci_port *s = arg;
1284 struct dma_chan *chan = s->chan_rx;
1285 struct uart_port *port = &s->port;
1286 struct dma_async_tx_descriptor *desc;
1287 unsigned long flags;
1288 int active, count = 0;
1290 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1293 spin_lock_irqsave(&port->lock, flags);
1295 active = sci_dma_rx_find_active(s);
1297 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1299 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1302 tty_flip_buffer_push(&port->state->port);
1304 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1306 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1310 desc->callback = sci_dma_rx_complete;
1311 desc->callback_param = s;
1312 s->cookie_rx[active] = dmaengine_submit(desc);
1313 if (dma_submit_error(s->cookie_rx[active]))
1316 s->active_rx = s->cookie_rx[!active];
1318 dma_async_issue_pending(chan);
1320 spin_unlock_irqrestore(&port->lock, flags);
1321 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1322 __func__, s->cookie_rx[active], active, s->active_rx);
1326 spin_unlock_irqrestore(&port->lock, flags);
1327 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1329 spin_lock_irqsave(&port->lock, flags);
1330 dmaengine_terminate_async(chan);
1331 sci_dma_rx_chan_invalidate(s);
1332 sci_dma_rx_reenable_irq(s);
1333 spin_unlock_irqrestore(&port->lock, flags);
1336 static void sci_dma_tx_release(struct sci_port *s)
1338 struct dma_chan *chan = s->chan_tx_saved;
1340 cancel_work_sync(&s->work_tx);
1341 s->chan_tx_saved = s->chan_tx = NULL;
1342 s->cookie_tx = -EINVAL;
1343 dmaengine_terminate_sync(chan);
1344 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1346 dma_release_channel(chan);
1349 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1351 struct dma_chan *chan = s->chan_rx;
1352 struct uart_port *port = &s->port;
1353 unsigned long flags;
1356 for (i = 0; i < 2; i++) {
1357 struct scatterlist *sg = &s->sg_rx[i];
1358 struct dma_async_tx_descriptor *desc;
1360 desc = dmaengine_prep_slave_sg(chan,
1361 sg, 1, DMA_DEV_TO_MEM,
1362 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1366 desc->callback = sci_dma_rx_complete;
1367 desc->callback_param = s;
1368 s->cookie_rx[i] = dmaengine_submit(desc);
1369 if (dma_submit_error(s->cookie_rx[i]))
1374 s->active_rx = s->cookie_rx[0];
1376 dma_async_issue_pending(chan);
1381 if (!port_lock_held)
1382 spin_lock_irqsave(&port->lock, flags);
1384 dmaengine_terminate_async(chan);
1385 sci_dma_rx_chan_invalidate(s);
1387 if (!port_lock_held)
1388 spin_unlock_irqrestore(&port->lock, flags);
1392 static void sci_dma_tx_work_fn(struct work_struct *work)
1394 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1395 struct dma_async_tx_descriptor *desc;
1396 struct dma_chan *chan = s->chan_tx;
1397 struct uart_port *port = &s->port;
1398 struct circ_buf *xmit = &port->state->xmit;
1399 unsigned long flags;
1405 * Port xmit buffer is already mapped, and it is one page... Just adjust
1406 * offsets and lengths. Since it is a circular buffer, we have to
1407 * transmit till the end, and then the rest. Take the port lock to get a
1408 * consistent xmit buffer state.
1410 spin_lock_irq(&port->lock);
1413 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1));
1414 s->tx_dma_len = min_t(unsigned int,
1415 CIRC_CNT(head, tail, UART_XMIT_SIZE),
1416 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE));
1417 if (!s->tx_dma_len) {
1418 /* Transmit buffer has been flushed */
1419 spin_unlock_irq(&port->lock);
1423 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1425 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1427 spin_unlock_irq(&port->lock);
1428 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1432 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1435 desc->callback = sci_dma_tx_complete;
1436 desc->callback_param = s;
1437 s->cookie_tx = dmaengine_submit(desc);
1438 if (dma_submit_error(s->cookie_tx)) {
1439 spin_unlock_irq(&port->lock);
1440 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1444 spin_unlock_irq(&port->lock);
1445 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1446 __func__, xmit->buf, tail, head, s->cookie_tx);
1448 dma_async_issue_pending(chan);
1452 spin_lock_irqsave(&port->lock, flags);
1455 spin_unlock_irqrestore(&port->lock, flags);
1459 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1461 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1462 struct dma_chan *chan = s->chan_rx;
1463 struct uart_port *port = &s->port;
1464 struct dma_tx_state state;
1465 enum dma_status status;
1466 unsigned long flags;
1470 dev_dbg(port->dev, "DMA Rx timed out\n");
1472 spin_lock_irqsave(&port->lock, flags);
1474 active = sci_dma_rx_find_active(s);
1476 spin_unlock_irqrestore(&port->lock, flags);
1477 return HRTIMER_NORESTART;
1480 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1481 if (status == DMA_COMPLETE) {
1482 spin_unlock_irqrestore(&port->lock, flags);
1483 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1484 s->active_rx, active);
1486 /* Let packet complete handler take care of the packet */
1487 return HRTIMER_NORESTART;
1490 dmaengine_pause(chan);
1493 * sometimes DMA transfer doesn't stop even if it is stopped and
1494 * data keeps on coming until transaction is complete so check
1495 * for DMA_COMPLETE again
1496 * Let packet complete handler take care of the packet
1498 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1499 if (status == DMA_COMPLETE) {
1500 spin_unlock_irqrestore(&port->lock, flags);
1501 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1502 return HRTIMER_NORESTART;
1505 /* Handle incomplete DMA receive */
1506 dmaengine_terminate_async(s->chan_rx);
1507 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1510 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1512 tty_flip_buffer_push(&port->state->port);
1515 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1516 sci_dma_rx_submit(s, true);
1518 sci_dma_rx_reenable_irq(s);
1520 spin_unlock_irqrestore(&port->lock, flags);
1522 return HRTIMER_NORESTART;
1525 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1526 enum dma_transfer_direction dir)
1528 struct dma_chan *chan;
1529 struct dma_slave_config cfg;
1532 chan = dma_request_slave_channel(port->dev,
1533 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1535 dev_dbg(port->dev, "dma_request_slave_channel failed\n");
1539 memset(&cfg, 0, sizeof(cfg));
1540 cfg.direction = dir;
1541 if (dir == DMA_MEM_TO_DEV) {
1542 cfg.dst_addr = port->mapbase +
1543 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1544 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1546 cfg.src_addr = port->mapbase +
1547 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1548 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1551 ret = dmaengine_slave_config(chan, &cfg);
1553 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1554 dma_release_channel(chan);
1561 static void sci_request_dma(struct uart_port *port)
1563 struct sci_port *s = to_sci_port(port);
1564 struct dma_chan *chan;
1566 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1569 * DMA on console may interfere with Kernel log messages which use
1570 * plain putchar(). So, simply don't use it with a console.
1572 if (uart_console(port))
1575 if (!port->dev->of_node)
1578 s->cookie_tx = -EINVAL;
1581 * Don't request a dma channel if no channel was specified
1582 * in the device tree.
1584 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1587 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1588 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1590 /* UART circular tx buffer is an aligned page. */
1591 s->tx_dma_addr = dma_map_single(chan->device->dev,
1592 port->state->xmit.buf,
1595 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1596 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1597 dma_release_channel(chan);
1599 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1600 __func__, UART_XMIT_SIZE,
1601 port->state->xmit.buf, &s->tx_dma_addr);
1603 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1604 s->chan_tx_saved = s->chan_tx = chan;
1608 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1609 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1615 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1616 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1620 "Failed to allocate Rx dma buffer, using PIO\n");
1621 dma_release_channel(chan);
1625 for (i = 0; i < 2; i++) {
1626 struct scatterlist *sg = &s->sg_rx[i];
1628 sg_init_table(sg, 1);
1630 sg_dma_address(sg) = dma;
1631 sg_dma_len(sg) = s->buf_len_rx;
1633 buf += s->buf_len_rx;
1634 dma += s->buf_len_rx;
1637 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1638 s->rx_timer.function = sci_dma_rx_timer_fn;
1640 s->chan_rx_saved = s->chan_rx = chan;
1642 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1643 sci_dma_rx_submit(s, false);
1647 static void sci_free_dma(struct uart_port *port)
1649 struct sci_port *s = to_sci_port(port);
1651 if (s->chan_tx_saved)
1652 sci_dma_tx_release(s);
1653 if (s->chan_rx_saved)
1654 sci_dma_rx_release(s);
1657 static void sci_flush_buffer(struct uart_port *port)
1659 struct sci_port *s = to_sci_port(port);
1662 * In uart_flush_buffer(), the xmit circular buffer has just been
1663 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1668 dmaengine_terminate_async(s->chan_tx);
1669 s->cookie_tx = -EINVAL;
1672 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
1673 static inline void sci_request_dma(struct uart_port *port)
1677 static inline void sci_free_dma(struct uart_port *port)
1681 #define sci_flush_buffer NULL
1682 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1684 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1686 struct uart_port *port = ptr;
1687 struct sci_port *s = to_sci_port(port);
1689 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1691 u16 scr = serial_port_in(port, SCSCR);
1692 u16 ssr = serial_port_in(port, SCxSR);
1694 /* Disable future Rx interrupts */
1695 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1696 disable_irq_nosync(irq);
1699 if (sci_dma_rx_submit(s, false) < 0)
1704 serial_port_out(port, SCSCR, scr);
1705 /* Clear current interrupt */
1706 serial_port_out(port, SCxSR,
1707 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1708 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1709 jiffies, s->rx_timeout);
1710 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1718 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1719 if (!scif_rtrg_enabled(port))
1720 scif_set_rtrg(port, s->rx_trigger);
1722 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1723 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1726 /* I think sci_receive_chars has to be called irrespective
1727 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1730 sci_receive_chars(port);
1735 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1737 struct uart_port *port = ptr;
1738 unsigned long flags;
1740 spin_lock_irqsave(&port->lock, flags);
1741 sci_transmit_chars(port);
1742 spin_unlock_irqrestore(&port->lock, flags);
1747 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1749 struct uart_port *port = ptr;
1752 sci_handle_breaks(port);
1753 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1758 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1760 struct uart_port *port = ptr;
1761 struct sci_port *s = to_sci_port(port);
1763 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1764 /* Break and Error interrupts are muxed */
1765 unsigned short ssr_status = serial_port_in(port, SCxSR);
1767 /* Break Interrupt */
1768 if (ssr_status & SCxSR_BRK(port))
1769 sci_br_interrupt(irq, ptr);
1772 if (!(ssr_status & SCxSR_ERRORS(port)))
1777 if (port->type == PORT_SCI) {
1778 if (sci_handle_errors(port)) {
1779 /* discard character in rx buffer */
1780 serial_port_in(port, SCxSR);
1781 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1784 sci_handle_fifo_overrun(port);
1786 sci_receive_chars(port);
1789 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1791 /* Kick the transmission */
1793 sci_tx_interrupt(irq, ptr);
1798 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1800 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1801 struct uart_port *port = ptr;
1802 struct sci_port *s = to_sci_port(port);
1803 irqreturn_t ret = IRQ_NONE;
1805 ssr_status = serial_port_in(port, SCxSR);
1806 scr_status = serial_port_in(port, SCSCR);
1807 if (s->params->overrun_reg == SCxSR)
1808 orer_status = ssr_status;
1809 else if (sci_getreg(port, s->params->overrun_reg)->size)
1810 orer_status = serial_port_in(port, s->params->overrun_reg);
1812 err_enabled = scr_status & port_rx_irq_mask(port);
1815 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1817 ret = sci_tx_interrupt(irq, ptr);
1820 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1823 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1824 (scr_status & SCSCR_RIE))
1825 ret = sci_rx_interrupt(irq, ptr);
1827 /* Error Interrupt */
1828 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1829 ret = sci_er_interrupt(irq, ptr);
1831 /* Break Interrupt */
1832 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1833 ret = sci_br_interrupt(irq, ptr);
1835 /* Overrun Interrupt */
1836 if (orer_status & s->params->overrun_mask) {
1837 sci_handle_fifo_overrun(port);
1844 static const struct sci_irq_desc {
1846 irq_handler_t handler;
1847 } sci_irq_desc[] = {
1849 * Split out handlers, the default case.
1853 .handler = sci_er_interrupt,
1858 .handler = sci_rx_interrupt,
1863 .handler = sci_tx_interrupt,
1868 .handler = sci_br_interrupt,
1873 .handler = sci_rx_interrupt,
1878 .handler = sci_tx_interrupt,
1882 * Special muxed handler.
1886 .handler = sci_mpxed_interrupt,
1890 static int sci_request_irq(struct sci_port *port)
1892 struct uart_port *up = &port->port;
1893 int i, j, w, ret = 0;
1895 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1896 const struct sci_irq_desc *desc;
1899 /* Check if already registered (muxed) */
1900 for (w = 0; w < i; w++)
1901 if (port->irqs[w] == port->irqs[i])
1906 if (SCIx_IRQ_IS_MUXED(port)) {
1910 irq = port->irqs[i];
1913 * Certain port types won't support all of the
1914 * available interrupt sources.
1916 if (unlikely(irq < 0))
1920 desc = sci_irq_desc + i;
1921 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1922 dev_name(up->dev), desc->desc);
1923 if (!port->irqstr[j]) {
1928 ret = request_irq(irq, desc->handler, up->irqflags,
1929 port->irqstr[j], port);
1930 if (unlikely(ret)) {
1931 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1940 free_irq(port->irqs[i], port);
1944 kfree(port->irqstr[j]);
1949 static void sci_free_irq(struct sci_port *port)
1954 * Intentionally in reverse order so we iterate over the muxed
1957 for (i = 0; i < SCIx_NR_IRQS; i++) {
1958 int irq = port->irqs[i];
1961 * Certain port types won't support all of the available
1962 * interrupt sources.
1964 if (unlikely(irq < 0))
1967 /* Check if already freed (irq was muxed) */
1968 for (j = 0; j < i; j++)
1969 if (port->irqs[j] == irq)
1974 free_irq(port->irqs[i], port);
1975 kfree(port->irqstr[i]);
1977 if (SCIx_IRQ_IS_MUXED(port)) {
1978 /* If there's only one IRQ, we're done. */
1984 static unsigned int sci_tx_empty(struct uart_port *port)
1986 unsigned short status = serial_port_in(port, SCxSR);
1987 unsigned short in_tx_fifo = sci_txfill(port);
1989 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1992 static void sci_set_rts(struct uart_port *port, bool state)
1994 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1995 u16 data = serial_port_in(port, SCPDR);
1999 data &= ~SCPDR_RTSD;
2002 serial_port_out(port, SCPDR, data);
2004 /* RTS# is output */
2005 serial_port_out(port, SCPCR,
2006 serial_port_in(port, SCPCR) | SCPCR_RTSC);
2007 } else if (sci_getreg(port, SCSPTR)->size) {
2008 u16 ctrl = serial_port_in(port, SCSPTR);
2012 ctrl &= ~SCSPTR_RTSDT;
2014 ctrl |= SCSPTR_RTSDT;
2015 serial_port_out(port, SCSPTR, ctrl);
2019 static bool sci_get_cts(struct uart_port *port)
2021 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2023 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2024 } else if (sci_getreg(port, SCSPTR)->size) {
2026 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2033 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2034 * CTS/RTS is supported in hardware by at least one port and controlled
2035 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2036 * handled via the ->init_pins() op, which is a bit of a one-way street,
2037 * lacking any ability to defer pin control -- this will later be
2038 * converted over to the GPIO framework).
2040 * Other modes (such as loopback) are supported generically on certain
2041 * port types, but not others. For these it's sufficient to test for the
2042 * existence of the support register and simply ignore the port type.
2044 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2046 struct sci_port *s = to_sci_port(port);
2048 if (mctrl & TIOCM_LOOP) {
2049 const struct plat_sci_reg *reg;
2052 * Standard loopback mode for SCFCR ports.
2054 reg = sci_getreg(port, SCFCR);
2056 serial_port_out(port, SCFCR,
2057 serial_port_in(port, SCFCR) |
2061 mctrl_gpio_set(s->gpios, mctrl);
2066 if (!(mctrl & TIOCM_RTS)) {
2067 /* Disable Auto RTS */
2068 serial_port_out(port, SCFCR,
2069 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2072 sci_set_rts(port, 0);
2073 } else if (s->autorts) {
2074 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2075 /* Enable RTS# pin function */
2076 serial_port_out(port, SCPCR,
2077 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2080 /* Enable Auto RTS */
2081 serial_port_out(port, SCFCR,
2082 serial_port_in(port, SCFCR) | SCFCR_MCE);
2085 sci_set_rts(port, 1);
2089 static unsigned int sci_get_mctrl(struct uart_port *port)
2091 struct sci_port *s = to_sci_port(port);
2092 struct mctrl_gpios *gpios = s->gpios;
2093 unsigned int mctrl = 0;
2095 mctrl_gpio_get(gpios, &mctrl);
2098 * CTS/RTS is handled in hardware when supported, while nothing
2102 if (sci_get_cts(port))
2104 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
2107 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
2109 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
2115 static void sci_enable_ms(struct uart_port *port)
2117 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2120 static void sci_break_ctl(struct uart_port *port, int break_state)
2122 unsigned short scscr, scsptr;
2123 unsigned long flags;
2125 /* check wheter the port has SCSPTR */
2126 if (!sci_getreg(port, SCSPTR)->size) {
2128 * Not supported by hardware. Most parts couple break and rx
2129 * interrupts together, with break detection always enabled.
2134 spin_lock_irqsave(&port->lock, flags);
2135 scsptr = serial_port_in(port, SCSPTR);
2136 scscr = serial_port_in(port, SCSCR);
2138 if (break_state == -1) {
2139 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2142 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2146 serial_port_out(port, SCSPTR, scsptr);
2147 serial_port_out(port, SCSCR, scscr);
2148 spin_unlock_irqrestore(&port->lock, flags);
2151 static int sci_startup(struct uart_port *port)
2153 struct sci_port *s = to_sci_port(port);
2156 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2158 sci_request_dma(port);
2160 ret = sci_request_irq(s);
2161 if (unlikely(ret < 0)) {
2169 static void sci_shutdown(struct uart_port *port)
2171 struct sci_port *s = to_sci_port(port);
2172 unsigned long flags;
2175 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2178 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2180 spin_lock_irqsave(&port->lock, flags);
2184 * Stop RX and TX, disable related interrupts, keep clock source
2185 * and HSCIF TOT bits
2187 scr = serial_port_in(port, SCSCR);
2188 serial_port_out(port, SCSCR, scr &
2189 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2190 spin_unlock_irqrestore(&port->lock, flags);
2192 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2193 if (s->chan_rx_saved) {
2194 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2196 hrtimer_cancel(&s->rx_timer);
2200 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2201 del_timer_sync(&s->rx_fifo_timer);
2206 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2209 unsigned long freq = s->clk_rates[SCI_SCK];
2210 int err, min_err = INT_MAX;
2213 if (s->port.type != PORT_HSCIF)
2216 for_each_sr(sr, s) {
2217 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2218 if (abs(err) >= abs(min_err))
2228 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2233 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2234 unsigned long freq, unsigned int *dlr,
2237 int err, min_err = INT_MAX;
2238 unsigned int sr, dl;
2240 if (s->port.type != PORT_HSCIF)
2243 for_each_sr(sr, s) {
2244 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2245 dl = clamp(dl, 1U, 65535U);
2247 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2248 if (abs(err) >= abs(min_err))
2259 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2260 min_err, *dlr, *srr + 1);
2264 /* calculate sample rate, BRR, and clock select */
2265 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2266 unsigned int *brr, unsigned int *srr,
2269 unsigned long freq = s->clk_rates[SCI_FCK];
2270 unsigned int sr, br, prediv, scrate, c;
2271 int err, min_err = INT_MAX;
2273 if (s->port.type != PORT_HSCIF)
2277 * Find the combination of sample rate and clock select with the
2278 * smallest deviation from the desired baud rate.
2279 * Prefer high sample rates to maximise the receive margin.
2281 * M: Receive margin (%)
2282 * N: Ratio of bit rate to clock (N = sampling rate)
2283 * D: Clock duty (D = 0 to 1.0)
2284 * L: Frame length (L = 9 to 12)
2285 * F: Absolute value of clock frequency deviation
2287 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2288 * (|D - 0.5| / N * (1 + F))|
2289 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2291 for_each_sr(sr, s) {
2292 for (c = 0; c <= 3; c++) {
2293 /* integerized formulas from HSCIF documentation */
2294 prediv = sr * (1 << (2 * c + 1));
2297 * We need to calculate:
2299 * br = freq / (prediv * bps) clamped to [1..256]
2300 * err = freq / (br * prediv) - bps
2302 * Watch out for overflow when calculating the desired
2303 * sampling clock rate!
2305 if (bps > UINT_MAX / prediv)
2308 scrate = prediv * bps;
2309 br = DIV_ROUND_CLOSEST(freq, scrate);
2310 br = clamp(br, 1U, 256U);
2312 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2313 if (abs(err) >= abs(min_err))
2327 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2328 min_err, *brr, *srr + 1, *cks);
2332 static void sci_reset(struct uart_port *port)
2334 const struct plat_sci_reg *reg;
2335 unsigned int status;
2336 struct sci_port *s = to_sci_port(port);
2338 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2340 reg = sci_getreg(port, SCFCR);
2342 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2344 sci_clear_SCxSR(port,
2345 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2346 SCxSR_BREAK_CLEAR(port));
2347 if (sci_getreg(port, SCLSR)->size) {
2348 status = serial_port_in(port, SCLSR);
2349 status &= ~(SCLSR_TO | SCLSR_ORER);
2350 serial_port_out(port, SCLSR, status);
2353 if (s->rx_trigger > 1) {
2354 if (s->rx_fifo_timeout) {
2355 scif_set_rtrg(port, 1);
2356 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2358 if (port->type == PORT_SCIFA ||
2359 port->type == PORT_SCIFB)
2360 scif_set_rtrg(port, 1);
2362 scif_set_rtrg(port, s->rx_trigger);
2367 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2368 struct ktermios *old)
2370 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2371 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2372 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2373 struct sci_port *s = to_sci_port(port);
2374 const struct plat_sci_reg *reg;
2375 int min_err = INT_MAX, err;
2376 unsigned long max_freq = 0;
2378 unsigned long flags;
2380 if ((termios->c_cflag & CSIZE) == CS7)
2381 smr_val |= SCSMR_CHR;
2382 if (termios->c_cflag & PARENB)
2383 smr_val |= SCSMR_PE;
2384 if (termios->c_cflag & PARODD)
2385 smr_val |= SCSMR_PE | SCSMR_ODD;
2386 if (termios->c_cflag & CSTOPB)
2387 smr_val |= SCSMR_STOP;
2390 * earlyprintk comes here early on with port->uartclk set to zero.
2391 * the clock framework is not up and running at this point so here
2392 * we assume that 115200 is the maximum baud rate. please note that
2393 * the baud rate is not programmed during earlyprintk - it is assumed
2394 * that the previous boot loader has enabled required clocks and
2395 * setup the baud rate generator hardware for us already.
2397 if (!port->uartclk) {
2398 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2402 for (i = 0; i < SCI_NUM_CLKS; i++)
2403 max_freq = max(max_freq, s->clk_rates[i]);
2405 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2410 * There can be multiple sources for the sampling clock. Find the one
2411 * that gives us the smallest deviation from the desired baud rate.
2414 /* Optional Undivided External Clock */
2415 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2416 port->type != PORT_SCIFB) {
2417 err = sci_sck_calc(s, baud, &srr1);
2418 if (abs(err) < abs(min_err)) {
2420 scr_val = SCSCR_CKE1;
2429 /* Optional BRG Frequency Divided External Clock */
2430 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2431 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2433 if (abs(err) < abs(min_err)) {
2434 best_clk = SCI_SCIF_CLK;
2435 scr_val = SCSCR_CKE1;
2445 /* Optional BRG Frequency Divided Internal Clock */
2446 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2447 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2449 if (abs(err) < abs(min_err)) {
2450 best_clk = SCI_BRG_INT;
2451 scr_val = SCSCR_CKE1;
2461 /* Divided Functional Clock using standard Bit Rate Register */
2462 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2463 if (abs(err) < abs(min_err)) {
2474 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2475 s->clks[best_clk], baud, min_err);
2480 * Program the optional External Baud Rate Generator (BRG) first.
2481 * It controls the mux to select (H)SCK or frequency divided clock.
2483 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2484 serial_port_out(port, SCDL, dl);
2485 serial_port_out(port, SCCKS, sccks);
2488 spin_lock_irqsave(&port->lock, flags);
2492 uart_update_timeout(port, termios->c_cflag, baud);
2494 /* byte size and parity */
2495 switch (termios->c_cflag & CSIZE) {
2510 if (termios->c_cflag & CSTOPB)
2512 if (termios->c_cflag & PARENB)
2515 if (best_clk >= 0) {
2516 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2518 case 5: smr_val |= SCSMR_SRC_5; break;
2519 case 7: smr_val |= SCSMR_SRC_7; break;
2520 case 11: smr_val |= SCSMR_SRC_11; break;
2521 case 13: smr_val |= SCSMR_SRC_13; break;
2522 case 16: smr_val |= SCSMR_SRC_16; break;
2523 case 17: smr_val |= SCSMR_SRC_17; break;
2524 case 19: smr_val |= SCSMR_SRC_19; break;
2525 case 27: smr_val |= SCSMR_SRC_27; break;
2528 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2529 serial_port_out(port, SCSMR, smr_val);
2530 serial_port_out(port, SCBRR, brr);
2531 if (sci_getreg(port, HSSRR)->size) {
2532 unsigned int hssrr = srr | HSCIF_SRE;
2533 /* Calculate deviation from intended rate at the
2534 * center of the last stop bit in sampling clocks.
2536 int last_stop = bits * 2 - 1;
2537 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2541 if (abs(deviation) >= 2) {
2542 /* At least two sampling clocks off at the
2543 * last stop bit; we can increase the error
2544 * margin by shifting the sampling point.
2546 int shift = clamp(deviation / 2, -8, 7);
2548 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2550 hssrr |= HSCIF_SRDE;
2552 serial_port_out(port, HSSRR, hssrr);
2555 /* Wait one bit interval */
2556 udelay((1000000 + (baud - 1)) / baud);
2558 /* Don't touch the bit rate configuration */
2559 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2560 smr_val |= serial_port_in(port, SCSMR) &
2561 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2562 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2563 serial_port_out(port, SCSMR, smr_val);
2566 sci_init_pins(port, termios->c_cflag);
2568 port->status &= ~UPSTAT_AUTOCTS;
2570 reg = sci_getreg(port, SCFCR);
2572 unsigned short ctrl = serial_port_in(port, SCFCR);
2574 if ((port->flags & UPF_HARD_FLOW) &&
2575 (termios->c_cflag & CRTSCTS)) {
2576 /* There is no CTS interrupt to restart the hardware */
2577 port->status |= UPSTAT_AUTOCTS;
2578 /* MCE is enabled when RTS is raised */
2583 * As we've done a sci_reset() above, ensure we don't
2584 * interfere with the FIFOs while toggling MCE. As the
2585 * reset values could still be set, simply mask them out.
2587 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2589 serial_port_out(port, SCFCR, ctrl);
2591 if (port->flags & UPF_HARD_FLOW) {
2592 /* Refresh (Auto) RTS */
2593 sci_set_mctrl(port, port->mctrl);
2596 scr_val |= SCSCR_RE | SCSCR_TE |
2597 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2598 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2599 if ((srr + 1 == 5) &&
2600 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2602 * In asynchronous mode, when the sampling rate is 1/5, first
2603 * received data may become invalid on some SCIFA and SCIFB.
2604 * To avoid this problem wait more than 1 serial data time (1
2605 * bit time x serial data number) after setting SCSCR.RE = 1.
2607 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2611 * Calculate delay for 2 DMA buffers (4 FIFO).
2612 * See serial_core.c::uart_update_timeout().
2613 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2614 * function calculates 1 jiffie for the data plus 5 jiffies for the
2615 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2616 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2617 * value obtained by this formula is too small. Therefore, if the value
2618 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2620 s->rx_frame = (10000 * bits) / (baud / 100);
2621 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2622 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2623 if (s->rx_timeout < 20)
2627 if ((termios->c_cflag & CREAD) != 0)
2630 spin_unlock_irqrestore(&port->lock, flags);
2632 sci_port_disable(s);
2634 if (UART_ENABLE_MS(port, termios->c_cflag))
2635 sci_enable_ms(port);
2638 static void sci_pm(struct uart_port *port, unsigned int state,
2639 unsigned int oldstate)
2641 struct sci_port *sci_port = to_sci_port(port);
2644 case UART_PM_STATE_OFF:
2645 sci_port_disable(sci_port);
2648 sci_port_enable(sci_port);
2653 static const char *sci_type(struct uart_port *port)
2655 switch (port->type) {
2673 static int sci_remap_port(struct uart_port *port)
2675 struct sci_port *sport = to_sci_port(port);
2678 * Nothing to do if there's already an established membase.
2683 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2684 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2685 if (unlikely(!port->membase)) {
2686 dev_err(port->dev, "can't remap port#%d\n", port->line);
2691 * For the simple (and majority of) cases where we don't
2692 * need to do any remapping, just cast the cookie
2695 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2701 static void sci_release_port(struct uart_port *port)
2703 struct sci_port *sport = to_sci_port(port);
2705 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2706 iounmap(port->membase);
2707 port->membase = NULL;
2710 release_mem_region(port->mapbase, sport->reg_size);
2713 static int sci_request_port(struct uart_port *port)
2715 struct resource *res;
2716 struct sci_port *sport = to_sci_port(port);
2719 res = request_mem_region(port->mapbase, sport->reg_size,
2720 dev_name(port->dev));
2721 if (unlikely(res == NULL)) {
2722 dev_err(port->dev, "request_mem_region failed.");
2726 ret = sci_remap_port(port);
2727 if (unlikely(ret != 0)) {
2728 release_resource(res);
2735 static void sci_config_port(struct uart_port *port, int flags)
2737 if (flags & UART_CONFIG_TYPE) {
2738 struct sci_port *sport = to_sci_port(port);
2740 port->type = sport->cfg->type;
2741 sci_request_port(port);
2745 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2747 if (ser->baud_base < 2400)
2748 /* No paper tape reader for Mitch.. */
2754 static const struct uart_ops sci_uart_ops = {
2755 .tx_empty = sci_tx_empty,
2756 .set_mctrl = sci_set_mctrl,
2757 .get_mctrl = sci_get_mctrl,
2758 .start_tx = sci_start_tx,
2759 .stop_tx = sci_stop_tx,
2760 .stop_rx = sci_stop_rx,
2761 .enable_ms = sci_enable_ms,
2762 .break_ctl = sci_break_ctl,
2763 .startup = sci_startup,
2764 .shutdown = sci_shutdown,
2765 .flush_buffer = sci_flush_buffer,
2766 .set_termios = sci_set_termios,
2769 .release_port = sci_release_port,
2770 .request_port = sci_request_port,
2771 .config_port = sci_config_port,
2772 .verify_port = sci_verify_port,
2773 #ifdef CONFIG_CONSOLE_POLL
2774 .poll_get_char = sci_poll_get_char,
2775 .poll_put_char = sci_poll_put_char,
2779 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2781 const char *clk_names[] = {
2784 [SCI_BRG_INT] = "brg_int",
2785 [SCI_SCIF_CLK] = "scif_clk",
2790 if (sci_port->cfg->type == PORT_HSCIF)
2791 clk_names[SCI_SCK] = "hsck";
2793 for (i = 0; i < SCI_NUM_CLKS; i++) {
2794 clk = devm_clk_get(dev, clk_names[i]);
2795 if (PTR_ERR(clk) == -EPROBE_DEFER)
2796 return -EPROBE_DEFER;
2798 if (IS_ERR(clk) && i == SCI_FCK) {
2800 * "fck" used to be called "sci_ick", and we need to
2801 * maintain DT backward compatibility.
2803 clk = devm_clk_get(dev, "sci_ick");
2804 if (PTR_ERR(clk) == -EPROBE_DEFER)
2805 return -EPROBE_DEFER;
2811 * Not all SH platforms declare a clock lookup entry
2812 * for SCI devices, in which case we need to get the
2813 * global "peripheral_clk" clock.
2815 clk = devm_clk_get(dev, "peripheral_clk");
2819 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2821 return PTR_ERR(clk);
2826 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2829 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2830 clk, clk_get_rate(clk));
2831 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2836 static const struct sci_port_params *
2837 sci_probe_regmap(const struct plat_sci_port *cfg)
2839 unsigned int regtype;
2841 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2842 return &sci_port_params[cfg->regtype];
2844 switch (cfg->type) {
2846 regtype = SCIx_SCI_REGTYPE;
2849 regtype = SCIx_IRDA_REGTYPE;
2852 regtype = SCIx_SCIFA_REGTYPE;
2855 regtype = SCIx_SCIFB_REGTYPE;
2859 * The SH-4 is a bit of a misnomer here, although that's
2860 * where this particular port layout originated. This
2861 * configuration (or some slight variation thereof)
2862 * remains the dominant model for all SCIFs.
2864 regtype = SCIx_SH4_SCIF_REGTYPE;
2867 regtype = SCIx_HSCIF_REGTYPE;
2870 pr_err("Can't probe register map for given port\n");
2874 return &sci_port_params[regtype];
2877 static int sci_init_single(struct platform_device *dev,
2878 struct sci_port *sci_port, unsigned int index,
2879 const struct plat_sci_port *p, bool early)
2881 struct uart_port *port = &sci_port->port;
2882 const struct resource *res;
2888 port->ops = &sci_uart_ops;
2889 port->iotype = UPIO_MEM;
2892 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2896 port->mapbase = res->start;
2897 sci_port->reg_size = resource_size(res);
2899 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2900 sci_port->irqs[i] = platform_get_irq(dev, i);
2902 /* The SCI generates several interrupts. They can be muxed together or
2903 * connected to different interrupt lines. In the muxed case only one
2904 * interrupt resource is specified as there is only one interrupt ID.
2905 * In the non-muxed case, up to 6 interrupt signals might be generated
2906 * from the SCI, however those signals might have their own individual
2907 * interrupt ID numbers, or muxed together with another interrupt.
2909 if (sci_port->irqs[0] < 0)
2912 if (sci_port->irqs[1] < 0)
2913 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2914 sci_port->irqs[i] = sci_port->irqs[0];
2916 sci_port->params = sci_probe_regmap(p);
2917 if (unlikely(sci_port->params == NULL))
2922 sci_port->rx_trigger = 48;
2925 sci_port->rx_trigger = 64;
2928 sci_port->rx_trigger = 32;
2931 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2932 /* RX triggering not implemented for this IP */
2933 sci_port->rx_trigger = 1;
2935 sci_port->rx_trigger = 8;
2938 sci_port->rx_trigger = 1;
2942 sci_port->rx_fifo_timeout = 0;
2943 sci_port->hscif_tot = 0;
2945 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2946 * match the SoC datasheet, this should be investigated. Let platform
2947 * data override the sampling rate for now.
2949 sci_port->sampling_rate_mask = p->sampling_rate
2950 ? SCI_SR(p->sampling_rate)
2951 : sci_port->params->sampling_rate_mask;
2954 ret = sci_init_clocks(sci_port, &dev->dev);
2958 port->dev = &dev->dev;
2960 pm_runtime_enable(&dev->dev);
2963 port->type = p->type;
2964 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2965 port->fifosize = sci_port->params->fifosize;
2967 if (port->type == PORT_SCI) {
2968 if (sci_port->reg_size >= 0x20)
2975 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2976 * for the multi-IRQ ports, which is where we are primarily
2977 * concerned with the shutdown path synchronization.
2979 * For the muxed case there's nothing more to do.
2981 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2984 port->serial_in = sci_serial_in;
2985 port->serial_out = sci_serial_out;
2990 static void sci_cleanup_single(struct sci_port *port)
2992 pm_runtime_disable(port->port.dev);
2995 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2996 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2997 static void serial_console_putchar(struct uart_port *port, int ch)
2999 sci_poll_put_char(port, ch);
3003 * Print a string to the serial port trying not to disturb
3004 * any possible real use of the port...
3006 static void serial_console_write(struct console *co, const char *s,
3009 struct sci_port *sci_port = &sci_ports[co->index];
3010 struct uart_port *port = &sci_port->port;
3011 unsigned short bits, ctrl, ctrl_temp;
3012 unsigned long flags;
3015 #if defined(SUPPORT_SYSRQ)
3020 if (oops_in_progress)
3021 locked = spin_trylock_irqsave(&port->lock, flags);
3023 spin_lock_irqsave(&port->lock, flags);
3025 /* first save SCSCR then disable interrupts, keep clock source */
3026 ctrl = serial_port_in(port, SCSCR);
3027 ctrl_temp = SCSCR_RE | SCSCR_TE |
3028 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3029 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3030 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3032 uart_console_write(port, s, count, serial_console_putchar);
3034 /* wait until fifo is empty and last bit has been transmitted */
3035 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3036 while ((serial_port_in(port, SCxSR) & bits) != bits)
3039 /* restore the SCSCR */
3040 serial_port_out(port, SCSCR, ctrl);
3043 spin_unlock_irqrestore(&port->lock, flags);
3046 static int serial_console_setup(struct console *co, char *options)
3048 struct sci_port *sci_port;
3049 struct uart_port *port;
3057 * Refuse to handle any bogus ports.
3059 if (co->index < 0 || co->index >= SCI_NPORTS)
3062 sci_port = &sci_ports[co->index];
3063 port = &sci_port->port;
3066 * Refuse to handle uninitialized ports.
3071 ret = sci_remap_port(port);
3072 if (unlikely(ret != 0))
3076 uart_parse_options(options, &baud, &parity, &bits, &flow);
3078 return uart_set_options(port, co, baud, parity, bits, flow);
3081 static struct console serial_console = {
3083 .device = uart_console_device,
3084 .write = serial_console_write,
3085 .setup = serial_console_setup,
3086 .flags = CON_PRINTBUFFER,
3088 .data = &sci_uart_driver,
3091 static struct console early_serial_console = {
3092 .name = "early_ttySC",
3093 .write = serial_console_write,
3094 .flags = CON_PRINTBUFFER,
3098 static char early_serial_buf[32];
3100 static int sci_probe_earlyprintk(struct platform_device *pdev)
3102 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3104 if (early_serial_console.data)
3107 early_serial_console.index = pdev->id;
3109 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3111 serial_console_setup(&early_serial_console, early_serial_buf);
3113 if (!strstr(early_serial_buf, "keep"))
3114 early_serial_console.flags |= CON_BOOT;
3116 register_console(&early_serial_console);
3120 #define SCI_CONSOLE (&serial_console)
3123 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3128 #define SCI_CONSOLE NULL
3130 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3132 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3134 static DEFINE_MUTEX(sci_uart_registration_lock);
3135 static struct uart_driver sci_uart_driver = {
3136 .owner = THIS_MODULE,
3137 .driver_name = "sci",
3138 .dev_name = "ttySC",
3140 .minor = SCI_MINOR_START,
3142 .cons = SCI_CONSOLE,
3145 static int sci_remove(struct platform_device *dev)
3147 struct sci_port *port = platform_get_drvdata(dev);
3148 unsigned int type = port->port.type; /* uart_remove_... clears it */
3150 sci_ports_in_use &= ~BIT(port->port.line);
3151 uart_remove_one_port(&sci_uart_driver, &port->port);
3153 sci_cleanup_single(port);
3155 if (port->port.fifosize > 1) {
3156 sysfs_remove_file(&dev->dev.kobj,
3157 &dev_attr_rx_fifo_trigger.attr);
3159 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) {
3160 sysfs_remove_file(&dev->dev.kobj,
3161 &dev_attr_rx_fifo_timeout.attr);
3168 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3169 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3170 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3172 static const struct of_device_id of_sci_match[] = {
3173 /* SoC-specific types */
3175 .compatible = "renesas,scif-r7s72100",
3176 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3179 .compatible = "renesas,scif-r7s9210",
3180 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3182 /* Family-specific types */
3184 .compatible = "renesas,rcar-gen1-scif",
3185 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3187 .compatible = "renesas,rcar-gen2-scif",
3188 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3190 .compatible = "renesas,rcar-gen3-scif",
3191 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3195 .compatible = "renesas,scif",
3196 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3198 .compatible = "renesas,scifa",
3199 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3201 .compatible = "renesas,scifb",
3202 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3204 .compatible = "renesas,hscif",
3205 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3207 .compatible = "renesas,sci",
3208 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3213 MODULE_DEVICE_TABLE(of, of_sci_match);
3215 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3216 unsigned int *dev_id)
3218 struct device_node *np = pdev->dev.of_node;
3219 struct plat_sci_port *p;
3220 struct sci_port *sp;
3224 if (!IS_ENABLED(CONFIG_OF) || !np)
3227 data = of_device_get_match_data(&pdev->dev);
3229 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3233 /* Get the line number from the aliases node. */
3234 id = of_alias_get_id(np, "serial");
3235 if (id < 0 && ~sci_ports_in_use)
3236 id = ffz(sci_ports_in_use);
3238 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3241 if (id >= ARRAY_SIZE(sci_ports)) {
3242 dev_err(&pdev->dev, "serial%d out of range\n", id);
3246 sp = &sci_ports[id];
3249 p->type = SCI_OF_TYPE(data);
3250 p->regtype = SCI_OF_REGTYPE(data);
3252 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3257 static int sci_probe_single(struct platform_device *dev,
3259 struct plat_sci_port *p,
3260 struct sci_port *sciport)
3265 if (unlikely(index >= SCI_NPORTS)) {
3266 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3267 index+1, SCI_NPORTS);
3268 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3271 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3272 if (sci_ports_in_use & BIT(index))
3275 mutex_lock(&sci_uart_registration_lock);
3276 if (!sci_uart_driver.state) {
3277 ret = uart_register_driver(&sci_uart_driver);
3279 mutex_unlock(&sci_uart_registration_lock);
3283 mutex_unlock(&sci_uart_registration_lock);
3285 ret = sci_init_single(dev, sciport, index, p, false);
3289 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3290 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3291 return PTR_ERR(sciport->gpios);
3293 if (sciport->has_rtscts) {
3294 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3296 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3298 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3301 sciport->port.flags |= UPF_HARD_FLOW;
3304 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3306 sci_cleanup_single(sciport);
3313 static int sci_probe(struct platform_device *dev)
3315 struct plat_sci_port *p;
3316 struct sci_port *sp;
3317 unsigned int dev_id;
3321 * If we've come here via earlyprintk initialization, head off to
3322 * the special early probe. We don't have sufficient device state
3323 * to make it beyond this yet.
3325 if (is_early_platform_device(dev))
3326 return sci_probe_earlyprintk(dev);
3328 if (dev->dev.of_node) {
3329 p = sci_parse_dt(dev, &dev_id);
3333 p = dev->dev.platform_data;
3335 dev_err(&dev->dev, "no platform data supplied\n");
3342 sp = &sci_ports[dev_id];
3343 platform_set_drvdata(dev, sp);
3345 ret = sci_probe_single(dev, dev_id, p, sp);
3349 if (sp->port.fifosize > 1) {
3350 ret = sysfs_create_file(&dev->dev.kobj,
3351 &dev_attr_rx_fifo_trigger.attr);
3355 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3356 sp->port.type == PORT_HSCIF) {
3357 ret = sysfs_create_file(&dev->dev.kobj,
3358 &dev_attr_rx_fifo_timeout.attr);
3360 if (sp->port.fifosize > 1) {
3361 sysfs_remove_file(&dev->dev.kobj,
3362 &dev_attr_rx_fifo_trigger.attr);
3368 #ifdef CONFIG_SH_STANDARD_BIOS
3369 sh_bios_gdb_detach();
3372 sci_ports_in_use |= BIT(dev_id);
3376 static __maybe_unused int sci_suspend(struct device *dev)
3378 struct sci_port *sport = dev_get_drvdata(dev);
3381 uart_suspend_port(&sci_uart_driver, &sport->port);
3386 static __maybe_unused int sci_resume(struct device *dev)
3388 struct sci_port *sport = dev_get_drvdata(dev);
3391 uart_resume_port(&sci_uart_driver, &sport->port);
3396 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3398 static struct platform_driver sci_driver = {
3400 .remove = sci_remove,
3403 .pm = &sci_dev_pm_ops,
3404 .of_match_table = of_match_ptr(of_sci_match),
3408 static int __init sci_init(void)
3410 pr_info("%s\n", banner);
3412 return platform_driver_register(&sci_driver);
3415 static void __exit sci_exit(void)
3417 platform_driver_unregister(&sci_driver);
3419 if (sci_uart_driver.state)
3420 uart_unregister_driver(&sci_uart_driver);
3423 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3424 early_platform_init_buffer("earlyprintk", &sci_driver,
3425 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3427 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3428 static struct plat_sci_port port_cfg __initdata;
3430 static int __init early_console_setup(struct earlycon_device *device,
3433 if (!device->port.membase)
3436 device->port.serial_in = sci_serial_in;
3437 device->port.serial_out = sci_serial_out;
3438 device->port.type = type;
3439 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3440 port_cfg.type = type;
3441 sci_ports[0].cfg = &port_cfg;
3442 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3443 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3444 sci_serial_out(&sci_ports[0].port, SCSCR,
3445 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3447 device->con->write = serial_console_write;
3450 static int __init sci_early_console_setup(struct earlycon_device *device,
3453 return early_console_setup(device, PORT_SCI);
3455 static int __init scif_early_console_setup(struct earlycon_device *device,
3458 return early_console_setup(device, PORT_SCIF);
3460 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3463 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3464 return early_console_setup(device, PORT_SCIF);
3466 static int __init scifa_early_console_setup(struct earlycon_device *device,
3469 return early_console_setup(device, PORT_SCIFA);
3471 static int __init scifb_early_console_setup(struct earlycon_device *device,
3474 return early_console_setup(device, PORT_SCIFB);
3476 static int __init hscif_early_console_setup(struct earlycon_device *device,
3479 return early_console_setup(device, PORT_HSCIF);
3482 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3483 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3484 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3485 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3486 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3487 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3488 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3490 module_init(sci_init);
3491 module_exit(sci_exit);
3493 MODULE_LICENSE("GPL");
3494 MODULE_ALIAS("platform:sh-sci");
3495 MODULE_AUTHOR("Paul Mundt");
3496 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");