drivers/tty/serial/pch_uart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   4  */
   5 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
   6 #define SUPPORT_SYSRQ
   7 #endif
   8 #include <linux/kernel.h>
   9 #include <linux/serial_reg.h>
  10 #include <linux/slab.h>
  11 #include <linux/module.h>
  12 #include <linux/pci.h>
  13 #include <linux/console.h>
  14 #include <linux/serial_core.h>
  15 #include <linux/tty.h>
  16 #include <linux/tty_flip.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/dmi.h>
  20 #include <linux/nmi.h>
  21 #include <linux/delay.h>
  22 #include <linux/of.h>
  23
  24 #include <linux/debugfs.h>
  25 #include <linux/dmaengine.h>
  26 #include <linux/pch_dma.h>
  27
  28 enum {
  29         PCH_UART_HANDLED_RX_INT_SHIFT,
  30         PCH_UART_HANDLED_TX_INT_SHIFT,
  31         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  32         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  33         PCH_UART_HANDLED_MS_INT_SHIFT,
  34         PCH_UART_HANDLED_LS_INT_SHIFT,
  35 };
  36
  37 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  38
  39 /* Set the max number of UART port
  40  * Intel EG20T PCH: 4 port
  41  * LAPIS Semiconductor ML7213 IOH: 3 port
  42  * LAPIS Semiconductor ML7223 IOH: 2 port
  43 */
  44 #define PCH_UART_NR     4
  45
  46 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  47 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  48 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  49                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  50 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  51                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  52 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  53
  54 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
  55
  56 #define PCH_UART_RBR            0x00
  57 #define PCH_UART_THR            0x00
  58
  59 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  60                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  61 #define PCH_UART_IER_ERBFI      0x00000001
  62 #define PCH_UART_IER_ETBEI      0x00000002
  63 #define PCH_UART_IER_ELSI       0x00000004
  64 #define PCH_UART_IER_EDSSI      0x00000008
  65
  66 #define PCH_UART_IIR_IP                 0x00000001
  67 #define PCH_UART_IIR_IID                0x00000006
  68 #define PCH_UART_IIR_MSI                0x00000000
  69 #define PCH_UART_IIR_TRI                0x00000002
  70 #define PCH_UART_IIR_RRI                0x00000004
  71 #define PCH_UART_IIR_REI                0x00000006
  72 #define PCH_UART_IIR_TOI                0x00000008
  73 #define PCH_UART_IIR_FIFO256            0x00000020
  74 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  75 #define PCH_UART_IIR_FE                 0x000000C0
  76
  77 #define PCH_UART_FCR_FIFOE              0x00000001
  78 #define PCH_UART_FCR_RFR                0x00000002
  79 #define PCH_UART_FCR_TFR                0x00000004
  80 #define PCH_UART_FCR_DMS                0x00000008
  81 #define PCH_UART_FCR_FIFO256            0x00000020
  82 #define PCH_UART_FCR_RFTL               0x000000C0
  83
  84 #define PCH_UART_FCR_RFTL1              0x00000000
  85 #define PCH_UART_FCR_RFTL64             0x00000040
  86 #define PCH_UART_FCR_RFTL128            0x00000080
  87 #define PCH_UART_FCR_RFTL224            0x000000C0
  88 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
  89 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
  90 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
  91 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
  92 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
  93 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
  94 #define PCH_UART_FCR_RFTL_SHIFT         6
  95
  96 #define PCH_UART_LCR_WLS        0x00000003
  97 #define PCH_UART_LCR_STB        0x00000004
  98 #define PCH_UART_LCR_PEN        0x00000008
  99 #define PCH_UART_LCR_EPS        0x00000010
 100 #define PCH_UART_LCR_SP         0x00000020
 101 #define PCH_UART_LCR_SB         0x00000040
 102 #define PCH_UART_LCR_DLAB       0x00000080
 103 #define PCH_UART_LCR_NP         0x00000000
 104 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 105 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 106 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 107 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 108                                 PCH_UART_LCR_SP)
 109
 110 #define PCH_UART_LCR_5BIT       0x00000000
 111 #define PCH_UART_LCR_6BIT       0x00000001
 112 #define PCH_UART_LCR_7BIT       0x00000002
 113 #define PCH_UART_LCR_8BIT       0x00000003
 114
 115 #define PCH_UART_MCR_DTR        0x00000001
 116 #define PCH_UART_MCR_RTS        0x00000002
 117 #define PCH_UART_MCR_OUT        0x0000000C
 118 #define PCH_UART_MCR_LOOP       0x00000010
 119 #define PCH_UART_MCR_AFE        0x00000020
 120
 121 #define PCH_UART_LSR_DR         0x00000001
 122 #define PCH_UART_LSR_ERR        (1<<7)
 123
 124 #define PCH_UART_MSR_DCTS       0x00000001
 125 #define PCH_UART_MSR_DDSR       0x00000002
 126 #define PCH_UART_MSR_TERI       0x00000004
 127 #define PCH_UART_MSR_DDCD       0x00000008
 128 #define PCH_UART_MSR_CTS        0x00000010
 129 #define PCH_UART_MSR_DSR        0x00000020
 130 #define PCH_UART_MSR_RI         0x00000040
 131 #define PCH_UART_MSR_DCD        0x00000080
 132 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 133                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 134
 135 #define PCH_UART_DLL            0x00
 136 #define PCH_UART_DLM            0x01
 137
 138 #define PCH_UART_BRCSR          0x0E
 139
 140 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 141 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 142 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 143 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 144 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 145
 146 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 147 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 148 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 149 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 150 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 151 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 152 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 153 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 154 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 155 #define PCH_UART_HAL_STB1               0
 156 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 157
 158 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 159 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 160 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 161                                         PCH_UART_HAL_CLR_RX_FIFO)
 162
 163 #define PCH_UART_HAL_DMA_MODE0          0
 164 #define PCH_UART_HAL_FIFO_DIS           0
 165 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 166 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 167                                         PCH_UART_FCR_FIFO256)
 168 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 169 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 170 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 171 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 172 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 173 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 174 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 175 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 176 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 177 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 178 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 179 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 180 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 181 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 182
 183 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 184 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 185 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 186 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 187 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 188
 189 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 190 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 191 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 192 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 193 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 194
 195 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 196
 197 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
 198 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
 199 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
 200 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
 201 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
 202 #define MINNOW_UARTCLK   50000000 /*  50.0000 MHz */
 203
 204 struct pch_uart_buffer {
 205         unsigned char *buf;
 206         int size;
 207 };
 208
 209 struct eg20t_port {
 210         struct uart_port port;
 211         int port_type;
 212         void __iomem *membase;
 213         resource_size_t mapbase;
 214         unsigned int iobase;
 215         struct pci_dev *pdev;
 216         int fifo_size;
 217         unsigned int uartclk;
 218         int start_tx;
 219         int start_rx;
 220         int tx_empty;
 221         int trigger;
 222         int trigger_level;
 223         struct pch_uart_buffer rxbuf;
 224         unsigned int dmsr;
 225         unsigned int fcr;
 226         unsigned int mcr;
 227         unsigned int use_dma;
 228         struct dma_async_tx_descriptor  *desc_tx;
 229         struct dma_async_tx_descriptor  *desc_rx;
 230         struct pch_dma_slave            param_tx;
 231         struct pch_dma_slave            param_rx;
 232         struct dma_chan                 *chan_tx;
 233         struct dma_chan                 *chan_rx;
 234         struct scatterlist              *sg_tx_p;
 235         int                             nent;
 236         struct scatterlist              sg_rx;
 237         int                             tx_dma_use;
 238         void                            *rx_buf_virt;
 239         dma_addr_t                      rx_buf_dma;
 240
 241         struct dentry   *debugfs;
 242 #define IRQ_NAME_SIZE 17
 243         char                            irq_name[IRQ_NAME_SIZE];
 244
 245         /* protect the eg20t_port private structure and io access to membase */
 246         spinlock_t lock;
 247 };
 248
 249 /**
 250  * struct pch_uart_driver_data - private data structure for UART-DMA
 251  * @port_type:                  The type of UART port
 252  * @line_no:                    UART port line number (0, 1, 2...)
 253  */
 254 struct pch_uart_driver_data {
 255         int port_type;
 256         int line_no;
 257 };
 258
 259 enum pch_uart_num_t {
 260         pch_et20t_uart0 = 0,
 261         pch_et20t_uart1,
 262         pch_et20t_uart2,
 263         pch_et20t_uart3,
 264         pch_ml7213_uart0,
 265         pch_ml7213_uart1,
 266         pch_ml7213_uart2,
 267         pch_ml7223_uart0,
 268         pch_ml7223_uart1,
 269         pch_ml7831_uart0,
 270         pch_ml7831_uart1,
 271 };
 272
 273 static struct pch_uart_driver_data drv_dat[] = {
 274         [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
 275         [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
 276         [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
 277         [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
 278         [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
 279         [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
 280         [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
 281         [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
 282         [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
 283         [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
 284         [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
 285 };
 286
 287 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
 288 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
 289 #endif
 290 static unsigned int default_baud = 9600;
 291 static unsigned int user_uartclk = 0;
 292 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 293 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 294 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 295 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 296
 297 #ifdef CONFIG_DEBUG_FS
 298
 299 #define PCH_REGS_BUFSIZE        1024
 300
 301
 302 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 303                                 size_t count, loff_t *ppos)
 304 {
 305         struct eg20t_port *priv = file->private_data;
 306         char *buf;
 307         u32 len = 0;
 308         ssize_t ret;
 309         unsigned char lcr;
 310
 311         buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
 312         if (!buf)
 313                 return 0;
 314
 315         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 316                         "PCH EG20T port[%d] regs:\n", priv->port.line);
 317
 318         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 319                         "=================================\n");
 320         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 321                         "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
 322         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 323                         "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
 324         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 325                         "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
 326         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 327                         "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
 328         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 329                         "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
 330         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 331                         "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
 332         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 333                         "BRCSR: \t0x%02x\n",
 334                         ioread8(priv->membase + PCH_UART_BRCSR));
 335
 336         lcr = ioread8(priv->membase + UART_LCR);
 337         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 338         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 339                         "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
 340         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 341                         "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
 342         iowrite8(lcr, priv->membase + UART_LCR);
 343
 344         if (len > PCH_REGS_BUFSIZE)
 345                 len = PCH_REGS_BUFSIZE;
 346
 347         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 348         kfree(buf);
 349         return ret;
 350 }
 351
 352 static const struct file_operations port_regs_ops = {
 353         .owner          = THIS_MODULE,
 354         .open           = simple_open,
 355         .read           = port_show_regs,
 356         .llseek         = default_llseek,
 357 };
 358 #endif  /* CONFIG_DEBUG_FS */
 359
 360 static const struct dmi_system_id pch_uart_dmi_table[] = {
 361         {
 362                 .ident = "CM-iTC",
 363                 {
 364                         DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
 365                 },
 366                 (void *)CMITC_UARTCLK,
 367         },
 368         {
 369                 .ident = "FRI2",
 370                 {
 371                         DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
 372                 },
 373                 (void *)FRI2_64_UARTCLK,
 374         },
 375         {
 376                 .ident = "Fish River Island II",
 377                 {
 378                         DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
 379                 },
 380                 (void *)FRI2_48_UARTCLK,
 381         },
 382         {
 383                 .ident = "COMe-mTT",
 384                 {
 385                         DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
 386                 },
 387                 (void *)NTC1_UARTCLK,
 388         },
 389         {
 390                 .ident = "nanoETXexpress-TT",
 391                 {
 392                         DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
 393                 },
 394                 (void *)NTC1_UARTCLK,
 395         },
 396         {
 397                 .ident = "MinnowBoard",
 398                 {
 399                         DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
 400                 },
 401                 (void *)MINNOW_UARTCLK,
 402         },
 403         { }
 404 };
 405
 406 /* Return UART clock, checking for board specific clocks. */
 407 static unsigned int pch_uart_get_uartclk(void)
 408 {
 409         const struct dmi_system_id *d;
 410
 411         if (user_uartclk)
 412                 return user_uartclk;
 413
 414         d = dmi_first_match(pch_uart_dmi_table);
 415         if (d)
 416                 return (unsigned long)d->driver_data;
 417
 418         return DEFAULT_UARTCLK;
 419 }
 420
 421 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 422                                           unsigned int flag)
 423 {
 424         u8 ier = ioread8(priv->membase + UART_IER);
 425         ier |= flag & PCH_UART_IER_MASK;
 426         iowrite8(ier, priv->membase + UART_IER);
 427 }
 428
 429 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 430                                            unsigned int flag)
 431 {
 432         u8 ier = ioread8(priv->membase + UART_IER);
 433         ier &= ~(flag & PCH_UART_IER_MASK);
 434         iowrite8(ier, priv->membase + UART_IER);
 435 }
 436
 437 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
 438                                  unsigned int parity, unsigned int bits,
 439                                  unsigned int stb)
 440 {
 441         unsigned int dll, dlm, lcr;
 442         int div;
 443
 444         div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
 445         if (div < 0 || USHRT_MAX <= div) {
 446                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 447                 return -EINVAL;
 448         }
 449
 450         dll = (unsigned int)div & 0x00FFU;
 451         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 452
 453         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 454                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 455                 return -EINVAL;
 456         }
 457
 458         if (bits & ~PCH_UART_LCR_WLS) {
 459                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 460                 return -EINVAL;
 461         }
 462
 463         if (stb & ~PCH_UART_LCR_STB) {
 464                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 465                 return -EINVAL;
 466         }
 467
 468         lcr = parity;
 469         lcr |= bits;
 470         lcr |= stb;
 471
 472         dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
 473                  __func__, baud, div, lcr, jiffies);
 474         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 475         iowrite8(dll, priv->membase + PCH_UART_DLL);
 476         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 477         iowrite8(lcr, priv->membase + UART_LCR);
 478
 479         return 0;
 480 }
 481
 482 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 483                                     unsigned int flag)
 484 {
 485         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 486                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 487                         __func__, flag);
 488                 return -EINVAL;
 489         }
 490
 491         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 492         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 493                  priv->membase + UART_FCR);
 494         iowrite8(priv->fcr, priv->membase + UART_FCR);
 495
 496         return 0;
 497 }
 498
 499 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 500                                  unsigned int dmamode,
 501                                  unsigned int fifo_size, unsigned int trigger)
 502 {
 503         u8 fcr;
 504
 505         if (dmamode & ~PCH_UART_FCR_DMS) {
 506                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 507                         __func__, dmamode);
 508                 return -EINVAL;
 509         }
 510
 511         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 512                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 513                         __func__, fifo_size);
 514                 return -EINVAL;
 515         }
 516
 517         if (trigger & ~PCH_UART_FCR_RFTL) {
 518                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 519                         __func__, trigger);
 520                 return -EINVAL;
 521         }
 522
 523         switch (priv->fifo_size) {
 524         case 256:
 525                 priv->trigger_level =
 526                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 527                 break;
 528         case 64:
 529                 priv->trigger_level =
 530                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 531                 break;
 532         case 16:
 533                 priv->trigger_level =
 534                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 535                 break;
 536         default:
 537                 priv->trigger_level =
 538                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 539                 break;
 540         }
 541         fcr =
 542             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 543         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 544         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 545                  priv->membase + UART_FCR);
 546         iowrite8(fcr, priv->membase + UART_FCR);
 547         priv->fcr = fcr;
 548
 549         return 0;
 550 }
 551
 552 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 553 {
 554         unsigned int msr = ioread8(priv->membase + UART_MSR);
 555         priv->dmsr = msr & PCH_UART_MSR_DELTA;
 556         return (u8)msr;
 557 }
 558
 559 static void pch_uart_hal_write(struct eg20t_port *priv,
 560                               const unsigned char *buf, int tx_size)
 561 {
 562         int i;
 563         unsigned int thr;
 564
 565         for (i = 0; i < tx_size;) {
 566                 thr = buf[i++];
 567                 iowrite8(thr, priv->membase + PCH_UART_THR);
 568         }
 569 }
 570
 571 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 572                              int rx_size)
 573 {
 574         int i;
 575         u8 rbr, lsr;
 576         struct uart_port *port = &priv->port;
 577
 578         lsr = ioread8(priv->membase + UART_LSR);
 579         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 580              i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
 581              lsr = ioread8(priv->membase + UART_LSR)) {
 582                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 583
 584                 if (lsr & UART_LSR_BI) {
 585                         port->icount.brk++;
 586                         if (uart_handle_break(port))
 587                                 continue;
 588                 }
 589 #ifdef SUPPORT_SYSRQ
 590                 if (port->sysrq) {
 591                         if (uart_handle_sysrq_char(port, rbr))
 592                                 continue;
 593                 }
 594 #endif
 595
 596                 buf[i++] = rbr;
 597         }
 598         return i;
 599 }
 600
 601 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
 602 {
 603         return ioread8(priv->membase + UART_IIR) &\
 604                       (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
 605 }
 606
 607 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 608 {
 609         return ioread8(priv->membase + UART_LSR);
 610 }
 611
 612 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 613 {
 614         unsigned int lcr;
 615
 616         lcr = ioread8(priv->membase + UART_LCR);
 617         if (on)
 618                 lcr |= PCH_UART_LCR_SB;
 619         else
 620                 lcr &= ~PCH_UART_LCR_SB;
 621
 622         iowrite8(lcr, priv->membase + UART_LCR);
 623 }
 624
 625 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 626                    int size)
 627 {
 628         struct uart_port *port = &priv->port;
 629         struct tty_port *tport = &port->state->port;
 630
 631         tty_insert_flip_string(tport, buf, size);
 632         tty_flip_buffer_push(tport);
 633
 634         return 0;
 635 }
 636
 637 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 638 {
 639         int ret = 0;
 640         struct uart_port *port = &priv->port;
 641
 642         if (port->x_char) {
 643                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 644                         __func__, port->x_char, jiffies);
 645                 buf[0] = port->x_char;
 646                 port->x_char = 0;
 647                 ret = 1;
 648         }
 649
 650         return ret;
 651 }
 652
 653 static int dma_push_rx(struct eg20t_port *priv, int size)
 654 {
 655         int room;
 656         struct uart_port *port = &priv->port;
 657         struct tty_port *tport = &port->state->port;
 658
 659         room = tty_buffer_request_room(tport, size);
 660
 661         if (room < size)
 662                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 663                          size - room);
 664         if (!room)
 665                 return 0;
 666
 667         tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
 668
 669         port->icount.rx += room;
 670
 671         return room;
 672 }
 673
 674 static void pch_free_dma(struct uart_port *port)
 675 {
 676         struct eg20t_port *priv;
 677         priv = container_of(port, struct eg20t_port, port);
 678
 679         if (priv->chan_tx) {
 680                 dma_release_channel(priv->chan_tx);
 681                 priv->chan_tx = NULL;
 682         }
 683         if (priv->chan_rx) {
 684                 dma_release_channel(priv->chan_rx);
 685                 priv->chan_rx = NULL;
 686         }
 687
 688         if (priv->rx_buf_dma) {
 689                 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
 690                                   priv->rx_buf_dma);
 691                 priv->rx_buf_virt = NULL;
 692                 priv->rx_buf_dma = 0;
 693         }
 694
 695         return;
 696 }
 697
 698 static bool filter(struct dma_chan *chan, void *slave)
 699 {
 700         struct pch_dma_slave *param = slave;
 701
 702         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 703                                                   chan->device->dev)) {
 704                 chan->private = param;
 705                 return true;
 706         } else {
 707                 return false;
 708         }
 709 }
 710
 711 static void pch_request_dma(struct uart_port *port)
 712 {
 713         dma_cap_mask_t mask;
 714         struct dma_chan *chan;
 715         struct pci_dev *dma_dev;
 716         struct pch_dma_slave *param;
 717         struct eg20t_port *priv =
 718                                 container_of(port, struct eg20t_port, port);
 719         dma_cap_zero(mask);
 720         dma_cap_set(DMA_SLAVE, mask);
 721
 722         /* Get DMA's dev information */
 723         dma_dev = pci_get_slot(priv->pdev->bus,
 724                         PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
 725
 726         /* Set Tx DMA */
 727         param = &priv->param_tx;
 728         param->dma_dev = &dma_dev->dev;
 729         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 730
 731         param->tx_reg = port->mapbase + UART_TX;
 732         chan = dma_request_channel(mask, filter, param);
 733         if (!chan) {
 734                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 735                         __func__);
 736                 return;
 737         }
 738         priv->chan_tx = chan;
 739
 740         /* Set Rx DMA */
 741         param = &priv->param_rx;
 742         param->dma_dev = &dma_dev->dev;
 743         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 744
 745         param->rx_reg = port->mapbase + UART_RX;
 746         chan = dma_request_channel(mask, filter, param);
 747         if (!chan) {
 748                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 749                         __func__);
 750                 dma_release_channel(priv->chan_tx);
 751                 priv->chan_tx = NULL;
 752                 return;
 753         }
 754
 755         /* Get Consistent memory for DMA */
 756         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 757                                     &priv->rx_buf_dma, GFP_KERNEL);
 758         priv->chan_rx = chan;
 759 }
 760
 761 static void pch_dma_rx_complete(void *arg)
 762 {
 763         struct eg20t_port *priv = arg;
 764         struct uart_port *port = &priv->port;
 765         int count;
 766
 767         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 768         count = dma_push_rx(priv, priv->trigger_level);
 769         if (count)
 770                 tty_flip_buffer_push(&port->state->port);
 771         async_tx_ack(priv->desc_rx);
 772         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
 773                                             PCH_UART_HAL_RX_ERR_INT);
 774 }
 775
 776 static void pch_dma_tx_complete(void *arg)
 777 {
 778         struct eg20t_port *priv = arg;
 779         struct uart_port *port = &priv->port;
 780         struct circ_buf *xmit = &port->state->xmit;
 781         struct scatterlist *sg = priv->sg_tx_p;
 782         int i;
 783
 784         for (i = 0; i < priv->nent; i++, sg++) {
 785                 xmit->tail += sg_dma_len(sg);
 786                 port->icount.tx += sg_dma_len(sg);
 787         }
 788         xmit->tail &= UART_XMIT_SIZE - 1;
 789         async_tx_ack(priv->desc_tx);
 790         dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
 791         priv->tx_dma_use = 0;
 792         priv->nent = 0;
 793         kfree(priv->sg_tx_p);
 794         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 795 }
 796
 797 static int pop_tx(struct eg20t_port *priv, int size)
 798 {
 799         int count = 0;
 800         struct uart_port *port = &priv->port;
 801         struct circ_buf *xmit = &port->state->xmit;
 802
 803         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 804                 goto pop_tx_end;
 805
 806         do {
 807                 int cnt_to_end =
 808                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 809                 int sz = min(size - count, cnt_to_end);
 810                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 811                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 812                 count += sz;
 813         } while (!uart_circ_empty(xmit) && count < size);
 814
 815 pop_tx_end:
 816         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 817                  count, size - count, jiffies);
 818
 819         return count;
 820 }
 821
 822 static int handle_rx_to(struct eg20t_port *priv)
 823 {
 824         struct pch_uart_buffer *buf;
 825         int rx_size;
 826         int ret;
 827         if (!priv->start_rx) {
 828                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
 829                                                      PCH_UART_HAL_RX_ERR_INT);
 830                 return 0;
 831         }
 832         buf = &priv->rxbuf;
 833         do {
 834                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 835                 ret = push_rx(priv, buf->buf, rx_size);
 836                 if (ret)
 837                         return 0;
 838         } while (rx_size == buf->size);
 839
 840         return PCH_UART_HANDLED_RX_INT;
 841 }
 842
 843 static int handle_rx(struct eg20t_port *priv)
 844 {
 845         return handle_rx_to(priv);
 846 }
 847
 848 static int dma_handle_rx(struct eg20t_port *priv)
 849 {
 850         struct uart_port *port = &priv->port;
 851         struct dma_async_tx_descriptor *desc;
 852         struct scatterlist *sg;
 853
 854         priv = container_of(port, struct eg20t_port, port);
 855         sg = &priv->sg_rx;
 856
 857         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 858
 859         sg_dma_len(sg) = priv->trigger_level;
 860
 861         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 862                      sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
 863
 864         sg_dma_address(sg) = priv->rx_buf_dma;
 865
 866         desc = dmaengine_prep_slave_sg(priv->chan_rx,
 867                         sg, 1, DMA_DEV_TO_MEM,
 868                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 869
 870         if (!desc)
 871                 return 0;
 872
 873         priv->desc_rx = desc;
 874         desc->callback = pch_dma_rx_complete;
 875         desc->callback_param = priv;
 876         desc->tx_submit(desc);
 877         dma_async_issue_pending(priv->chan_rx);
 878
 879         return PCH_UART_HANDLED_RX_INT;
 880 }
 881
 882 static unsigned int handle_tx(struct eg20t_port *priv)
 883 {
 884         struct uart_port *port = &priv->port;
 885         struct circ_buf *xmit = &port->state->xmit;
 886         int fifo_size;
 887         int tx_size;
 888         int size;
 889         int tx_empty;
 890
 891         if (!priv->start_tx) {
 892                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 893                         __func__, jiffies);
 894                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 895                 priv->tx_empty = 1;
 896                 return 0;
 897         }
 898
 899         fifo_size = max(priv->fifo_size, 1);
 900         tx_empty = 1;
 901         if (pop_tx_x(priv, xmit->buf)) {
 902                 pch_uart_hal_write(priv, xmit->buf, 1);
 903                 port->icount.tx++;
 904                 tx_empty = 0;
 905                 fifo_size--;
 906         }
 907         size = min(xmit->head - xmit->tail, fifo_size);
 908         if (size < 0)
 909                 size = fifo_size;
 910
 911         tx_size = pop_tx(priv, size);
 912         if (tx_size > 0) {
 913                 port->icount.tx += tx_size;
 914                 tx_empty = 0;
 915         }
 916
 917         priv->tx_empty = tx_empty;
 918
 919         if (tx_empty) {
 920                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 921                 uart_write_wakeup(port);
 922         }
 923
 924         return PCH_UART_HANDLED_TX_INT;
 925 }
 926
 927 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 928 {
 929         struct uart_port *port = &priv->port;
 930         struct circ_buf *xmit = &port->state->xmit;
 931         struct scatterlist *sg;
 932         int nent;
 933         int fifo_size;
 934         struct dma_async_tx_descriptor *desc;
 935         int num;
 936         int i;
 937         int bytes;
 938         int size;
 939         int rem;
 940
 941         if (!priv->start_tx) {
 942                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 943                         __func__, jiffies);
 944                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 945                 priv->tx_empty = 1;
 946                 return 0;
 947         }
 948
 949         if (priv->tx_dma_use) {
 950                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 951                         __func__, jiffies);
 952                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 953                 priv->tx_empty = 1;
 954                 return 0;
 955         }
 956
 957         fifo_size = max(priv->fifo_size, 1);
 958         if (pop_tx_x(priv, xmit->buf)) {
 959                 pch_uart_hal_write(priv, xmit->buf, 1);
 960                 port->icount.tx++;
 961                 fifo_size--;
 962         }
 963
 964         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 965                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 966                              xmit->tail, UART_XMIT_SIZE));
 967         if (!bytes) {
 968                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 969                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 970                 uart_write_wakeup(port);
 971                 return 0;
 972         }
 973
 974         if (bytes > fifo_size) {
 975                 num = bytes / fifo_size + 1;
 976                 size = fifo_size;
 977                 rem = bytes % fifo_size;
 978         } else {
 979                 num = 1;
 980                 size = bytes;
 981                 rem = bytes;
 982         }
 983
 984         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
 985                 __func__, num, size, rem);
 986
 987         priv->tx_dma_use = 1;
 988
 989         priv->sg_tx_p = kcalloc(num, sizeof(struct scatterlist), GFP_ATOMIC);
 990         if (!priv->sg_tx_p) {
 991                 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
 992                 return 0;
 993         }
 994
 995         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 996         sg = priv->sg_tx_p;
 997
 998         for (i = 0; i < num; i++, sg++) {
 999                 if (i == (num - 1))
1000                         sg_set_page(sg, virt_to_page(xmit->buf),
1001                                     rem, fifo_size * i);
1002                 else
1003                         sg_set_page(sg, virt_to_page(xmit->buf),
1004                                     size, fifo_size * i);
1005         }
1006
1007         sg = priv->sg_tx_p;
1008         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1009         if (!nent) {
1010                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1011                 return 0;
1012         }
1013         priv->nent = nent;
1014
1015         for (i = 0; i < nent; i++, sg++) {
1016                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1017                               fifo_size * i;
1018                 sg_dma_address(sg) = (sg_dma_address(sg) &
1019                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
1020                 if (i == (nent - 1))
1021                         sg_dma_len(sg) = rem;
1022                 else
1023                         sg_dma_len(sg) = size;
1024         }
1025
1026         desc = dmaengine_prep_slave_sg(priv->chan_tx,
1027                                         priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1028                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1029         if (!desc) {
1030                 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1031                         __func__);
1032                 return 0;
1033         }
1034         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1035         priv->desc_tx = desc;
1036         desc->callback = pch_dma_tx_complete;
1037         desc->callback_param = priv;
1038
1039         desc->tx_submit(desc);
1040
1041         dma_async_issue_pending(priv->chan_tx);
1042
1043         return PCH_UART_HANDLED_TX_INT;
1044 }
1045
1046 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1047 {
1048         struct uart_port *port = &priv->port;
1049         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1050         char   *error_msg[5] = {};
1051         int    i = 0;
1052
1053         if (lsr & PCH_UART_LSR_ERR)
1054                 error_msg[i++] = "Error data in FIFO\n";
1055
1056         if (lsr & UART_LSR_FE) {
1057                 port->icount.frame++;
1058                 error_msg[i++] = "  Framing Error\n";
1059         }
1060
1061         if (lsr & UART_LSR_PE) {
1062                 port->icount.parity++;
1063                 error_msg[i++] = "  Parity Error\n";
1064         }
1065
1066         if (lsr & UART_LSR_OE) {
1067                 port->icount.overrun++;
1068                 error_msg[i++] = "  Overrun Error\n";
1069         }
1070
1071         if (tty == NULL) {
1072                 for (i = 0; error_msg[i] != NULL; i++)
1073                         dev_err(&priv->pdev->dev, error_msg[i]);
1074         } else {
1075                 tty_kref_put(tty);
1076         }
1077 }
1078
1079 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1080 {
1081         struct eg20t_port *priv = dev_id;
1082         unsigned int handled;
1083         u8 lsr;
1084         int ret = 0;
1085         unsigned char iid;
1086         unsigned long flags;
1087         int next = 1;
1088         u8 msr;
1089
1090         spin_lock_irqsave(&priv->lock, flags);
1091         handled = 0;
1092         while (next) {
1093                 iid = pch_uart_hal_get_iid(priv);
1094                 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1095                         break;
1096                 switch (iid) {
1097                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
1098                         lsr = pch_uart_hal_get_line_status(priv);
1099                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1100                                                 UART_LSR_PE | UART_LSR_OE)) {
1101                                 pch_uart_err_ir(priv, lsr);
1102                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
1103                         } else {
1104                                 ret = PCH_UART_HANDLED_LS_INT;
1105                         }
1106                         break;
1107                 case PCH_UART_IID_RDR:  /* Received Data Ready */
1108                         if (priv->use_dma) {
1109                                 pch_uart_hal_disable_interrupt(priv,
1110                                                 PCH_UART_HAL_RX_INT |
1111                                                 PCH_UART_HAL_RX_ERR_INT);
1112                                 ret = dma_handle_rx(priv);
1113                                 if (!ret)
1114                                         pch_uart_hal_enable_interrupt(priv,
1115                                                 PCH_UART_HAL_RX_INT |
1116                                                 PCH_UART_HAL_RX_ERR_INT);
1117                         } else {
1118                                 ret = handle_rx(priv);
1119                         }
1120                         break;
1121                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1122                                                    (FIFO Timeout) */
1123                         ret = handle_rx_to(priv);
1124                         break;
1125                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1126                                                    Empty */
1127                         if (priv->use_dma)
1128                                 ret = dma_handle_tx(priv);
1129                         else
1130                                 ret = handle_tx(priv);
1131                         break;
1132                 case PCH_UART_IID_MS:   /* Modem Status */
1133                         msr = pch_uart_hal_get_modem(priv);
1134                         next = 0; /* MS ir prioirty is the lowest. So, MS ir
1135                                      means final interrupt */
1136                         if ((msr & UART_MSR_ANY_DELTA) == 0)
1137                                 break;
1138                         ret |= PCH_UART_HANDLED_MS_INT;
1139                         break;
1140                 default:        /* Never junp to this label */
1141                         dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1142                                 iid, jiffies);
1143                         ret = -1;
1144                         next = 0;
1145                         break;
1146                 }
1147                 handled |= (unsigned int)ret;
1148         }
1149
1150         spin_unlock_irqrestore(&priv->lock, flags);
1151         return IRQ_RETVAL(handled);
1152 }
1153
1154 /* This function tests whether the transmitter fifo and shifter for the port
1155                                                 described by 'port' is empty. */
1156 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1157 {
1158         struct eg20t_port *priv;
1159
1160         priv = container_of(port, struct eg20t_port, port);
1161         if (priv->tx_empty)
1162                 return TIOCSER_TEMT;
1163         else
1164                 return 0;
1165 }
1166
1167 /* Returns the current state of modem control inputs. */
1168 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1169 {
1170         struct eg20t_port *priv;
1171         u8 modem;
1172         unsigned int ret = 0;
1173
1174         priv = container_of(port, struct eg20t_port, port);
1175         modem = pch_uart_hal_get_modem(priv);
1176
1177         if (modem & UART_MSR_DCD)
1178                 ret |= TIOCM_CAR;
1179
1180         if (modem & UART_MSR_RI)
1181                 ret |= TIOCM_RNG;
1182
1183         if (modem & UART_MSR_DSR)
1184                 ret |= TIOCM_DSR;
1185
1186         if (modem & UART_MSR_CTS)
1187                 ret |= TIOCM_CTS;
1188
1189         return ret;
1190 }
1191
1192 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1193 {
1194         u32 mcr = 0;
1195         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1196
1197         if (mctrl & TIOCM_DTR)
1198                 mcr |= UART_MCR_DTR;
1199         if (mctrl & TIOCM_RTS)
1200                 mcr |= UART_MCR_RTS;
1201         if (mctrl & TIOCM_LOOP)
1202                 mcr |= UART_MCR_LOOP;
1203
1204         if (priv->mcr & UART_MCR_AFE)
1205                 mcr |= UART_MCR_AFE;
1206
1207         if (mctrl)
1208                 iowrite8(mcr, priv->membase + UART_MCR);
1209 }
1210
1211 static void pch_uart_stop_tx(struct uart_port *port)
1212 {
1213         struct eg20t_port *priv;
1214         priv = container_of(port, struct eg20t_port, port);
1215         priv->start_tx = 0;
1216         priv->tx_dma_use = 0;
1217 }
1218
1219 static void pch_uart_start_tx(struct uart_port *port)
1220 {
1221         struct eg20t_port *priv;
1222
1223         priv = container_of(port, struct eg20t_port, port);
1224
1225         if (priv->use_dma) {
1226                 if (priv->tx_dma_use) {
1227                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1228                                 __func__);
1229                         return;
1230                 }
1231         }
1232
1233         priv->start_tx = 1;
1234         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1235 }
1236
1237 static void pch_uart_stop_rx(struct uart_port *port)
1238 {
1239         struct eg20t_port *priv;
1240         priv = container_of(port, struct eg20t_port, port);
1241         priv->start_rx = 0;
1242         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1243                                              PCH_UART_HAL_RX_ERR_INT);
1244 }
1245
1246 /* Enable the modem status interrupts. */
1247 static void pch_uart_enable_ms(struct uart_port *port)
1248 {
1249         struct eg20t_port *priv;
1250         priv = container_of(port, struct eg20t_port, port);
1251         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1252 }
1253
1254 /* Control the transmission of a break signal. */
1255 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1256 {
1257         struct eg20t_port *priv;
1258         unsigned long flags;
1259
1260         priv = container_of(port, struct eg20t_port, port);
1261         spin_lock_irqsave(&priv->lock, flags);
1262         pch_uart_hal_set_break(priv, ctl);
1263         spin_unlock_irqrestore(&priv->lock, flags);
1264 }
1265
1266 /* Grab any interrupt resources and initialise any low level driver state. */
1267 static int pch_uart_startup(struct uart_port *port)
1268 {
1269         struct eg20t_port *priv;
1270         int ret;
1271         int fifo_size;
1272         int trigger_level;
1273
1274         priv = container_of(port, struct eg20t_port, port);
1275         priv->tx_empty = 1;
1276
1277         if (port->uartclk)
1278                 priv->uartclk = port->uartclk;
1279         else
1280                 port->uartclk = priv->uartclk;
1281
1282         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1283         ret = pch_uart_hal_set_line(priv, default_baud,
1284                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1285                               PCH_UART_HAL_STB1);
1286         if (ret)
1287                 return ret;
1288
1289         switch (priv->fifo_size) {
1290         case 256:
1291                 fifo_size = PCH_UART_HAL_FIFO256;
1292                 break;
1293         case 64:
1294                 fifo_size = PCH_UART_HAL_FIFO64;
1295                 break;
1296         case 16:
1297                 fifo_size = PCH_UART_HAL_FIFO16;
1298                 break;
1299         case 1:
1300         default:
1301                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1302                 break;
1303         }
1304
1305         switch (priv->trigger) {
1306         case PCH_UART_HAL_TRIGGER1:
1307                 trigger_level = 1;
1308                 break;
1309         case PCH_UART_HAL_TRIGGER_L:
1310                 trigger_level = priv->fifo_size / 4;
1311                 break;
1312         case PCH_UART_HAL_TRIGGER_M:
1313                 trigger_level = priv->fifo_size / 2;
1314                 break;
1315         case PCH_UART_HAL_TRIGGER_H:
1316         default:
1317                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1318                 break;
1319         }
1320
1321         priv->trigger_level = trigger_level;
1322         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1323                                     fifo_size, priv->trigger);
1324         if (ret < 0)
1325                 return ret;
1326
1327         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1328                         priv->irq_name, priv);
1329         if (ret < 0)
1330                 return ret;
1331
1332         if (priv->use_dma)
1333                 pch_request_dma(port);
1334
1335         priv->start_rx = 1;
1336         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1337                                             PCH_UART_HAL_RX_ERR_INT);
1338         uart_update_timeout(port, CS8, default_baud);
1339
1340         return 0;
1341 }
1342
1343 static void pch_uart_shutdown(struct uart_port *port)
1344 {
1345         struct eg20t_port *priv;
1346         int ret;
1347
1348         priv = container_of(port, struct eg20t_port, port);
1349         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1350         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1351         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1352                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1353         if (ret)
1354                 dev_err(priv->port.dev,
1355                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1356
1357         pch_free_dma(port);
1358
1359         free_irq(priv->port.irq, priv);
1360 }
1361
1362 /* Change the port parameters, including word length, parity, stop
1363  *bits.  Update read_status_mask and ignore_status_mask to indicate
1364  *the types of events we are interested in receiving.  */
1365 static void pch_uart_set_termios(struct uart_port *port,
1366                                  struct ktermios *termios, struct ktermios *old)
1367 {
1368         int rtn;
1369         unsigned int baud, parity, bits, stb;
1370         struct eg20t_port *priv;
1371         unsigned long flags;
1372
1373         priv = container_of(port, struct eg20t_port, port);
1374         switch (termios->c_cflag & CSIZE) {
1375         case CS5:
1376                 bits = PCH_UART_HAL_5BIT;
1377                 break;
1378         case CS6:
1379                 bits = PCH_UART_HAL_6BIT;
1380                 break;
1381         case CS7:
1382                 bits = PCH_UART_HAL_7BIT;
1383                 break;
1384         default:                /* CS8 */
1385                 bits = PCH_UART_HAL_8BIT;
1386                 break;
1387         }
1388         if (termios->c_cflag & CSTOPB)
1389                 stb = PCH_UART_HAL_STB2;
1390         else
1391                 stb = PCH_UART_HAL_STB1;
1392
1393         if (termios->c_cflag & PARENB) {
1394                 if (termios->c_cflag & PARODD)
1395                         parity = PCH_UART_HAL_PARITY_ODD;
1396                 else
1397                         parity = PCH_UART_HAL_PARITY_EVEN;
1398
1399         } else
1400                 parity = PCH_UART_HAL_PARITY_NONE;
1401
1402         /* Only UART0 has auto hardware flow function */
1403         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1404                 priv->mcr |= UART_MCR_AFE;
1405         else
1406                 priv->mcr &= ~UART_MCR_AFE;
1407
1408         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1409
1410         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1411
1412         spin_lock_irqsave(&priv->lock, flags);
1413         spin_lock(&port->lock);
1414
1415         uart_update_timeout(port, termios->c_cflag, baud);
1416         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1417         if (rtn)
1418                 goto out;
1419
1420         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1421         /* Don't rewrite B0 */
1422         if (tty_termios_baud_rate(termios))
1423                 tty_termios_encode_baud_rate(termios, baud, baud);
1424
1425 out:
1426         spin_unlock(&port->lock);
1427         spin_unlock_irqrestore(&priv->lock, flags);
1428 }
1429
1430 static const char *pch_uart_type(struct uart_port *port)
1431 {
1432         return KBUILD_MODNAME;
1433 }
1434
1435 static void pch_uart_release_port(struct uart_port *port)
1436 {
1437         struct eg20t_port *priv;
1438
1439         priv = container_of(port, struct eg20t_port, port);
1440         pci_iounmap(priv->pdev, priv->membase);
1441         pci_release_regions(priv->pdev);
1442 }
1443
1444 static int pch_uart_request_port(struct uart_port *port)
1445 {
1446         struct eg20t_port *priv;
1447         int ret;
1448         void __iomem *membase;
1449
1450         priv = container_of(port, struct eg20t_port, port);
1451         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1452         if (ret < 0)
1453                 return -EBUSY;
1454
1455         membase = pci_iomap(priv->pdev, 1, 0);
1456         if (!membase) {
1457                 pci_release_regions(priv->pdev);
1458                 return -EBUSY;
1459         }
1460         priv->membase = port->membase = membase;
1461
1462         return 0;
1463 }
1464
1465 static void pch_uart_config_port(struct uart_port *port, int type)
1466 {
1467         struct eg20t_port *priv;
1468
1469         priv = container_of(port, struct eg20t_port, port);
1470         if (type & UART_CONFIG_TYPE) {
1471                 port->type = priv->port_type;
1472                 pch_uart_request_port(port);
1473         }
1474 }
1475
1476 static int pch_uart_verify_port(struct uart_port *port,
1477                                 struct serial_struct *serinfo)
1478 {
1479         struct eg20t_port *priv;
1480
1481         priv = container_of(port, struct eg20t_port, port);
1482         if (serinfo->flags & UPF_LOW_LATENCY) {
1483                 dev_info(priv->port.dev,
1484                         "PCH UART : Use PIO Mode (without DMA)\n");
1485                 priv->use_dma = 0;
1486                 serinfo->flags &= ~UPF_LOW_LATENCY;
1487         } else {
1488 #ifndef CONFIG_PCH_DMA
1489                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1490                         __func__);
1491                 return -EOPNOTSUPP;
1492 #endif
1493                 if (!priv->use_dma) {
1494                         pch_request_dma(port);
1495                         if (priv->chan_rx)
1496                                 priv->use_dma = 1;
1497                 }
1498                 dev_info(priv->port.dev, "PCH UART: %s\n",
1499                                 priv->use_dma ?
1500                                 "Use DMA Mode" : "No DMA");
1501         }
1502
1503         return 0;
1504 }
1505
1506 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1507 /*
1508  *      Wait for transmitter & holding register to empty
1509  */
1510 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1511 {
1512         unsigned int status, tmout = 10000;
1513
1514         /* Wait up to 10ms for the character(s) to be sent. */
1515         for (;;) {
1516                 status = ioread8(up->membase + UART_LSR);
1517
1518                 if ((status & bits) == bits)
1519                         break;
1520                 if (--tmout == 0)
1521                         break;
1522                 udelay(1);
1523         }
1524
1525         /* Wait up to 1s for flow control if necessary */
1526         if (up->port.flags & UPF_CONS_FLOW) {
1527                 unsigned int tmout;
1528                 for (tmout = 1000000; tmout; tmout--) {
1529                         unsigned int msr = ioread8(up->membase + UART_MSR);
1530                         if (msr & UART_MSR_CTS)
1531                                 break;
1532                         udelay(1);
1533                         touch_nmi_watchdog();
1534                 }
1535         }
1536 }
1537 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1538
1539 #ifdef CONFIG_CONSOLE_POLL
1540 /*
1541  * Console polling routines for communicate via uart while
1542  * in an interrupt or debug context.
1543  */
1544 static int pch_uart_get_poll_char(struct uart_port *port)
1545 {
1546         struct eg20t_port *priv =
1547                 container_of(port, struct eg20t_port, port);
1548         u8 lsr = ioread8(priv->membase + UART_LSR);
1549
1550         if (!(lsr & UART_LSR_DR))
1551                 return NO_POLL_CHAR;
1552
1553         return ioread8(priv->membase + PCH_UART_RBR);
1554 }
1555
1556
1557 static void pch_uart_put_poll_char(struct uart_port *port,
1558                          unsigned char c)
1559 {
1560         unsigned int ier;
1561         struct eg20t_port *priv =
1562                 container_of(port, struct eg20t_port, port);
1563
1564         /*
1565          * First save the IER then disable the interrupts
1566          */
1567         ier = ioread8(priv->membase + UART_IER);
1568         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1569
1570         wait_for_xmitr(priv, UART_LSR_THRE);
1571         /*
1572          * Send the character out.
1573          */
1574         iowrite8(c, priv->membase + PCH_UART_THR);
1575
1576         /*
1577          * Finally, wait for transmitter to become empty
1578          * and restore the IER
1579          */
1580         wait_for_xmitr(priv, BOTH_EMPTY);
1581         iowrite8(ier, priv->membase + UART_IER);
1582 }
1583 #endif /* CONFIG_CONSOLE_POLL */
1584
1585 static const struct uart_ops pch_uart_ops = {
1586         .tx_empty = pch_uart_tx_empty,
1587         .set_mctrl = pch_uart_set_mctrl,
1588         .get_mctrl = pch_uart_get_mctrl,
1589         .stop_tx = pch_uart_stop_tx,
1590         .start_tx = pch_uart_start_tx,
1591         .stop_rx = pch_uart_stop_rx,
1592         .enable_ms = pch_uart_enable_ms,
1593         .break_ctl = pch_uart_break_ctl,
1594         .startup = pch_uart_startup,
1595         .shutdown = pch_uart_shutdown,
1596         .set_termios = pch_uart_set_termios,
1597 /*      .pm             = pch_uart_pm,          Not supported yet */
1598         .type = pch_uart_type,
1599         .release_port = pch_uart_release_port,
1600         .request_port = pch_uart_request_port,
1601         .config_port = pch_uart_config_port,
1602         .verify_port = pch_uart_verify_port,
1603 #ifdef CONFIG_CONSOLE_POLL
1604         .poll_get_char = pch_uart_get_poll_char,
1605         .poll_put_char = pch_uart_put_poll_char,
1606 #endif
1607 };
1608
1609 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1610
1611 static void pch_console_putchar(struct uart_port *port, int ch)
1612 {
1613         struct eg20t_port *priv =
1614                 container_of(port, struct eg20t_port, port);
1615
1616         wait_for_xmitr(priv, UART_LSR_THRE);
1617         iowrite8(ch, priv->membase + PCH_UART_THR);
1618 }
1619
1620 /*
1621  *      Print a string to the serial port trying not to disturb
1622  *      any possible real use of the port...
1623  *
1624  *      The console_lock must be held when we get here.
1625  */
1626 static void
1627 pch_console_write(struct console *co, const char *s, unsigned int count)
1628 {
1629         struct eg20t_port *priv;
1630         unsigned long flags;
1631         int priv_locked = 1;
1632         int port_locked = 1;
1633         u8 ier;
1634
1635         priv = pch_uart_ports[co->index];
1636
1637         touch_nmi_watchdog();
1638
1639         local_irq_save(flags);
1640         if (priv->port.sysrq) {
1641                 /* call to uart_handle_sysrq_char already took the priv lock */
1642                 priv_locked = 0;
1643                 /* serial8250_handle_port() already took the port lock */
1644                 port_locked = 0;
1645         } else if (oops_in_progress) {
1646                 priv_locked = spin_trylock(&priv->lock);
1647                 port_locked = spin_trylock(&priv->port.lock);
1648         } else {
1649                 spin_lock(&priv->lock);
1650                 spin_lock(&priv->port.lock);
1651         }
1652
1653         /*
1654          *      First save the IER then disable the interrupts
1655          */
1656         ier = ioread8(priv->membase + UART_IER);
1657
1658         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1659
1660         uart_console_write(&priv->port, s, count, pch_console_putchar);
1661
1662         /*
1663          *      Finally, wait for transmitter to become empty
1664          *      and restore the IER
1665          */
1666         wait_for_xmitr(priv, BOTH_EMPTY);
1667         iowrite8(ier, priv->membase + UART_IER);
1668
1669         if (port_locked)
1670                 spin_unlock(&priv->port.lock);
1671         if (priv_locked)
1672                 spin_unlock(&priv->lock);
1673         local_irq_restore(flags);
1674 }
1675
1676 static int __init pch_console_setup(struct console *co, char *options)
1677 {
1678         struct uart_port *port;
1679         int baud = default_baud;
1680         int bits = 8;
1681         int parity = 'n';
1682         int flow = 'n';
1683
1684         /*
1685          * Check whether an invalid uart number has been specified, and
1686          * if so, search for the first available port that does have
1687          * console support.
1688          */
1689         if (co->index >= PCH_UART_NR)
1690                 co->index = 0;
1691         port = &pch_uart_ports[co->index]->port;
1692
1693         if (!port || (!port->iobase && !port->membase))
1694                 return -ENODEV;
1695
1696         port->uartclk = pch_uart_get_uartclk();
1697
1698         if (options)
1699                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1700
1701         return uart_set_options(port, co, baud, parity, bits, flow);
1702 }
1703
1704 static struct uart_driver pch_uart_driver;
1705
1706 static struct console pch_console = {
1707         .name           = PCH_UART_DRIVER_DEVICE,
1708         .write          = pch_console_write,
1709         .device         = uart_console_device,
1710         .setup          = pch_console_setup,
1711         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
1712         .index          = -1,
1713         .data           = &pch_uart_driver,
1714 };
1715
1716 #define PCH_CONSOLE     (&pch_console)
1717 #else
1718 #define PCH_CONSOLE     NULL
1719 #endif  /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1720
1721 static struct uart_driver pch_uart_driver = {
1722         .owner = THIS_MODULE,
1723         .driver_name = KBUILD_MODNAME,
1724         .dev_name = PCH_UART_DRIVER_DEVICE,
1725         .major = 0,
1726         .minor = 0,
1727         .nr = PCH_UART_NR,
1728         .cons = PCH_CONSOLE,
1729 };
1730
1731 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1732                                              const struct pci_device_id *id)
1733 {
1734         struct eg20t_port *priv;
1735         int ret;
1736         unsigned int iobase;
1737         unsigned int mapbase;
1738         unsigned char *rxbuf;
1739         int fifosize;
1740         int port_type;
1741         struct pch_uart_driver_data *board;
1742 #ifdef CONFIG_DEBUG_FS
1743         char name[32];  /* for debugfs file name */
1744 #endif
1745
1746         board = &drv_dat[id->driver_data];
1747         port_type = board->port_type;
1748
1749         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1750         if (priv == NULL)
1751                 goto init_port_alloc_err;
1752
1753         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1754         if (!rxbuf)
1755                 goto init_port_free_txbuf;
1756
1757         switch (port_type) {
1758         case PORT_PCH_8LINE:
1759                 fifosize = 256; /* EG20T/ML7213: UART0 */
1760                 break;
1761         case PORT_PCH_2LINE:
1762                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1763                 break;
1764         default:
1765                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1766                 goto init_port_hal_free;
1767         }
1768
1769         pci_enable_msi(pdev);
1770         pci_set_master(pdev);
1771
1772         spin_lock_init(&priv->lock);
1773
1774         iobase = pci_resource_start(pdev, 0);
1775         mapbase = pci_resource_start(pdev, 1);
1776         priv->mapbase = mapbase;
1777         priv->iobase = iobase;
1778         priv->pdev = pdev;
1779         priv->tx_empty = 1;
1780         priv->rxbuf.buf = rxbuf;
1781         priv->rxbuf.size = PAGE_SIZE;
1782
1783         priv->fifo_size = fifosize;
1784         priv->uartclk = pch_uart_get_uartclk();
1785         priv->port_type = port_type;
1786         priv->port.dev = &pdev->dev;
1787         priv->port.iobase = iobase;
1788         priv->port.membase = NULL;
1789         priv->port.mapbase = mapbase;
1790         priv->port.irq = pdev->irq;
1791         priv->port.iotype = UPIO_PORT;
1792         priv->port.ops = &pch_uart_ops;
1793         priv->port.flags = UPF_BOOT_AUTOCONF;
1794         priv->port.fifosize = fifosize;
1795         priv->port.line = board->line_no;
1796         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1797
1798         snprintf(priv->irq_name, IRQ_NAME_SIZE,
1799                  KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1800                  priv->port.line);
1801
1802         spin_lock_init(&priv->port.lock);
1803
1804         pci_set_drvdata(pdev, priv);
1805         priv->trigger_level = 1;
1806         priv->fcr = 0;
1807
1808         if (pdev->dev.of_node)
1809                 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1810                                          , &user_uartclk);
1811
1812 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1813         pch_uart_ports[board->line_no] = priv;
1814 #endif
1815         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1816         if (ret < 0)
1817                 goto init_port_hal_free;
1818
1819 #ifdef CONFIG_DEBUG_FS
1820         snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1821         priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1822                                 NULL, priv, &port_regs_ops);
1823 #endif
1824
1825         return priv;
1826
1827 init_port_hal_free:
1828 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1829         pch_uart_ports[board->line_no] = NULL;
1830 #endif
1831         free_page((unsigned long)rxbuf);
1832 init_port_free_txbuf:
1833         kfree(priv);
1834 init_port_alloc_err:
1835
1836         return NULL;
1837 }
1838
1839 static void pch_uart_exit_port(struct eg20t_port *priv)
1840 {
1841
1842 #ifdef CONFIG_DEBUG_FS
1843         debugfs_remove(priv->debugfs);
1844 #endif
1845         uart_remove_one_port(&pch_uart_driver, &priv->port);
1846         free_page((unsigned long)priv->rxbuf.buf);
1847 }
1848
1849 static void pch_uart_pci_remove(struct pci_dev *pdev)
1850 {
1851         struct eg20t_port *priv = pci_get_drvdata(pdev);
1852
1853         pci_disable_msi(pdev);
1854
1855 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1856         pch_uart_ports[priv->port.line] = NULL;
1857 #endif
1858         pch_uart_exit_port(priv);
1859         pci_disable_device(pdev);
1860         kfree(priv);
1861         return;
1862 }
1863 #ifdef CONFIG_PM
1864 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1865 {
1866         struct eg20t_port *priv = pci_get_drvdata(pdev);
1867
1868         uart_suspend_port(&pch_uart_driver, &priv->port);
1869
1870         pci_save_state(pdev);
1871         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1872         return 0;
1873 }
1874
1875 static int pch_uart_pci_resume(struct pci_dev *pdev)
1876 {
1877         struct eg20t_port *priv = pci_get_drvdata(pdev);
1878         int ret;
1879
1880         pci_set_power_state(pdev, PCI_D0);
1881         pci_restore_state(pdev);
1882
1883         ret = pci_enable_device(pdev);
1884         if (ret) {
1885                 dev_err(&pdev->dev,
1886                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1887                 return ret;
1888         }
1889
1890         uart_resume_port(&pch_uart_driver, &priv->port);
1891
1892         return 0;
1893 }
1894 #else
1895 #define pch_uart_pci_suspend NULL
1896 #define pch_uart_pci_resume NULL
1897 #endif
1898
1899 static const struct pci_device_id pch_uart_pci_id[] = {
1900         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1901          .driver_data = pch_et20t_uart0},
1902         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1903          .driver_data = pch_et20t_uart1},
1904         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1905          .driver_data = pch_et20t_uart2},
1906         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1907          .driver_data = pch_et20t_uart3},
1908         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1909          .driver_data = pch_ml7213_uart0},
1910         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1911          .driver_data = pch_ml7213_uart1},
1912         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1913          .driver_data = pch_ml7213_uart2},
1914         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1915          .driver_data = pch_ml7223_uart0},
1916         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1917          .driver_data = pch_ml7223_uart1},
1918         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1919          .driver_data = pch_ml7831_uart0},
1920         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1921          .driver_data = pch_ml7831_uart1},
1922         {0,},
1923 };
1924
1925 static int pch_uart_pci_probe(struct pci_dev *pdev,
1926                                         const struct pci_device_id *id)
1927 {
1928         int ret;
1929         struct eg20t_port *priv;
1930
1931         ret = pci_enable_device(pdev);
1932         if (ret < 0)
1933                 goto probe_error;
1934
1935         priv = pch_uart_init_port(pdev, id);
1936         if (!priv) {
1937                 ret = -EBUSY;
1938                 goto probe_disable_device;
1939         }
1940         pci_set_drvdata(pdev, priv);
1941
1942         return ret;
1943
1944 probe_disable_device:
1945         pci_disable_msi(pdev);
1946         pci_disable_device(pdev);
1947 probe_error:
1948         return ret;
1949 }
1950
1951 static struct pci_driver pch_uart_pci_driver = {
1952         .name = "pch_uart",
1953         .id_table = pch_uart_pci_id,
1954         .probe = pch_uart_pci_probe,
1955         .remove = pch_uart_pci_remove,
1956         .suspend = pch_uart_pci_suspend,
1957         .resume = pch_uart_pci_resume,
1958 };
1959
1960 static int __init pch_uart_module_init(void)
1961 {
1962         int ret;
1963
1964         /* register as UART driver */
1965         ret = uart_register_driver(&pch_uart_driver);
1966         if (ret < 0)
1967                 return ret;
1968
1969         /* register as PCI driver */
1970         ret = pci_register_driver(&pch_uart_pci_driver);
1971         if (ret < 0)
1972                 uart_unregister_driver(&pch_uart_driver);
1973
1974         return ret;
1975 }
1976 module_init(pch_uart_module_init);
1977
1978 static void __exit pch_uart_module_exit(void)
1979 {
1980         pci_unregister_driver(&pch_uart_pci_driver);
1981         uart_unregister_driver(&pch_uart_driver);
1982 }
1983 module_exit(pch_uart_module_exit);
1984
1985 MODULE_LICENSE("GPL v2");
1986 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1987 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
1988
1989 module_param(default_baud, uint, S_IRUGO);
1990 MODULE_PARM_DESC(default_baud,
1991                  "Default BAUD for initial driver state and console (default 9600)");
1992 module_param(user_uartclk, uint, S_IRUGO);
1993 MODULE_PARM_DESC(user_uartclk,
1994                  "Override UART default or board specific UART clock");