1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
8 * A note about mapbase / membase
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
14 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/ioport.h>
21 #include <linux/init.h>
22 #include <linux/console.h>
23 #include <linux/sysrq.h>
24 #include <linux/delay.h>
25 #include <linux/platform_device.h>
26 #include <linux/tty.h>
27 #include <linux/ratelimit.h>
28 #include <linux/tty_flip.h>
29 #include <linux/serial.h>
30 #include <linux/serial_8250.h>
31 #include <linux/nmi.h>
32 #include <linux/mutex.h>
33 #include <linux/slab.h>
34 #include <linux/uaccess.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/ktime.h>
44 * These are definitions for the Exar XR17V35X and XR17(C|D)15X
46 #define UART_EXAR_INT0 0x80
47 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
48 #define UART_EXAR_DVID 0x8d /* Device identification */
50 /* Nuvoton NPCM timeout register */
51 #define UART_NPCM_TOR 7
52 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
58 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
60 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
63 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
66 * Here we define the default xmit fifo size used for each type of UART.
68 static const struct serial8250_config uart_config[] = {
93 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
94 .rxtrig_bytes = {1, 4, 8, 14},
95 .flags = UART_CAP_FIFO,
106 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
112 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
114 .rxtrig_bytes = {8, 16, 24, 28},
115 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
121 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
123 .rxtrig_bytes = {1, 16, 32, 56},
124 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
132 .name = "16C950/954",
135 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
136 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
137 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
143 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
145 .rxtrig_bytes = {8, 16, 56, 60},
146 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
152 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
153 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
159 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
160 .flags = UART_CAP_FIFO,
166 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
167 .flags = UART_CAP_FIFO | UART_NATSEMI,
173 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
174 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
180 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
181 .flags = UART_CAP_FIFO,
187 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
188 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
195 .flags = UART_CAP_FIFO | UART_CAP_AFE,
201 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
203 .rxtrig_bytes = {1, 4, 8, 14},
204 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
211 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
220 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
227 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
228 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
229 .flags = UART_CAP_FIFO,
231 [PORT_BRCM_TRUMANAGE] = {
235 .flags = UART_CAP_HFIFO,
240 [PORT_ALTR_16550_F32] = {
241 .name = "Altera 16550 FIFO32",
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .rxtrig_bytes = {1, 8, 16, 30},
246 .flags = UART_CAP_FIFO | UART_CAP_AFE,
248 [PORT_ALTR_16550_F64] = {
249 .name = "Altera 16550 FIFO64",
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .rxtrig_bytes = {1, 16, 32, 62},
254 .flags = UART_CAP_FIFO | UART_CAP_AFE,
256 [PORT_ALTR_16550_F128] = {
257 .name = "Altera 16550 FIFO128",
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
261 .rxtrig_bytes = {1, 32, 64, 126},
262 .flags = UART_CAP_FIFO | UART_CAP_AFE,
265 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
266 * workaround of errata A-008006 which states that tx_loadsz should
267 * be configured less than Maximum supported fifo bytes.
269 [PORT_16550A_FSL64] = {
270 .name = "16550A_FSL64",
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
275 .flags = UART_CAP_FIFO,
278 .name = "Palmchip BK-3103",
281 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
282 .rxtrig_bytes = {1, 4, 8, 14},
283 .flags = UART_CAP_FIFO,
286 .name = "TI DA8xx/66AK2x",
289 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
291 .rxtrig_bytes = {1, 4, 8, 14},
292 .flags = UART_CAP_FIFO | UART_CAP_AFE,
295 .name = "MediaTek BTIF",
298 .fcr = UART_FCR_ENABLE_FIFO |
299 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
300 .flags = UART_CAP_FIFO,
303 .name = "Nuvoton 16550",
306 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
307 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
308 .rxtrig_bytes = {1, 4, 8, 14},
309 .flags = UART_CAP_FIFO,
313 /* Uart divisor latch read */
314 static int default_serial_dl_read(struct uart_8250_port *up)
316 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
319 /* Uart divisor latch write */
320 static void default_serial_dl_write(struct uart_8250_port *up, int value)
322 serial_out(up, UART_DLL, value & 0xff);
323 serial_out(up, UART_DLM, value >> 8 & 0xff);
326 #ifdef CONFIG_SERIAL_8250_RT288X
328 /* Au1x00/RT288x UART hardware has a weird register layout */
329 static const s8 au_io_in_map[8] = {
337 -1, /* UART_SCR (unmapped) */
340 static const s8 au_io_out_map[8] = {
346 -1, /* UART_LSR (unmapped) */
347 -1, /* UART_MSR (unmapped) */
348 -1, /* UART_SCR (unmapped) */
351 unsigned int au_serial_in(struct uart_port *p, int offset)
353 if (offset >= ARRAY_SIZE(au_io_in_map))
355 offset = au_io_in_map[offset];
358 return __raw_readl(p->membase + (offset << p->regshift));
361 void au_serial_out(struct uart_port *p, int offset, int value)
363 if (offset >= ARRAY_SIZE(au_io_out_map))
365 offset = au_io_out_map[offset];
368 __raw_writel(value, p->membase + (offset << p->regshift));
371 /* Au1x00 haven't got a standard divisor latch */
372 static int au_serial_dl_read(struct uart_8250_port *up)
374 return __raw_readl(up->port.membase + 0x28);
377 static void au_serial_dl_write(struct uart_8250_port *up, int value)
379 __raw_writel(value, up->port.membase + 0x28);
384 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
386 offset = offset << p->regshift;
387 outb(p->hub6 - 1 + offset, p->iobase);
388 return inb(p->iobase + 1);
391 static void hub6_serial_out(struct uart_port *p, int offset, int value)
393 offset = offset << p->regshift;
394 outb(p->hub6 - 1 + offset, p->iobase);
395 outb(value, p->iobase + 1);
398 static unsigned int mem_serial_in(struct uart_port *p, int offset)
400 offset = offset << p->regshift;
401 return readb(p->membase + offset);
404 static void mem_serial_out(struct uart_port *p, int offset, int value)
406 offset = offset << p->regshift;
407 writeb(value, p->membase + offset);
410 static void mem16_serial_out(struct uart_port *p, int offset, int value)
412 offset = offset << p->regshift;
413 writew(value, p->membase + offset);
416 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
418 offset = offset << p->regshift;
419 return readw(p->membase + offset);
422 static void mem32_serial_out(struct uart_port *p, int offset, int value)
424 offset = offset << p->regshift;
425 writel(value, p->membase + offset);
428 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
430 offset = offset << p->regshift;
431 return readl(p->membase + offset);
434 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
436 offset = offset << p->regshift;
437 iowrite32be(value, p->membase + offset);
440 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
442 offset = offset << p->regshift;
443 return ioread32be(p->membase + offset);
446 static unsigned int io_serial_in(struct uart_port *p, int offset)
448 offset = offset << p->regshift;
449 return inb(p->iobase + offset);
452 static void io_serial_out(struct uart_port *p, int offset, int value)
454 offset = offset << p->regshift;
455 outb(value, p->iobase + offset);
458 static int serial8250_default_handle_irq(struct uart_port *port);
460 static void set_io_from_upio(struct uart_port *p)
462 struct uart_8250_port *up = up_to_u8250p(p);
464 up->dl_read = default_serial_dl_read;
465 up->dl_write = default_serial_dl_write;
469 p->serial_in = hub6_serial_in;
470 p->serial_out = hub6_serial_out;
474 p->serial_in = mem_serial_in;
475 p->serial_out = mem_serial_out;
479 p->serial_in = mem16_serial_in;
480 p->serial_out = mem16_serial_out;
484 p->serial_in = mem32_serial_in;
485 p->serial_out = mem32_serial_out;
489 p->serial_in = mem32be_serial_in;
490 p->serial_out = mem32be_serial_out;
493 #ifdef CONFIG_SERIAL_8250_RT288X
495 p->serial_in = au_serial_in;
496 p->serial_out = au_serial_out;
497 up->dl_read = au_serial_dl_read;
498 up->dl_write = au_serial_dl_write;
503 p->serial_in = io_serial_in;
504 p->serial_out = io_serial_out;
507 /* Remember loaded iotype */
508 up->cur_iotype = p->iotype;
509 p->handle_irq = serial8250_default_handle_irq;
513 serial_port_out_sync(struct uart_port *p, int offset, int value)
521 p->serial_out(p, offset, value);
522 p->serial_in(p, UART_LCR); /* safe, no side-effects */
525 p->serial_out(p, offset, value);
532 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
534 serial_out(up, UART_SCR, offset);
535 serial_out(up, UART_ICR, value);
538 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
542 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
543 serial_out(up, UART_SCR, offset);
544 value = serial_in(up, UART_ICR);
545 serial_icr_write(up, UART_ACR, up->acr);
553 static void serial8250_clear_fifos(struct uart_8250_port *p)
555 if (p->capabilities & UART_CAP_FIFO) {
556 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
557 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
558 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
559 serial_out(p, UART_FCR, 0);
563 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
565 unsigned char mcr = serial8250_in_MCR(p);
567 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
570 mcr &= ~UART_MCR_RTS;
571 serial8250_out_MCR(p, mcr);
574 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
575 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
577 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
579 serial8250_clear_fifos(p);
580 serial_out(p, UART_FCR, p->fcr);
582 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
584 void serial8250_rpm_get(struct uart_8250_port *p)
586 if (!(p->capabilities & UART_CAP_RPM))
588 pm_runtime_get_sync(p->port.dev);
590 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
592 void serial8250_rpm_put(struct uart_8250_port *p)
594 if (!(p->capabilities & UART_CAP_RPM))
596 pm_runtime_mark_last_busy(p->port.dev);
597 pm_runtime_put_autosuspend(p->port.dev);
599 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
602 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
603 * @p: uart_8250_port port instance
605 * The function is used to start rs485 software emulating on the
606 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
607 * transmission. The function is idempotent, so it is safe to call it
610 * The caller MUST enable interrupt on empty shift register before
611 * calling serial8250_em485_init(). This interrupt is not a part of
612 * 8250 standard, but implementation defined.
614 * The function is supposed to be called from .rs485_config callback
615 * or from any other callback protected with p->port.lock spinlock.
617 * See also serial8250_em485_destroy()
619 * Return 0 - success, -errno - otherwise
621 int serial8250_em485_init(struct uart_8250_port *p)
626 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
630 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
632 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
634 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
635 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
637 p->em485->active_timer = NULL;
638 serial8250_em485_rts_after_send(p);
642 EXPORT_SYMBOL_GPL(serial8250_em485_init);
645 * serial8250_em485_destroy() - put uart_8250_port into normal state
646 * @p: uart_8250_port port instance
648 * The function is used to stop rs485 software emulating on the
649 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
650 * call it multiple times.
652 * The function is supposed to be called from .rs485_config callback
653 * or from any other callback protected with p->port.lock spinlock.
655 * See also serial8250_em485_init()
657 void serial8250_em485_destroy(struct uart_8250_port *p)
662 hrtimer_cancel(&p->em485->start_tx_timer);
663 hrtimer_cancel(&p->em485->stop_tx_timer);
668 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
671 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
672 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
673 * empty and the HW can idle again.
675 void serial8250_rpm_get_tx(struct uart_8250_port *p)
677 unsigned char rpm_active;
679 if (!(p->capabilities & UART_CAP_RPM))
682 rpm_active = xchg(&p->rpm_tx_active, 1);
685 pm_runtime_get_sync(p->port.dev);
687 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
689 void serial8250_rpm_put_tx(struct uart_8250_port *p)
691 unsigned char rpm_active;
693 if (!(p->capabilities & UART_CAP_RPM))
696 rpm_active = xchg(&p->rpm_tx_active, 0);
699 pm_runtime_mark_last_busy(p->port.dev);
700 pm_runtime_put_autosuspend(p->port.dev);
702 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
705 * IER sleep support. UARTs which have EFRs need the "extended
706 * capability" bit enabled. Note that on XR16C850s, we need to
707 * reset LCR to write to IER.
709 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
711 unsigned char lcr = 0, efr = 0;
713 * Exar UARTs have a SLEEP register that enables or disables
714 * each UART to enter sleep mode separately. On the XR17V35x the
715 * register is accessible to each UART at the UART_EXAR_SLEEP
716 * offset but the UART channel may only write to the corresponding
719 serial8250_rpm_get(p);
720 if ((p->port.type == PORT_XR17V35X) ||
721 (p->port.type == PORT_XR17D15X)) {
722 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
726 if (p->capabilities & UART_CAP_SLEEP) {
727 if (p->capabilities & UART_CAP_EFR) {
728 lcr = serial_in(p, UART_LCR);
729 efr = serial_in(p, UART_EFR);
730 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
731 serial_out(p, UART_EFR, UART_EFR_ECB);
732 serial_out(p, UART_LCR, 0);
734 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
735 if (p->capabilities & UART_CAP_EFR) {
736 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
737 serial_out(p, UART_EFR, efr);
738 serial_out(p, UART_LCR, lcr);
742 serial8250_rpm_put(p);
745 #ifdef CONFIG_SERIAL_8250_RSA
747 * Attempts to turn on the RSA FIFO. Returns zero on failure.
748 * We set the port uart clock rate if we succeed.
750 static int __enable_rsa(struct uart_8250_port *up)
755 mode = serial_in(up, UART_RSA_MSR);
756 result = mode & UART_RSA_MSR_FIFO;
759 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
760 mode = serial_in(up, UART_RSA_MSR);
761 result = mode & UART_RSA_MSR_FIFO;
765 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
770 static void enable_rsa(struct uart_8250_port *up)
772 if (up->port.type == PORT_RSA) {
773 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
774 spin_lock_irq(&up->port.lock);
776 spin_unlock_irq(&up->port.lock);
778 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
779 serial_out(up, UART_RSA_FRR, 0);
784 * Attempts to turn off the RSA FIFO. Returns zero on failure.
785 * It is unknown why interrupts were disabled in here. However,
786 * the caller is expected to preserve this behaviour by grabbing
787 * the spinlock before calling this function.
789 static void disable_rsa(struct uart_8250_port *up)
794 if (up->port.type == PORT_RSA &&
795 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
796 spin_lock_irq(&up->port.lock);
798 mode = serial_in(up, UART_RSA_MSR);
799 result = !(mode & UART_RSA_MSR_FIFO);
802 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
803 mode = serial_in(up, UART_RSA_MSR);
804 result = !(mode & UART_RSA_MSR_FIFO);
808 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
809 spin_unlock_irq(&up->port.lock);
812 #endif /* CONFIG_SERIAL_8250_RSA */
815 * This is a quickie test to see how big the FIFO is.
816 * It doesn't work at all the time, more's the pity.
818 static int size_fifo(struct uart_8250_port *up)
820 unsigned char old_fcr, old_mcr, old_lcr;
821 unsigned short old_dl;
824 old_lcr = serial_in(up, UART_LCR);
825 serial_out(up, UART_LCR, 0);
826 old_fcr = serial_in(up, UART_FCR);
827 old_mcr = serial8250_in_MCR(up);
828 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
829 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
830 serial8250_out_MCR(up, UART_MCR_LOOP);
831 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
832 old_dl = serial_dl_read(up);
833 serial_dl_write(up, 0x0001);
834 serial_out(up, UART_LCR, 0x03);
835 for (count = 0; count < 256; count++)
836 serial_out(up, UART_TX, count);
837 mdelay(20);/* FIXME - schedule_timeout */
838 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
839 (count < 256); count++)
840 serial_in(up, UART_RX);
841 serial_out(up, UART_FCR, old_fcr);
842 serial8250_out_MCR(up, old_mcr);
843 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
844 serial_dl_write(up, old_dl);
845 serial_out(up, UART_LCR, old_lcr);
851 * Read UART ID using the divisor method - set DLL and DLM to zero
852 * and the revision will be in DLL and device type in DLM. We
853 * preserve the device state across this.
855 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
857 unsigned char old_lcr;
858 unsigned int id, old_dl;
860 old_lcr = serial_in(p, UART_LCR);
861 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
862 old_dl = serial_dl_read(p);
863 serial_dl_write(p, 0);
864 id = serial_dl_read(p);
865 serial_dl_write(p, old_dl);
867 serial_out(p, UART_LCR, old_lcr);
873 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
874 * When this function is called we know it is at least a StarTech
875 * 16650 V2, but it might be one of several StarTech UARTs, or one of
876 * its clones. (We treat the broken original StarTech 16650 V1 as a
877 * 16550, and why not? Startech doesn't seem to even acknowledge its
880 * What evil have men's minds wrought...
882 static void autoconfig_has_efr(struct uart_8250_port *up)
884 unsigned int id1, id2, id3, rev;
887 * Everything with an EFR has SLEEP
889 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
892 * First we check to see if it's an Oxford Semiconductor UART.
894 * If we have to do this here because some non-National
895 * Semiconductor clone chips lock up if you try writing to the
896 * LSR register (which serial_icr_read does)
900 * Check for Oxford Semiconductor 16C950.
902 * EFR [4] must be set else this test fails.
904 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
905 * claims that it's needed for 952 dual UART's (which are not
906 * recommended for new designs).
909 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
910 serial_out(up, UART_EFR, UART_EFR_ECB);
911 serial_out(up, UART_LCR, 0x00);
912 id1 = serial_icr_read(up, UART_ID1);
913 id2 = serial_icr_read(up, UART_ID2);
914 id3 = serial_icr_read(up, UART_ID3);
915 rev = serial_icr_read(up, UART_REV);
917 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
919 if (id1 == 0x16 && id2 == 0xC9 &&
920 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
921 up->port.type = PORT_16C950;
924 * Enable work around for the Oxford Semiconductor 952 rev B
925 * chip which causes it to seriously miscalculate baud rates
928 if (id3 == 0x52 && rev == 0x01)
929 up->bugs |= UART_BUG_QUOT;
934 * We check for a XR16C850 by setting DLL and DLM to 0, and then
935 * reading back DLL and DLM. The chip type depends on the DLM
937 * 0x10 - XR16C850 and the DLL contains the chip revision.
941 id1 = autoconfig_read_divisor_id(up);
942 DEBUG_AUTOCONF("850id=%04x ", id1);
945 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
946 up->port.type = PORT_16850;
951 * It wasn't an XR16C850.
953 * We distinguish between the '654 and the '650 by counting
954 * how many bytes are in the FIFO. I'm using this for now,
955 * since that's the technique that was sent to me in the
956 * serial driver update, but I'm not convinced this works.
957 * I've had problems doing this in the past. -TYT
959 if (size_fifo(up) == 64)
960 up->port.type = PORT_16654;
962 up->port.type = PORT_16650V2;
966 * We detected a chip without a FIFO. Only two fall into
967 * this category - the original 8250 and the 16450. The
968 * 16450 has a scratch register (accessible with LCR=0)
970 static void autoconfig_8250(struct uart_8250_port *up)
972 unsigned char scratch, status1, status2;
974 up->port.type = PORT_8250;
976 scratch = serial_in(up, UART_SCR);
977 serial_out(up, UART_SCR, 0xa5);
978 status1 = serial_in(up, UART_SCR);
979 serial_out(up, UART_SCR, 0x5a);
980 status2 = serial_in(up, UART_SCR);
981 serial_out(up, UART_SCR, scratch);
983 if (status1 == 0xa5 && status2 == 0x5a)
984 up->port.type = PORT_16450;
987 static int broken_efr(struct uart_8250_port *up)
990 * Exar ST16C2550 "A2" devices incorrectly detect as
991 * having an EFR, and report an ID of 0x0201. See
992 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
994 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1001 * We know that the chip has FIFOs. Does it have an EFR? The
1002 * EFR is located in the same register position as the IIR and
1003 * we know the top two bits of the IIR are currently set. The
1004 * EFR should contain zero. Try to read the EFR.
1006 static void autoconfig_16550a(struct uart_8250_port *up)
1008 unsigned char status1, status2;
1009 unsigned int iersave;
1011 up->port.type = PORT_16550A;
1012 up->capabilities |= UART_CAP_FIFO;
1015 * XR17V35x UARTs have an extra divisor register, DLD
1016 * that gets enabled with when DLAB is set which will
1017 * cause the device to incorrectly match and assign
1018 * port type to PORT_16650. The EFR for this UART is
1019 * found at offset 0x09. Instead check the Deice ID (DVID)
1020 * register for a 2, 4 or 8 port UART.
1022 if (up->port.flags & UPF_EXAR_EFR) {
1023 status1 = serial_in(up, UART_EXAR_DVID);
1024 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
1025 DEBUG_AUTOCONF("Exar XR17V35x ");
1026 up->port.type = PORT_XR17V35X;
1027 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1036 * Check for presence of the EFR when DLAB is set.
1037 * Only ST16C650V1 UARTs pass this test.
1039 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1040 if (serial_in(up, UART_EFR) == 0) {
1041 serial_out(up, UART_EFR, 0xA8);
1042 if (serial_in(up, UART_EFR) != 0) {
1043 DEBUG_AUTOCONF("EFRv1 ");
1044 up->port.type = PORT_16650;
1045 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1047 serial_out(up, UART_LCR, 0);
1048 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1050 status1 = serial_in(up, UART_IIR) >> 5;
1051 serial_out(up, UART_FCR, 0);
1052 serial_out(up, UART_LCR, 0);
1055 up->port.type = PORT_16550A_FSL64;
1057 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1059 serial_out(up, UART_EFR, 0);
1064 * Maybe it requires 0xbf to be written to the LCR.
1065 * (other ST16C650V2 UARTs, TI16C752A, etc)
1067 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1068 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1069 DEBUG_AUTOCONF("EFRv2 ");
1070 autoconfig_has_efr(up);
1075 * Check for a National Semiconductor SuperIO chip.
1076 * Attempt to switch to bank 2, read the value of the LOOP bit
1077 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1078 * switch back to bank 2, read it from EXCR1 again and check
1079 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1081 serial_out(up, UART_LCR, 0);
1082 status1 = serial8250_in_MCR(up);
1083 serial_out(up, UART_LCR, 0xE0);
1084 status2 = serial_in(up, 0x02); /* EXCR1 */
1086 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1087 serial_out(up, UART_LCR, 0);
1088 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1089 serial_out(up, UART_LCR, 0xE0);
1090 status2 = serial_in(up, 0x02); /* EXCR1 */
1091 serial_out(up, UART_LCR, 0);
1092 serial8250_out_MCR(up, status1);
1094 if ((status2 ^ status1) & UART_MCR_LOOP) {
1095 unsigned short quot;
1097 serial_out(up, UART_LCR, 0xE0);
1099 quot = serial_dl_read(up);
1102 if (ns16550a_goto_highspeed(up))
1103 serial_dl_write(up, quot);
1105 serial_out(up, UART_LCR, 0);
1107 up->port.uartclk = 921600*16;
1108 up->port.type = PORT_NS16550A;
1109 up->capabilities |= UART_NATSEMI;
1115 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1116 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1117 * Try setting it with and without DLAB set. Cheap clones
1118 * set bit 5 without DLAB set.
1120 serial_out(up, UART_LCR, 0);
1121 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1122 status1 = serial_in(up, UART_IIR) >> 5;
1123 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1124 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1125 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1126 status2 = serial_in(up, UART_IIR) >> 5;
1127 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1128 serial_out(up, UART_LCR, 0);
1130 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1132 if (status1 == 6 && status2 == 7) {
1133 up->port.type = PORT_16750;
1134 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1139 * Try writing and reading the UART_IER_UUE bit (b6).
1140 * If it works, this is probably one of the Xscale platform's
1142 * We're going to explicitly set the UUE bit to 0 before
1143 * trying to write and read a 1 just to make sure it's not
1144 * already a 1 and maybe locked there before we even start start.
1146 iersave = serial_in(up, UART_IER);
1147 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1148 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1150 * OK it's in a known zero state, try writing and reading
1151 * without disturbing the current state of the other bits.
1153 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1154 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1157 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1159 DEBUG_AUTOCONF("Xscale ");
1160 up->port.type = PORT_XSCALE;
1161 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1166 * If we got here we couldn't force the IER_UUE bit to 0.
1167 * Log it and continue.
1169 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1171 serial_out(up, UART_IER, iersave);
1174 * Exar uarts have EFR in a weird location
1176 if (up->port.flags & UPF_EXAR_EFR) {
1177 DEBUG_AUTOCONF("Exar XR17D15x ");
1178 up->port.type = PORT_XR17D15X;
1179 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1186 * We distinguish between 16550A and U6 16550A by counting
1187 * how many bytes are in the FIFO.
1189 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1190 up->port.type = PORT_U6_16550A;
1191 up->capabilities |= UART_CAP_AFE;
1196 * This routine is called by rs_init() to initialize a specific serial
1197 * port. It determines what type of UART chip this serial port is
1198 * using: 8250, 16450, 16550, 16550A. The important question is
1199 * whether or not this UART is a 16550A or not, since this will
1200 * determine whether or not we can use its FIFO features or not.
1202 static void autoconfig(struct uart_8250_port *up)
1204 unsigned char status1, scratch, scratch2, scratch3;
1205 unsigned char save_lcr, save_mcr;
1206 struct uart_port *port = &up->port;
1207 unsigned long flags;
1208 unsigned int old_capabilities;
1210 if (!port->iobase && !port->mapbase && !port->membase)
1213 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1214 port->name, port->iobase, port->membase);
1217 * We really do need global IRQs disabled here - we're going to
1218 * be frobbing the chips IRQ enable register to see if it exists.
1220 spin_lock_irqsave(&port->lock, flags);
1222 up->capabilities = 0;
1225 if (!(port->flags & UPF_BUGGY_UART)) {
1227 * Do a simple existence test first; if we fail this,
1228 * there's no point trying anything else.
1230 * 0x80 is used as a nonsense port to prevent against
1231 * false positives due to ISA bus float. The
1232 * assumption is that 0x80 is a non-existent port;
1233 * which should be safe since include/asm/io.h also
1234 * makes this assumption.
1236 * Note: this is safe as long as MCR bit 4 is clear
1237 * and the device is in "PC" mode.
1239 scratch = serial_in(up, UART_IER);
1240 serial_out(up, UART_IER, 0);
1245 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1246 * 16C754B) allow only to modify them if an EFR bit is set.
1248 scratch2 = serial_in(up, UART_IER) & 0x0f;
1249 serial_out(up, UART_IER, 0x0F);
1253 scratch3 = serial_in(up, UART_IER) & 0x0f;
1254 serial_out(up, UART_IER, scratch);
1255 if (scratch2 != 0 || scratch3 != 0x0F) {
1257 * We failed; there's nothing here
1259 spin_unlock_irqrestore(&port->lock, flags);
1260 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1261 scratch2, scratch3);
1266 save_mcr = serial8250_in_MCR(up);
1267 save_lcr = serial_in(up, UART_LCR);
1270 * Check to see if a UART is really there. Certain broken
1271 * internal modems based on the Rockwell chipset fail this
1272 * test, because they apparently don't implement the loopback
1273 * test mode. So this test is skipped on the COM 1 through
1274 * COM 4 ports. This *should* be safe, since no board
1275 * manufacturer would be stupid enough to design a board
1276 * that conflicts with COM 1-4 --- we hope!
1278 if (!(port->flags & UPF_SKIP_TEST)) {
1279 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1280 status1 = serial_in(up, UART_MSR) & 0xF0;
1281 serial8250_out_MCR(up, save_mcr);
1282 if (status1 != 0x90) {
1283 spin_unlock_irqrestore(&port->lock, flags);
1284 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1291 * We're pretty sure there's a port here. Lets find out what
1292 * type of port it is. The IIR top two bits allows us to find
1293 * out if it's 8250 or 16450, 16550, 16550A or later. This
1294 * determines what we test for next.
1296 * We also initialise the EFR (if any) to zero for later. The
1297 * EFR occupies the same register location as the FCR and IIR.
1299 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1300 serial_out(up, UART_EFR, 0);
1301 serial_out(up, UART_LCR, 0);
1303 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1304 scratch = serial_in(up, UART_IIR) >> 6;
1308 autoconfig_8250(up);
1311 port->type = PORT_UNKNOWN;
1314 port->type = PORT_16550;
1317 autoconfig_16550a(up);
1321 #ifdef CONFIG_SERIAL_8250_RSA
1323 * Only probe for RSA ports if we got the region.
1325 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1327 port->type = PORT_RSA;
1330 serial_out(up, UART_LCR, save_lcr);
1332 port->fifosize = uart_config[up->port.type].fifo_size;
1333 old_capabilities = up->capabilities;
1334 up->capabilities = uart_config[port->type].flags;
1335 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1337 if (port->type == PORT_UNKNOWN)
1343 #ifdef CONFIG_SERIAL_8250_RSA
1344 if (port->type == PORT_RSA)
1345 serial_out(up, UART_RSA_FRR, 0);
1347 serial8250_out_MCR(up, save_mcr);
1348 serial8250_clear_fifos(up);
1349 serial_in(up, UART_RX);
1350 if (up->capabilities & UART_CAP_UUE)
1351 serial_out(up, UART_IER, UART_IER_UUE);
1353 serial_out(up, UART_IER, 0);
1356 spin_unlock_irqrestore(&port->lock, flags);
1359 * Check if the device is a Fintek F81216A
1361 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1362 fintek_8250_probe(up);
1364 if (up->capabilities != old_capabilities) {
1365 pr_warn("%s: detected caps %08x should be %08x\n",
1366 port->name, old_capabilities, up->capabilities);
1369 DEBUG_AUTOCONF("iir=%d ", scratch);
1370 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1373 static void autoconfig_irq(struct uart_8250_port *up)
1375 struct uart_port *port = &up->port;
1376 unsigned char save_mcr, save_ier;
1377 unsigned char save_ICP = 0;
1378 unsigned int ICP = 0;
1382 if (port->flags & UPF_FOURPORT) {
1383 ICP = (port->iobase & 0xfe0) | 0x1f;
1384 save_ICP = inb_p(ICP);
1389 if (uart_console(port))
1392 /* forget possible initially masked and pending IRQ */
1393 probe_irq_off(probe_irq_on());
1394 save_mcr = serial8250_in_MCR(up);
1395 save_ier = serial_in(up, UART_IER);
1396 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1398 irqs = probe_irq_on();
1399 serial8250_out_MCR(up, 0);
1401 if (port->flags & UPF_FOURPORT) {
1402 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1404 serial8250_out_MCR(up,
1405 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1407 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1408 serial_in(up, UART_LSR);
1409 serial_in(up, UART_RX);
1410 serial_in(up, UART_IIR);
1411 serial_in(up, UART_MSR);
1412 serial_out(up, UART_TX, 0xFF);
1414 irq = probe_irq_off(irqs);
1416 serial8250_out_MCR(up, save_mcr);
1417 serial_out(up, UART_IER, save_ier);
1419 if (port->flags & UPF_FOURPORT)
1420 outb_p(save_ICP, ICP);
1422 if (uart_console(port))
1425 port->irq = (irq > 0) ? irq : 0;
1428 static void serial8250_stop_rx(struct uart_port *port)
1430 struct uart_8250_port *up = up_to_u8250p(port);
1432 serial8250_rpm_get(up);
1434 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1435 up->port.read_status_mask &= ~UART_LSR_DR;
1436 serial_port_out(port, UART_IER, up->ier);
1438 serial8250_rpm_put(up);
1441 static void __do_stop_tx_rs485(struct uart_8250_port *p)
1443 serial8250_em485_rts_after_send(p);
1446 * Empty the RX FIFO, we are not interested in anything
1447 * received during the half-duplex transmission.
1448 * Enable previously disabled RX interrupts.
1450 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1451 serial8250_clear_and_reinit_fifos(p);
1453 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1454 serial_port_out(&p->port, UART_IER, p->ier);
1457 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1459 struct uart_8250_em485 *em485;
1460 struct uart_8250_port *p;
1461 unsigned long flags;
1463 em485 = container_of(t, struct uart_8250_em485, stop_tx_timer);
1466 serial8250_rpm_get(p);
1467 spin_lock_irqsave(&p->port.lock, flags);
1468 if (em485->active_timer == &em485->stop_tx_timer) {
1469 __do_stop_tx_rs485(p);
1470 em485->active_timer = NULL;
1472 spin_unlock_irqrestore(&p->port.lock, flags);
1473 serial8250_rpm_put(p);
1474 return HRTIMER_NORESTART;
1477 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1479 long sec = msec / 1000;
1480 long nsec = (msec % 1000) * 1000000;
1481 ktime_t t = ktime_set(sec, nsec);
1483 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1486 static void __stop_tx_rs485(struct uart_8250_port *p)
1488 struct uart_8250_em485 *em485 = p->em485;
1491 * __do_stop_tx_rs485 is going to set RTS according to config
1492 * AND flush RX FIFO if required.
1494 if (p->port.rs485.delay_rts_after_send > 0) {
1495 em485->active_timer = &em485->stop_tx_timer;
1496 start_hrtimer_ms(&em485->stop_tx_timer,
1497 p->port.rs485.delay_rts_after_send);
1499 __do_stop_tx_rs485(p);
1503 static inline void __do_stop_tx(struct uart_8250_port *p)
1505 if (serial8250_clear_THRI(p))
1506 serial8250_rpm_put_tx(p);
1509 static inline void __stop_tx(struct uart_8250_port *p)
1511 struct uart_8250_em485 *em485 = p->em485;
1514 unsigned char lsr = serial_in(p, UART_LSR);
1516 * To provide required timeing and allow FIFO transfer,
1517 * __stop_tx_rs485() must be called only when both FIFO and
1518 * shift register are empty. It is for device driver to enable
1519 * interrupt on TEMT.
1521 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1524 em485->active_timer = NULL;
1531 static void serial8250_stop_tx(struct uart_port *port)
1533 struct uart_8250_port *up = up_to_u8250p(port);
1535 serial8250_rpm_get(up);
1539 * We really want to stop the transmitter from sending.
1541 if (port->type == PORT_16C950) {
1542 up->acr |= UART_ACR_TXDIS;
1543 serial_icr_write(up, UART_ACR, up->acr);
1545 serial8250_rpm_put(up);
1548 static inline void __start_tx(struct uart_port *port)
1550 struct uart_8250_port *up = up_to_u8250p(port);
1552 if (up->dma && !up->dma->tx_dma(up))
1555 if (serial8250_set_THRI(up)) {
1556 if (up->bugs & UART_BUG_TXEN) {
1559 lsr = serial_in(up, UART_LSR);
1560 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1561 if (lsr & UART_LSR_THRE)
1562 serial8250_tx_chars(up);
1567 * Re-enable the transmitter if we disabled it.
1569 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1570 up->acr &= ~UART_ACR_TXDIS;
1571 serial_icr_write(up, UART_ACR, up->acr);
1575 static inline void start_tx_rs485(struct uart_port *port)
1577 struct uart_8250_port *up = up_to_u8250p(port);
1578 struct uart_8250_em485 *em485 = up->em485;
1581 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1582 serial8250_stop_rx(&up->port);
1584 em485->active_timer = NULL;
1586 mcr = serial8250_in_MCR(up);
1587 if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1588 !!(mcr & UART_MCR_RTS)) {
1589 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1590 mcr |= UART_MCR_RTS;
1592 mcr &= ~UART_MCR_RTS;
1593 serial8250_out_MCR(up, mcr);
1595 if (up->port.rs485.delay_rts_before_send > 0) {
1596 em485->active_timer = &em485->start_tx_timer;
1597 start_hrtimer_ms(&em485->start_tx_timer,
1598 up->port.rs485.delay_rts_before_send);
1606 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1608 struct uart_8250_em485 *em485;
1609 struct uart_8250_port *p;
1610 unsigned long flags;
1612 em485 = container_of(t, struct uart_8250_em485, start_tx_timer);
1615 spin_lock_irqsave(&p->port.lock, flags);
1616 if (em485->active_timer == &em485->start_tx_timer) {
1617 __start_tx(&p->port);
1618 em485->active_timer = NULL;
1620 spin_unlock_irqrestore(&p->port.lock, flags);
1621 return HRTIMER_NORESTART;
1624 static void serial8250_start_tx(struct uart_port *port)
1626 struct uart_8250_port *up = up_to_u8250p(port);
1627 struct uart_8250_em485 *em485 = up->em485;
1629 serial8250_rpm_get_tx(up);
1632 em485->active_timer == &em485->start_tx_timer)
1636 start_tx_rs485(port);
1641 static void serial8250_throttle(struct uart_port *port)
1643 port->throttle(port);
1646 static void serial8250_unthrottle(struct uart_port *port)
1648 port->unthrottle(port);
1651 static void serial8250_disable_ms(struct uart_port *port)
1653 struct uart_8250_port *up = up_to_u8250p(port);
1655 /* no MSR capabilities */
1656 if (up->bugs & UART_BUG_NOMSR)
1659 mctrl_gpio_disable_ms(up->gpios);
1661 up->ier &= ~UART_IER_MSI;
1662 serial_port_out(port, UART_IER, up->ier);
1665 static void serial8250_enable_ms(struct uart_port *port)
1667 struct uart_8250_port *up = up_to_u8250p(port);
1669 /* no MSR capabilities */
1670 if (up->bugs & UART_BUG_NOMSR)
1673 mctrl_gpio_enable_ms(up->gpios);
1675 up->ier |= UART_IER_MSI;
1677 serial8250_rpm_get(up);
1678 serial_port_out(port, UART_IER, up->ier);
1679 serial8250_rpm_put(up);
1682 void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1684 struct uart_port *port = &up->port;
1686 char flag = TTY_NORMAL;
1688 if (likely(lsr & UART_LSR_DR))
1689 ch = serial_in(up, UART_RX);
1692 * Intel 82571 has a Serial Over Lan device that will
1693 * set UART_LSR_BI without setting UART_LSR_DR when
1694 * it receives a break. To avoid reading from the
1695 * receive buffer without UART_LSR_DR bit set, we
1696 * just force the read character to be 0
1702 lsr |= up->lsr_saved_flags;
1703 up->lsr_saved_flags = 0;
1705 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1706 if (lsr & UART_LSR_BI) {
1707 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1710 * We do the SysRQ and SAK checking
1711 * here because otherwise the break
1712 * may get masked by ignore_status_mask
1713 * or read_status_mask.
1715 if (uart_handle_break(port))
1717 } else if (lsr & UART_LSR_PE)
1718 port->icount.parity++;
1719 else if (lsr & UART_LSR_FE)
1720 port->icount.frame++;
1721 if (lsr & UART_LSR_OE)
1722 port->icount.overrun++;
1725 * Mask off conditions which should be ignored.
1727 lsr &= port->read_status_mask;
1729 if (lsr & UART_LSR_BI) {
1730 pr_debug("%s: handling break\n", __func__);
1732 } else if (lsr & UART_LSR_PE)
1734 else if (lsr & UART_LSR_FE)
1737 if (uart_prepare_sysrq_char(port, ch))
1740 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1742 EXPORT_SYMBOL_GPL(serial8250_read_char);
1745 * serial8250_rx_chars: processes according to the passed in LSR
1746 * value, and returns the remaining LSR bits not handled
1747 * by this Rx routine.
1749 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1751 struct uart_port *port = &up->port;
1752 int max_count = 256;
1755 serial8250_read_char(up, lsr);
1756 if (--max_count == 0)
1758 lsr = serial_in(up, UART_LSR);
1759 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1761 tty_flip_buffer_push(&port->state->port);
1764 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1766 void serial8250_tx_chars(struct uart_8250_port *up)
1768 struct uart_port *port = &up->port;
1769 struct circ_buf *xmit = &port->state->xmit;
1773 serial_out(up, UART_TX, port->x_char);
1778 if (uart_tx_stopped(port)) {
1779 serial8250_stop_tx(port);
1782 if (uart_circ_empty(xmit)) {
1787 count = up->tx_loadsz;
1789 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1790 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1792 if (uart_circ_empty(xmit))
1794 if ((up->capabilities & UART_CAP_HFIFO) &&
1795 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1797 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1798 if ((up->capabilities & UART_CAP_MINI) &&
1799 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1801 } while (--count > 0);
1803 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1804 uart_write_wakeup(port);
1807 * With RPM enabled, we have to wait until the FIFO is empty before the
1808 * HW can go idle. So we get here once again with empty FIFO and disable
1809 * the interrupt and RPM in __stop_tx()
1811 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1814 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1816 /* Caller holds uart port lock */
1817 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1819 struct uart_port *port = &up->port;
1820 unsigned int status = serial_in(up, UART_MSR);
1822 status |= up->msr_saved_flags;
1823 up->msr_saved_flags = 0;
1824 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1825 port->state != NULL) {
1826 if (status & UART_MSR_TERI)
1828 if (status & UART_MSR_DDSR)
1830 if (status & UART_MSR_DDCD)
1831 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1832 if (status & UART_MSR_DCTS)
1833 uart_handle_cts_change(port, status & UART_MSR_CTS);
1835 wake_up_interruptible(&port->state->port.delta_msr_wait);
1840 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1842 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1844 switch (iir & 0x3f) {
1845 case UART_IIR_RX_TIMEOUT:
1846 serial8250_rx_dma_flush(up);
1851 return up->dma->rx_dma(up);
1855 * This handles the interrupt from one port.
1857 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1859 unsigned char status;
1860 unsigned long flags;
1861 struct uart_8250_port *up = up_to_u8250p(port);
1863 if (iir & UART_IIR_NO_INT)
1866 spin_lock_irqsave(&port->lock, flags);
1868 status = serial_port_in(port, UART_LSR);
1870 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1871 if (!up->dma || handle_rx_dma(up, iir))
1872 status = serial8250_rx_chars(up, status);
1874 serial8250_modem_status(up);
1875 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1876 (up->ier & UART_IER_THRI))
1877 serial8250_tx_chars(up);
1879 uart_unlock_and_check_sysrq(port, flags);
1882 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1884 static int serial8250_default_handle_irq(struct uart_port *port)
1886 struct uart_8250_port *up = up_to_u8250p(port);
1890 serial8250_rpm_get(up);
1892 iir = serial_port_in(port, UART_IIR);
1893 ret = serial8250_handle_irq(port, iir);
1895 serial8250_rpm_put(up);
1900 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1901 * have a programmable TX threshold that triggers the THRE interrupt in
1902 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1903 * has space available. Load it up with tx_loadsz bytes.
1905 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1907 unsigned long flags;
1908 unsigned int iir = serial_port_in(port, UART_IIR);
1910 /* TX Threshold IRQ triggered so load up FIFO */
1911 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1912 struct uart_8250_port *up = up_to_u8250p(port);
1914 spin_lock_irqsave(&port->lock, flags);
1915 serial8250_tx_chars(up);
1916 spin_unlock_irqrestore(&port->lock, flags);
1919 iir = serial_port_in(port, UART_IIR);
1920 return serial8250_handle_irq(port, iir);
1923 static unsigned int serial8250_tx_empty(struct uart_port *port)
1925 struct uart_8250_port *up = up_to_u8250p(port);
1926 unsigned long flags;
1929 serial8250_rpm_get(up);
1931 spin_lock_irqsave(&port->lock, flags);
1932 lsr = serial_port_in(port, UART_LSR);
1933 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1934 spin_unlock_irqrestore(&port->lock, flags);
1936 serial8250_rpm_put(up);
1938 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1941 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1943 struct uart_8250_port *up = up_to_u8250p(port);
1944 unsigned int status;
1947 serial8250_rpm_get(up);
1948 status = serial8250_modem_status(up);
1949 serial8250_rpm_put(up);
1951 val = serial8250_MSR_to_TIOCM(status);
1953 return mctrl_gpio_get(up->gpios, &val);
1957 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1959 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1961 if (port->get_mctrl)
1962 return port->get_mctrl(port);
1963 return serial8250_do_get_mctrl(port);
1966 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1968 struct uart_8250_port *up = up_to_u8250p(port);
1971 mcr = serial8250_TIOCM_to_MCR(mctrl);
1973 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1975 serial8250_out_MCR(up, mcr);
1977 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1979 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1981 if (port->set_mctrl)
1982 port->set_mctrl(port, mctrl);
1984 serial8250_do_set_mctrl(port, mctrl);
1987 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1989 struct uart_8250_port *up = up_to_u8250p(port);
1990 unsigned long flags;
1992 serial8250_rpm_get(up);
1993 spin_lock_irqsave(&port->lock, flags);
1994 if (break_state == -1)
1995 up->lcr |= UART_LCR_SBC;
1997 up->lcr &= ~UART_LCR_SBC;
1998 serial_port_out(port, UART_LCR, up->lcr);
1999 spin_unlock_irqrestore(&port->lock, flags);
2000 serial8250_rpm_put(up);
2004 * Wait for transmitter & holding register to empty
2006 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2008 unsigned int status, tmout = 10000;
2010 /* Wait up to 10ms for the character(s) to be sent. */
2012 status = serial_in(up, UART_LSR);
2014 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2016 if ((status & bits) == bits)
2021 touch_nmi_watchdog();
2024 /* Wait up to 1s for flow control if necessary */
2025 if (up->port.flags & UPF_CONS_FLOW) {
2026 for (tmout = 1000000; tmout; tmout--) {
2027 unsigned int msr = serial_in(up, UART_MSR);
2028 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2029 if (msr & UART_MSR_CTS)
2032 touch_nmi_watchdog();
2037 #ifdef CONFIG_CONSOLE_POLL
2039 * Console polling routines for writing and reading from the uart while
2040 * in an interrupt or debug context.
2043 static int serial8250_get_poll_char(struct uart_port *port)
2045 struct uart_8250_port *up = up_to_u8250p(port);
2049 serial8250_rpm_get(up);
2051 lsr = serial_port_in(port, UART_LSR);
2053 if (!(lsr & UART_LSR_DR)) {
2054 status = NO_POLL_CHAR;
2058 status = serial_port_in(port, UART_RX);
2060 serial8250_rpm_put(up);
2065 static void serial8250_put_poll_char(struct uart_port *port,
2069 struct uart_8250_port *up = up_to_u8250p(port);
2071 serial8250_rpm_get(up);
2073 * First save the IER then disable the interrupts
2075 ier = serial_port_in(port, UART_IER);
2076 if (up->capabilities & UART_CAP_UUE)
2077 serial_port_out(port, UART_IER, UART_IER_UUE);
2079 serial_port_out(port, UART_IER, 0);
2081 wait_for_xmitr(up, BOTH_EMPTY);
2083 * Send the character out.
2085 serial_port_out(port, UART_TX, c);
2088 * Finally, wait for transmitter to become empty
2089 * and restore the IER
2091 wait_for_xmitr(up, BOTH_EMPTY);
2092 serial_port_out(port, UART_IER, ier);
2093 serial8250_rpm_put(up);
2096 #endif /* CONFIG_CONSOLE_POLL */
2098 int serial8250_do_startup(struct uart_port *port)
2100 struct uart_8250_port *up = up_to_u8250p(port);
2101 unsigned long flags;
2102 unsigned char lsr, iir;
2105 if (!port->fifosize)
2106 port->fifosize = uart_config[port->type].fifo_size;
2108 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2109 if (!up->capabilities)
2110 up->capabilities = uart_config[port->type].flags;
2113 if (port->iotype != up->cur_iotype)
2114 set_io_from_upio(port);
2116 serial8250_rpm_get(up);
2117 if (port->type == PORT_16C950) {
2118 /* Wake up and initialize UART */
2120 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2121 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2122 serial_port_out(port, UART_IER, 0);
2123 serial_port_out(port, UART_LCR, 0);
2124 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2125 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2126 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2127 serial_port_out(port, UART_LCR, 0);
2130 if (port->type == PORT_DA830) {
2131 /* Reset the port */
2132 serial_port_out(port, UART_IER, 0);
2133 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2136 /* Enable Tx, Rx and free run mode */
2137 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2138 UART_DA830_PWREMU_MGMT_UTRST |
2139 UART_DA830_PWREMU_MGMT_URRST |
2140 UART_DA830_PWREMU_MGMT_FREE);
2143 if (port->type == PORT_NPCM) {
2145 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2146 * register). Enable it, and set TIOC (timeout interrupt
2147 * comparator) to be 0x20 for correct operation.
2149 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2152 #ifdef CONFIG_SERIAL_8250_RSA
2154 * If this is an RSA port, see if we can kick it up to the
2155 * higher speed clock.
2160 if (port->type == PORT_XR17V35X) {
2162 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2163 * MCR [7:5] and MSR [7:0]
2165 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2168 * Make sure all interrups are masked until initialization is
2169 * complete and the FIFOs are cleared
2171 serial_port_out(port, UART_IER, 0);
2175 * Clear the FIFO buffers and disable them.
2176 * (they will be reenabled in set_termios())
2178 serial8250_clear_fifos(up);
2181 * Clear the interrupt registers.
2183 serial_port_in(port, UART_LSR);
2184 serial_port_in(port, UART_RX);
2185 serial_port_in(port, UART_IIR);
2186 serial_port_in(port, UART_MSR);
2187 if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X))
2188 serial_port_in(port, UART_EXAR_INT0);
2191 * At this point, there's no way the LSR could still be 0xff;
2192 * if it is, then bail out, because there's likely no UART
2195 if (!(port->flags & UPF_BUGGY_UART) &&
2196 (serial_port_in(port, UART_LSR) == 0xff)) {
2197 pr_info_ratelimited("%s: LSR safety check engaged!\n", port->name);
2203 * For a XR16C850, we need to set the trigger levels
2205 if (port->type == PORT_16850) {
2208 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2210 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2211 serial_port_out(port, UART_FCTR,
2212 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2213 serial_port_out(port, UART_TRG, UART_TRG_96);
2214 serial_port_out(port, UART_FCTR,
2215 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2216 serial_port_out(port, UART_TRG, UART_TRG_96);
2218 serial_port_out(port, UART_LCR, 0);
2222 * For the Altera 16550 variants, set TX threshold trigger level.
2224 if (((port->type == PORT_ALTR_16550_F32) ||
2225 (port->type == PORT_ALTR_16550_F64) ||
2226 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2227 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2228 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2229 pr_err("%s TX FIFO Threshold errors, skipping\n",
2232 serial_port_out(port, UART_ALTR_AFR,
2233 UART_ALTR_EN_TXFIFO_LW);
2234 serial_port_out(port, UART_ALTR_TX_LOW,
2235 port->fifosize - up->tx_loadsz);
2236 port->handle_irq = serial8250_tx_threshold_handle_irq;
2240 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2243 * Test for UARTs that do not reassert THRE when the
2244 * transmitter is idle and the interrupt has already
2245 * been cleared. Real 16550s should always reassert
2246 * this interrupt whenever the transmitter is idle and
2247 * the interrupt is enabled. Delays are necessary to
2248 * allow register changes to become visible.
2250 spin_lock_irqsave(&port->lock, flags);
2251 if (up->port.irqflags & IRQF_SHARED)
2252 disable_irq_nosync(port->irq);
2254 wait_for_xmitr(up, UART_LSR_THRE);
2255 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2256 udelay(1); /* allow THRE to set */
2257 iir1 = serial_port_in(port, UART_IIR);
2258 serial_port_out(port, UART_IER, 0);
2259 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2260 udelay(1); /* allow a working UART time to re-assert THRE */
2261 iir = serial_port_in(port, UART_IIR);
2262 serial_port_out(port, UART_IER, 0);
2264 if (port->irqflags & IRQF_SHARED)
2265 enable_irq(port->irq);
2266 spin_unlock_irqrestore(&port->lock, flags);
2269 * If the interrupt is not reasserted, or we otherwise
2270 * don't trust the iir, setup a timer to kick the UART
2271 * on a regular basis.
2273 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2274 up->port.flags & UPF_BUG_THRE) {
2275 up->bugs |= UART_BUG_THRE;
2279 retval = up->ops->setup_irq(up);
2284 * Now, initialize the UART
2286 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2288 spin_lock_irqsave(&port->lock, flags);
2289 if (up->port.flags & UPF_FOURPORT) {
2291 up->port.mctrl |= TIOCM_OUT1;
2294 * Most PC uarts need OUT2 raised to enable interrupts.
2297 up->port.mctrl |= TIOCM_OUT2;
2299 serial8250_set_mctrl(port, port->mctrl);
2302 * Serial over Lan (SoL) hack:
2303 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2304 * used for Serial Over Lan. Those chips take a longer time than a
2305 * normal serial device to signalize that a transmission data was
2306 * queued. Due to that, the above test generally fails. One solution
2307 * would be to delay the reading of iir. However, this is not
2308 * reliable, since the timeout is variable. So, let's just don't
2309 * test if we receive TX irq. This way, we'll never enable
2312 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2313 goto dont_test_tx_en;
2316 * Do a quick test to see if we receive an interrupt when we enable
2319 serial_port_out(port, UART_IER, UART_IER_THRI);
2320 lsr = serial_port_in(port, UART_LSR);
2321 iir = serial_port_in(port, UART_IIR);
2322 serial_port_out(port, UART_IER, 0);
2324 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2325 if (!(up->bugs & UART_BUG_TXEN)) {
2326 up->bugs |= UART_BUG_TXEN;
2327 pr_debug("%s - enabling bad tx status workarounds\n",
2331 up->bugs &= ~UART_BUG_TXEN;
2335 spin_unlock_irqrestore(&port->lock, flags);
2338 * Clear the interrupt registers again for luck, and clear the
2339 * saved flags to avoid getting false values from polling
2340 * routines or the previous session.
2342 serial_port_in(port, UART_LSR);
2343 serial_port_in(port, UART_RX);
2344 serial_port_in(port, UART_IIR);
2345 serial_port_in(port, UART_MSR);
2346 if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X))
2347 serial_port_in(port, UART_EXAR_INT0);
2348 up->lsr_saved_flags = 0;
2349 up->msr_saved_flags = 0;
2352 * Request DMA channels for both RX and TX.
2355 retval = serial8250_request_dma(up);
2357 pr_warn_ratelimited("%s - failed to request DMA\n",
2364 * Set the IER shadow for rx interrupts but defer actual interrupt
2365 * enable until after the FIFOs are enabled; otherwise, an already-
2366 * active sender can swamp the interrupt handler with "too much work".
2368 up->ier = UART_IER_RLSI | UART_IER_RDI;
2370 if (port->flags & UPF_FOURPORT) {
2373 * Enable interrupts on the AST Fourport board
2375 icp = (port->iobase & 0xfe0) | 0x01f;
2381 serial8250_rpm_put(up);
2384 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2386 static int serial8250_startup(struct uart_port *port)
2389 return port->startup(port);
2390 return serial8250_do_startup(port);
2393 void serial8250_do_shutdown(struct uart_port *port)
2395 struct uart_8250_port *up = up_to_u8250p(port);
2396 unsigned long flags;
2398 serial8250_rpm_get(up);
2400 * Disable interrupts from this port
2402 spin_lock_irqsave(&port->lock, flags);
2404 serial_port_out(port, UART_IER, 0);
2405 spin_unlock_irqrestore(&port->lock, flags);
2407 synchronize_irq(port->irq);
2410 serial8250_release_dma(up);
2412 spin_lock_irqsave(&port->lock, flags);
2413 if (port->flags & UPF_FOURPORT) {
2414 /* reset interrupts on the AST Fourport board */
2415 inb((port->iobase & 0xfe0) | 0x1f);
2416 port->mctrl |= TIOCM_OUT1;
2418 port->mctrl &= ~TIOCM_OUT2;
2420 serial8250_set_mctrl(port, port->mctrl);
2421 spin_unlock_irqrestore(&port->lock, flags);
2424 * Disable break condition and FIFOs
2426 serial_port_out(port, UART_LCR,
2427 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2428 serial8250_clear_fifos(up);
2430 #ifdef CONFIG_SERIAL_8250_RSA
2432 * Reset the RSA board back to 115kbps compat mode.
2438 * Read data port to reset things, and then unlink from
2441 serial_port_in(port, UART_RX);
2442 serial8250_rpm_put(up);
2444 up->ops->release_irq(up);
2446 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2448 static void serial8250_shutdown(struct uart_port *port)
2451 port->shutdown(port);
2453 serial8250_do_shutdown(port);
2457 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2458 * Calculate divisor with extra 4-bit fractional portion
2460 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2464 struct uart_port *port = &up->port;
2465 unsigned int quot_16;
2467 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2468 *frac = quot_16 & 0x0f;
2470 return quot_16 >> 4;
2473 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2474 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2477 struct uart_port *port = &up->port;
2479 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2482 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2486 struct uart_8250_port *up = up_to_u8250p(port);
2490 * Handle magic divisors for baud rates above baud_base on
2491 * SMSC SuperIO chips.
2494 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2495 baud == (port->uartclk/4))
2497 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2498 baud == (port->uartclk/8))
2500 else if (up->port.type == PORT_XR17V35X)
2501 quot = xr17v35x_get_divisor(up, baud, frac);
2502 else if (up->port.type == PORT_NPCM)
2503 quot = npcm_get_divisor(up, baud);
2505 quot = uart_get_divisor(port, baud);
2508 * Oxford Semi 952 rev B workaround
2510 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2516 static unsigned int serial8250_get_divisor(struct uart_port *port,
2520 if (port->get_divisor)
2521 return port->get_divisor(port, baud, frac);
2523 return serial8250_do_get_divisor(port, baud, frac);
2526 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2531 switch (c_cflag & CSIZE) {
2533 cval = UART_LCR_WLEN5;
2536 cval = UART_LCR_WLEN6;
2539 cval = UART_LCR_WLEN7;
2543 cval = UART_LCR_WLEN8;
2547 if (c_cflag & CSTOPB)
2548 cval |= UART_LCR_STOP;
2549 if (c_cflag & PARENB) {
2550 cval |= UART_LCR_PARITY;
2551 if (up->bugs & UART_BUG_PARITY)
2552 up->fifo_bug = true;
2554 if (!(c_cflag & PARODD))
2555 cval |= UART_LCR_EPAR;
2557 if (c_cflag & CMSPAR)
2558 cval |= UART_LCR_SPAR;
2564 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2565 unsigned int quot, unsigned int quot_frac)
2567 struct uart_8250_port *up = up_to_u8250p(port);
2569 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2570 if (is_omap1510_8250(up)) {
2571 if (baud == 115200) {
2573 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2575 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2579 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2580 * otherwise just set DLAB
2582 if (up->capabilities & UART_NATSEMI)
2583 serial_port_out(port, UART_LCR, 0xe0);
2585 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2587 serial_dl_write(up, quot);
2589 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2590 if (up->port.type == PORT_XR17V35X) {
2591 /* Preserve bits not related to baudrate; DLD[7:4]. */
2592 quot_frac |= serial_port_in(port, 0x2) & 0xf0;
2593 serial_port_out(port, 0x2, quot_frac);
2596 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2598 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2599 unsigned int quot, unsigned int quot_frac)
2601 if (port->set_divisor)
2602 port->set_divisor(port, baud, quot, quot_frac);
2604 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2607 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2608 struct ktermios *termios,
2609 struct ktermios *old)
2612 * Ask the core to calculate the divisor for us.
2613 * Allow 1% tolerance at the upper limit so uart clks marginally
2614 * slower than nominal still match standard baud rates without
2615 * causing transmission errors.
2617 return uart_get_baud_rate(port, termios, old,
2618 port->uartclk / 16 / UART_DIV_MAX,
2623 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2624 struct ktermios *old)
2626 struct uart_8250_port *up = up_to_u8250p(port);
2628 unsigned long flags;
2629 unsigned int baud, quot, frac = 0;
2631 if (up->capabilities & UART_CAP_MINI) {
2632 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2633 if ((termios->c_cflag & CSIZE) == CS5 ||
2634 (termios->c_cflag & CSIZE) == CS6)
2635 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2637 cval = serial8250_compute_lcr(up, termios->c_cflag);
2639 baud = serial8250_get_baud_rate(port, termios, old);
2640 quot = serial8250_get_divisor(port, baud, &frac);
2643 * Ok, we're now changing the port state. Do it with
2644 * interrupts disabled.
2646 serial8250_rpm_get(up);
2647 spin_lock_irqsave(&port->lock, flags);
2649 up->lcr = cval; /* Save computed LCR */
2651 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2652 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2653 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2654 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2655 up->fcr |= UART_FCR_TRIGGER_1;
2660 * MCR-based auto flow control. When AFE is enabled, RTS will be
2661 * deasserted when the receive FIFO contains more characters than
2662 * the trigger, or the MCR RTS bit is cleared.
2664 if (up->capabilities & UART_CAP_AFE) {
2665 up->mcr &= ~UART_MCR_AFE;
2666 if (termios->c_cflag & CRTSCTS)
2667 up->mcr |= UART_MCR_AFE;
2671 * Update the per-port timeout.
2673 uart_update_timeout(port, termios->c_cflag, baud);
2675 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2676 if (termios->c_iflag & INPCK)
2677 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2678 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2679 port->read_status_mask |= UART_LSR_BI;
2682 * Characteres to ignore
2684 port->ignore_status_mask = 0;
2685 if (termios->c_iflag & IGNPAR)
2686 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2687 if (termios->c_iflag & IGNBRK) {
2688 port->ignore_status_mask |= UART_LSR_BI;
2690 * If we're ignoring parity and break indicators,
2691 * ignore overruns too (for real raw support).
2693 if (termios->c_iflag & IGNPAR)
2694 port->ignore_status_mask |= UART_LSR_OE;
2698 * ignore all characters if CREAD is not set
2700 if ((termios->c_cflag & CREAD) == 0)
2701 port->ignore_status_mask |= UART_LSR_DR;
2704 * CTS flow control flag and modem status interrupts
2706 up->ier &= ~UART_IER_MSI;
2707 if (!(up->bugs & UART_BUG_NOMSR) &&
2708 UART_ENABLE_MS(&up->port, termios->c_cflag))
2709 up->ier |= UART_IER_MSI;
2710 if (up->capabilities & UART_CAP_UUE)
2711 up->ier |= UART_IER_UUE;
2712 if (up->capabilities & UART_CAP_RTOIE)
2713 up->ier |= UART_IER_RTOIE;
2715 serial_port_out(port, UART_IER, up->ier);
2717 if (up->capabilities & UART_CAP_EFR) {
2718 unsigned char efr = 0;
2720 * TI16C752/Startech hardware flow control. FIXME:
2721 * - TI16C752 requires control thresholds to be set.
2722 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2724 if (termios->c_cflag & CRTSCTS)
2725 efr |= UART_EFR_CTS;
2727 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2728 if (port->flags & UPF_EXAR_EFR)
2729 serial_port_out(port, UART_XR_EFR, efr);
2731 serial_port_out(port, UART_EFR, efr);
2734 serial8250_set_divisor(port, baud, quot, frac);
2737 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2738 * is written without DLAB set, this mode will be disabled.
2740 if (port->type == PORT_16750)
2741 serial_port_out(port, UART_FCR, up->fcr);
2743 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2744 if (port->type != PORT_16750) {
2745 /* emulated UARTs (Lucent Venus 167x) need two steps */
2746 if (up->fcr & UART_FCR_ENABLE_FIFO)
2747 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2748 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2750 serial8250_set_mctrl(port, port->mctrl);
2751 spin_unlock_irqrestore(&port->lock, flags);
2752 serial8250_rpm_put(up);
2754 /* Don't rewrite B0 */
2755 if (tty_termios_baud_rate(termios))
2756 tty_termios_encode_baud_rate(termios, baud, baud);
2758 EXPORT_SYMBOL(serial8250_do_set_termios);
2761 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2762 struct ktermios *old)
2764 if (port->set_termios)
2765 port->set_termios(port, termios, old);
2767 serial8250_do_set_termios(port, termios, old);
2770 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2772 if (termios->c_line == N_PPS) {
2773 port->flags |= UPF_HARDPPS_CD;
2774 spin_lock_irq(&port->lock);
2775 serial8250_enable_ms(port);
2776 spin_unlock_irq(&port->lock);
2778 port->flags &= ~UPF_HARDPPS_CD;
2779 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2780 spin_lock_irq(&port->lock);
2781 serial8250_disable_ms(port);
2782 spin_unlock_irq(&port->lock);
2786 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2789 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2791 if (port->set_ldisc)
2792 port->set_ldisc(port, termios);
2794 serial8250_do_set_ldisc(port, termios);
2797 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2798 unsigned int oldstate)
2800 struct uart_8250_port *p = up_to_u8250p(port);
2802 serial8250_set_sleep(p, state != 0);
2804 EXPORT_SYMBOL(serial8250_do_pm);
2807 serial8250_pm(struct uart_port *port, unsigned int state,
2808 unsigned int oldstate)
2811 port->pm(port, state, oldstate);
2813 serial8250_do_pm(port, state, oldstate);
2816 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2818 if (pt->port.mapsize)
2819 return pt->port.mapsize;
2820 if (pt->port.iotype == UPIO_AU) {
2821 if (pt->port.type == PORT_RT2880)
2825 if (is_omap1_8250(pt))
2826 return 0x16 << pt->port.regshift;
2828 return 8 << pt->port.regshift;
2832 * Resource handling.
2834 static int serial8250_request_std_resource(struct uart_8250_port *up)
2836 unsigned int size = serial8250_port_size(up);
2837 struct uart_port *port = &up->port;
2840 switch (port->iotype) {
2850 if (!request_mem_region(port->mapbase, size, "serial")) {
2855 if (port->flags & UPF_IOREMAP) {
2856 port->membase = ioremap_nocache(port->mapbase, size);
2857 if (!port->membase) {
2858 release_mem_region(port->mapbase, size);
2866 if (!request_region(port->iobase, size, "serial"))
2873 static void serial8250_release_std_resource(struct uart_8250_port *up)
2875 unsigned int size = serial8250_port_size(up);
2876 struct uart_port *port = &up->port;
2878 switch (port->iotype) {
2888 if (port->flags & UPF_IOREMAP) {
2889 iounmap(port->membase);
2890 port->membase = NULL;
2893 release_mem_region(port->mapbase, size);
2898 release_region(port->iobase, size);
2903 static void serial8250_release_port(struct uart_port *port)
2905 struct uart_8250_port *up = up_to_u8250p(port);
2907 serial8250_release_std_resource(up);
2910 static int serial8250_request_port(struct uart_port *port)
2912 struct uart_8250_port *up = up_to_u8250p(port);
2914 return serial8250_request_std_resource(up);
2917 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2919 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2920 unsigned char bytes;
2922 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2924 return bytes ? bytes : -EOPNOTSUPP;
2927 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2929 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2932 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2935 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2936 if (bytes < conf_type->rxtrig_bytes[i])
2937 /* Use the nearest lower value */
2938 return (--i) << UART_FCR_R_TRIG_SHIFT;
2941 return UART_FCR_R_TRIG_11;
2944 static int do_get_rxtrig(struct tty_port *port)
2946 struct uart_state *state = container_of(port, struct uart_state, port);
2947 struct uart_port *uport = state->uart_port;
2948 struct uart_8250_port *up = up_to_u8250p(uport);
2950 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2953 return fcr_get_rxtrig_bytes(up);
2956 static int do_serial8250_get_rxtrig(struct tty_port *port)
2960 mutex_lock(&port->mutex);
2961 rxtrig_bytes = do_get_rxtrig(port);
2962 mutex_unlock(&port->mutex);
2964 return rxtrig_bytes;
2967 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2968 struct device_attribute *attr, char *buf)
2970 struct tty_port *port = dev_get_drvdata(dev);
2973 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2974 if (rxtrig_bytes < 0)
2975 return rxtrig_bytes;
2977 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2980 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2982 struct uart_state *state = container_of(port, struct uart_state, port);
2983 struct uart_port *uport = state->uart_port;
2984 struct uart_8250_port *up = up_to_u8250p(uport);
2987 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2991 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2995 serial8250_clear_fifos(up);
2996 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2997 up->fcr |= (unsigned char)rxtrig;
2998 serial_out(up, UART_FCR, up->fcr);
3002 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3006 mutex_lock(&port->mutex);
3007 ret = do_set_rxtrig(port, bytes);
3008 mutex_unlock(&port->mutex);
3013 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
3014 struct device_attribute *attr, const char *buf, size_t count)
3016 struct tty_port *port = dev_get_drvdata(dev);
3017 unsigned char bytes;
3023 ret = kstrtou8(buf, 10, &bytes);
3027 ret = do_serial8250_set_rxtrig(port, bytes);
3034 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
3035 serial8250_get_attr_rx_trig_bytes,
3036 serial8250_set_attr_rx_trig_bytes);
3038 static struct attribute *serial8250_dev_attrs[] = {
3039 &dev_attr_rx_trig_bytes.attr,
3043 static struct attribute_group serial8250_dev_attr_group = {
3044 .attrs = serial8250_dev_attrs,
3047 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3049 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3051 if (conf_type->rxtrig_bytes[0])
3052 up->port.attr_group = &serial8250_dev_attr_group;
3055 static void serial8250_config_port(struct uart_port *port, int flags)
3057 struct uart_8250_port *up = up_to_u8250p(port);
3061 * Find the region that we can probe for. This in turn
3062 * tells us whether we can probe for the type of port.
3064 ret = serial8250_request_std_resource(up);
3068 if (port->iotype != up->cur_iotype)
3069 set_io_from_upio(port);
3071 if (flags & UART_CONFIG_TYPE)
3074 /* if access method is AU, it is a 16550 with a quirk */
3075 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3076 up->bugs |= UART_BUG_NOMSR;
3078 /* HW bugs may trigger IRQ while IIR == NO_INT */
3079 if (port->type == PORT_TEGRA)
3080 up->bugs |= UART_BUG_NOMSR;
3082 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3085 if (port->type == PORT_UNKNOWN)
3086 serial8250_release_std_resource(up);
3088 register_dev_spec_attr_grp(up);
3089 up->fcr = uart_config[up->port.type].fcr;
3093 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3095 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3096 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3097 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3098 ser->type == PORT_STARTECH)
3103 static const char *serial8250_type(struct uart_port *port)
3105 int type = port->type;
3107 if (type >= ARRAY_SIZE(uart_config))
3109 return uart_config[type].name;
3112 static const struct uart_ops serial8250_pops = {
3113 .tx_empty = serial8250_tx_empty,
3114 .set_mctrl = serial8250_set_mctrl,
3115 .get_mctrl = serial8250_get_mctrl,
3116 .stop_tx = serial8250_stop_tx,
3117 .start_tx = serial8250_start_tx,
3118 .throttle = serial8250_throttle,
3119 .unthrottle = serial8250_unthrottle,
3120 .stop_rx = serial8250_stop_rx,
3121 .enable_ms = serial8250_enable_ms,
3122 .break_ctl = serial8250_break_ctl,
3123 .startup = serial8250_startup,
3124 .shutdown = serial8250_shutdown,
3125 .set_termios = serial8250_set_termios,
3126 .set_ldisc = serial8250_set_ldisc,
3127 .pm = serial8250_pm,
3128 .type = serial8250_type,
3129 .release_port = serial8250_release_port,
3130 .request_port = serial8250_request_port,
3131 .config_port = serial8250_config_port,
3132 .verify_port = serial8250_verify_port,
3133 #ifdef CONFIG_CONSOLE_POLL
3134 .poll_get_char = serial8250_get_poll_char,
3135 .poll_put_char = serial8250_put_poll_char,
3139 void serial8250_init_port(struct uart_8250_port *up)
3141 struct uart_port *port = &up->port;
3143 spin_lock_init(&port->lock);
3144 port->ops = &serial8250_pops;
3146 up->cur_iotype = 0xFF;
3148 EXPORT_SYMBOL_GPL(serial8250_init_port);
3150 void serial8250_set_defaults(struct uart_8250_port *up)
3152 struct uart_port *port = &up->port;
3154 if (up->port.flags & UPF_FIXED_TYPE) {
3155 unsigned int type = up->port.type;
3157 if (!up->port.fifosize)
3158 up->port.fifosize = uart_config[type].fifo_size;
3160 up->tx_loadsz = uart_config[type].tx_loadsz;
3161 if (!up->capabilities)
3162 up->capabilities = uart_config[type].flags;
3165 set_io_from_upio(port);
3167 /* default dma handlers */
3169 if (!up->dma->tx_dma)
3170 up->dma->tx_dma = serial8250_tx_dma;
3171 if (!up->dma->rx_dma)
3172 up->dma->rx_dma = serial8250_rx_dma;
3175 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3177 #ifdef CONFIG_SERIAL_8250_CONSOLE
3179 static void serial8250_console_putchar(struct uart_port *port, int ch)
3181 struct uart_8250_port *up = up_to_u8250p(port);
3183 wait_for_xmitr(up, UART_LSR_THRE);
3184 serial_port_out(port, UART_TX, ch);
3188 * Restore serial console when h/w power-off detected
3190 static void serial8250_console_restore(struct uart_8250_port *up)
3192 struct uart_port *port = &up->port;
3193 struct ktermios termios;
3194 unsigned int baud, quot, frac = 0;
3196 termios.c_cflag = port->cons->cflag;
3197 if (port->state->port.tty && termios.c_cflag == 0)
3198 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3200 baud = serial8250_get_baud_rate(port, &termios, NULL);
3201 quot = serial8250_get_divisor(port, baud, &frac);
3203 serial8250_set_divisor(port, baud, quot, frac);
3204 serial_port_out(port, UART_LCR, up->lcr);
3205 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3209 * Print a string to the serial port trying not to disturb
3210 * any possible real use of the port...
3212 * The console_lock must be held when we get here.
3214 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3217 struct uart_port *port = &up->port;
3218 unsigned long flags;
3222 touch_nmi_watchdog();
3224 serial8250_rpm_get(up);
3226 if (oops_in_progress)
3227 locked = spin_trylock_irqsave(&port->lock, flags);
3229 spin_lock_irqsave(&port->lock, flags);
3232 * First save the IER then disable the interrupts
3234 ier = serial_port_in(port, UART_IER);
3236 if (up->capabilities & UART_CAP_UUE)
3237 serial_port_out(port, UART_IER, UART_IER_UUE);
3239 serial_port_out(port, UART_IER, 0);
3241 /* check scratch reg to see if port powered off during system sleep */
3242 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3243 serial8250_console_restore(up);
3247 uart_console_write(port, s, count, serial8250_console_putchar);
3250 * Finally, wait for transmitter to become empty
3251 * and restore the IER
3253 wait_for_xmitr(up, BOTH_EMPTY);
3254 serial_port_out(port, UART_IER, ier);
3257 * The receive handling will happen properly because the
3258 * receive ready bit will still be set; it is not cleared
3259 * on read. However, modem control will not, we must
3260 * call it if we have saved something in the saved flags
3261 * while processing with interrupts off.
3263 if (up->msr_saved_flags)
3264 serial8250_modem_status(up);
3267 spin_unlock_irqrestore(&port->lock, flags);
3268 serial8250_rpm_put(up);
3271 static unsigned int probe_baud(struct uart_port *port)
3273 unsigned char lcr, dll, dlm;
3276 lcr = serial_port_in(port, UART_LCR);
3277 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3278 dll = serial_port_in(port, UART_DLL);
3279 dlm = serial_port_in(port, UART_DLM);
3280 serial_port_out(port, UART_LCR, lcr);
3282 quot = (dlm << 8) | dll;
3283 return (port->uartclk / 16) / quot;
3286 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3293 if (!port->iobase && !port->membase)
3297 uart_parse_options(options, &baud, &parity, &bits, &flow);
3299 baud = probe_baud(port);
3301 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3304 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3306 MODULE_LICENSE("GPL");