2 * (C) Copyright 2004 Tundra Semiconductor Corp.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #ifdef CONFIG_TSI108_I2C
31 #if (CONFIG_COMMANDS & CFG_CMD_I2C)
33 #define I2C_DELAY 100000
37 #define DPRINT(x) printf (x)
42 /* All functions assume that Tsi108 I2C block is the only master on the bus */
43 /* I2C read helper function */
45 static int i2c_read_byte (
46 uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */
47 uchar chip_addr,/* I2C device address on the bus */
48 uint byte_addr, /* Byte address within I2C device */
49 uchar * buffer /* pointer to data buffer */
53 u32 to_count = I2C_DELAY;
54 u32 op_status = TSI108_I2C_TIMEOUT_ERR;
55 u32 chan_offset = TSI108_I2C_OFFSET;
57 DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n",
58 i2c_chan, chip_addr, byte_addr));
61 chan_offset = TSI108_I2C_SDRAM_OFFSET;
63 /* Check if I2C operation is in progress */
64 temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
66 if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS |
68 /* Set device address and operation (read = 0) */
69 temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) |
70 ((chip_addr >> 3) & 0x0F);
71 *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL1) =
74 /* Issue the read command
75 * (at this moment all other parameters are 0
76 * (size = 1 byte, lane = 0)
79 *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2) =
82 /* Wait until operation completed */
84 /* Read I2C operation status */
86 *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset +
90 (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START)))
94 (I2C_CNTRL2_I2C_CFGERR |
95 I2C_CNTRL2_I2C_TO_ERR))
97 op_status = TSI108_I2C_SUCCESS;
99 temp = *(u32 *) (CFG_TSI108_CSR_BASE +
103 *buffer = (u8) (temp & 0xFF);
105 /* report HW error */
106 op_status = TSI108_I2C_IF_ERROR;
108 DPRINT (("I2C HW error reported: 0x%02x\n", temp));
113 } while (to_count--);
115 op_status = TSI108_I2C_IF_BUSY;
117 DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
120 DPRINT (("I2C read_byte() status: 0x%02x\n", op_status));
125 * I2C Read interface as defined in "include/i2c.h" :
126 * chip_addr: I2C chip address, range 0..127
127 * (to read from SPD channel EEPROM use (0xD0 ... 0xD7)
128 * NOTE: The bit 7 in the chip_addr serves as a channel select.
129 * This hack is for enabling "isdram" command on Tsi108 boards
130 * without changes to common code. Used for I2C reads only.
131 * byte_addr: Memory or register address within the chip
132 * alen: Number of bytes to use for addr (typically 1, 2 for larger
133 * memories, 0 for register type devices with only one
135 * buffer: Pointer to destination buffer for data to be read
136 * len: How many bytes to read
138 * Returns: 0 on success, not 0 on failure
141 int i2c_read (uchar chip_addr, uint byte_addr, int alen,
142 uchar * buffer, int len)
144 u32 op_status = TSI108_I2C_PARAM_ERR;
147 /* Hack to support second (SPD) I2C controller (SPD EEPROM read only).*/
148 if (0xD0 == (chip_addr & ~0x07)) {
152 /* Check for valid I2C address */
153 if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
156 i2c_read_byte(i2c_if, chip_addr, byte_addr++,
159 if (TSI108_I2C_SUCCESS != op_status) {
160 DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
167 DPRINT (("I2C read() status: 0x%02x\n", op_status));
171 /* I2C write helper function */
173 static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */
174 uint byte_addr, /* Byte address within I2C device */
175 uchar * buffer /* pointer to data buffer */
179 u32 to_count = I2C_DELAY;
180 u32 op_status = TSI108_I2C_TIMEOUT_ERR;
182 /* Check if I2C operation is in progress */
183 temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
187 (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START)))
189 /* Place data into the I2C Tx Register */
190 *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
191 I2C_TX_DATA) = (u32) * buffer;
193 /* Set device address and operation */
195 I2C_CNTRL1_I2CWRITE | (byte_addr << 16) |
196 ((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F);
197 *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
200 /* Issue the write command (at this moment all other parameters
201 * are 0 (size = 1 byte, lane = 0)
204 *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
205 I2C_CNTRL2) = (I2C_CNTRL2_START);
207 op_status = TSI108_I2C_TIMEOUT_ERR;
209 /* Wait until operation completed */
211 /* Read I2C operation status */
213 *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
217 (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START)))
221 (I2C_CNTRL2_I2C_CFGERR |
222 I2C_CNTRL2_I2C_TO_ERR))) {
223 op_status = TSI108_I2C_SUCCESS;
225 /* report detected HW error */
226 op_status = TSI108_I2C_IF_ERROR;
228 DPRINT (("I2C HW error reported: 0x%02x\n", temp));
234 } while (to_count--);
236 op_status = TSI108_I2C_IF_BUSY;
238 DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
245 * I2C Write interface as defined in "include/i2c.h" :
246 * chip_addr: I2C chip address, range 0..127
247 * byte_addr: Memory or register address within the chip
248 * alen: Number of bytes to use for addr (typically 1, 2 for larger
249 * memories, 0 for register type devices with only one
251 * buffer: Pointer to data to be written
252 * len: How many bytes to write
254 * Returns: 0 on success, not 0 on failure
257 int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer,
260 u32 op_status = TSI108_I2C_PARAM_ERR;
262 /* Check for valid I2C address */
263 if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
266 i2c_write_byte (chip_addr, byte_addr++, buffer++);
268 if (TSI108_I2C_SUCCESS != op_status) {
269 DPRINT (("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len));
280 * I2C interface function as defined in "include/i2c.h".
281 * Probe the given I2C chip address by reading single byte from offset 0.
282 * Returns 0 if a chip responded, not 0 on failure.
285 int i2c_probe (uchar chip)
290 * Try to read the first location of the chip.
291 * The Tsi108 HW doesn't support sending just the chip address
292 * and checkong for an <ACK> back.
294 return i2c_read (chip, 0, 1, (char *)&tmp, 1);
297 #endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */
298 #endif /* CONFIG_TSI108_I2C */