2 * Freescale Three Speed Ethernet Controller driver
4 * This software may be used and distributed according to the
5 * terms of the GNU Public License, Version 2, incorporated
8 * Copyright 2004, 2007 Freescale Semiconductor, Inc.
9 * (C) Copyright 2003, Motorola, Inc.
20 #if defined(CONFIG_TSEC_ENET)
24 DECLARE_GLOBAL_DATA_PTR;
28 static uint rxIdx; /* index of the current RX buffer */
29 static uint txIdx; /* index of the current TX buffer */
31 typedef volatile struct rtxbd {
32 txbd8_t txbd[TX_BUF_CNT];
33 rxbd8_t rxbd[PKTBUFSRX];
36 struct tsec_info_struct {
39 unsigned int phyregidx;
42 /* The tsec_info structure contains 3 values which the
43 * driver uses to determine how to operate a given ethernet
44 * device. The information needed is:
45 * phyaddr - The address of the PHY which is attached to
48 * flags - This variable indicates whether the device
49 * supports gigabit speed ethernet, and whether it should be
52 * phyregidx - This variable specifies which ethernet device
53 * controls the MII Management registers which are connected
54 * to the PHY. For now, only TSEC1 (index 0) has
55 * access to the PHYs, so all of the entries have "0".
57 * The values specified in the table are taken from the board's
58 * config file in include/configs/. When implementing a new
59 * board with ethernet capability, it is necessary to define:
63 * for n = 1,2,3, etc. And for FEC:
67 static struct tsec_info_struct tsec_info[] = {
68 #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
69 #if defined(CONFIG_MPC8544DS)
70 {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
72 {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
74 #elif defined(CONFIG_MPC86XX_TSEC1)
75 {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
79 #if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
80 {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
81 #elif defined(CONFIG_MPC86XX_TSEC2)
82 {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
86 #ifdef CONFIG_MPC85XX_FEC
87 {FEC_PHY_ADDR, 0, FEC_PHYIDX},
89 #if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3)
90 {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
94 #if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
95 {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
102 #define MAXCONTROLLERS (4)
104 static int relocated = 0;
106 static struct tsec_private *privlist[MAXCONTROLLERS];
109 static RTXBD rtx __attribute__ ((aligned(8)));
111 #error "rtx must be 64-bit aligned"
114 static int tsec_send(struct eth_device *dev,
115 volatile void *packet, int length);
116 static int tsec_recv(struct eth_device *dev);
117 static int tsec_init(struct eth_device *dev, bd_t * bd);
118 static void tsec_halt(struct eth_device *dev);
119 static void init_registers(volatile tsec_t * regs);
120 static void startup_tsec(struct eth_device *dev);
121 static int init_phy(struct eth_device *dev);
122 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
123 uint read_phy_reg(struct tsec_private *priv, uint regnum);
124 struct phy_info *get_phy_info(struct eth_device *dev);
125 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
126 static void adjust_link(struct eth_device *dev);
127 static void relocate_cmds(void);
128 static int tsec_miiphy_write(char *devname, unsigned char addr,
129 unsigned char reg, unsigned short value);
130 static int tsec_miiphy_read(char *devname, unsigned char addr,
131 unsigned char reg, unsigned short *value);
133 /* Initialize device structure. Returns success if PHY
134 * initialization succeeded (i.e. if it recognizes the PHY)
136 int tsec_initialize(bd_t * bis, int index, char *devname)
138 struct eth_device *dev;
140 struct tsec_private *priv;
142 dev = (struct eth_device *)malloc(sizeof *dev);
147 memset(dev, 0, sizeof *dev);
149 priv = (struct tsec_private *)malloc(sizeof(*priv));
154 privlist[index] = priv;
155 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
156 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
157 tsec_info[index].phyregidx *
160 priv->phyaddr = tsec_info[index].phyaddr;
161 priv->flags = tsec_info[index].flags;
163 sprintf(dev->name, devname);
166 dev->init = tsec_init;
167 dev->halt = tsec_halt;
168 dev->send = tsec_send;
169 dev->recv = tsec_recv;
171 /* Tell u-boot to get the addr from the env */
172 for (i = 0; i < 6; i++)
173 dev->enetaddr[i] = 0;
178 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
179 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
181 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
182 && !defined(BITBANGMII)
183 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
186 /* Try to initialize PHY here, and return */
187 return init_phy(dev);
190 /* Initializes data structures and registers for the controller,
191 * and brings the interface up. Returns the link status, meaning
192 * that it returns success if the link is up, failure otherwise.
193 * This allows u-boot to find the first active controller.
195 int tsec_init(struct eth_device *dev, bd_t * bd)
198 char tmpbuf[MAC_ADDR_LEN];
200 struct tsec_private *priv = (struct tsec_private *)dev->priv;
201 volatile tsec_t *regs = priv->regs;
203 /* Make sure the controller is stopped */
206 /* Init MACCFG2. Defaults to GMII */
207 regs->maccfg2 = MACCFG2_INIT_SETTINGS;
210 regs->ecntrl = ECNTRL_INIT_SETTINGS;
212 /* Copy the station address into the address registers.
213 * Backwards, because little endian MACS are dumb */
214 for (i = 0; i < MAC_ADDR_LEN; i++) {
215 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
217 regs->macstnaddr1 = *((uint *) (tmpbuf));
219 tempval = *((uint *) (tmpbuf + 4));
221 regs->macstnaddr2 = tempval;
223 /* reset the indices to zero */
227 /* Clear out (for the most part) the other registers */
228 init_registers(regs);
230 /* Ready the device for tx/rx */
233 /* If there's no link, fail */
238 /* Write value to the device's PHY through the registers
239 * specified in priv, modifying the register specified in regnum.
240 * It will wait for the write to be done (or for a timeout to
241 * expire) before exiting
243 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
245 volatile tsec_t *regbase = priv->phyregs;
246 uint phyid = priv->phyaddr;
247 int timeout = 1000000;
249 regbase->miimadd = (phyid << 8) | regnum;
250 regbase->miimcon = value;
254 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
257 /* Reads register regnum on the device's PHY through the
258 * registers specified in priv. It lowers and raises the read
259 * command, and waits for the data to become valid (miimind
260 * notvalid bit cleared), and the bus to cease activity (miimind
261 * busy bit cleared), and then returns the value
263 uint read_phy_reg(struct tsec_private *priv, uint regnum)
266 volatile tsec_t *regbase = priv->phyregs;
267 uint phyid = priv->phyaddr;
269 /* Put the address of the phy, and the register
270 * number into MIIMADD */
271 regbase->miimadd = (phyid << 8) | regnum;
273 /* Clear the command register, and wait */
274 regbase->miimcom = 0;
277 /* Initiate a read command, and wait */
278 regbase->miimcom = MIIM_READ_COMMAND;
281 /* Wait for the the indication that the read is done */
282 while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
284 /* Grab the value read from the PHY */
285 value = regbase->miimstat;
290 /* Discover which PHY is attached to the device, and configure it
291 * properly. If the PHY is not recognized, then return 0
292 * (failure). Otherwise, return 1
294 static int init_phy(struct eth_device *dev)
296 struct tsec_private *priv = (struct tsec_private *)dev->priv;
297 struct phy_info *curphy;
298 volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
300 /* Assign a Physical address to the TBI */
301 regs->tbipa = TBIPA_VALUE;
302 regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
303 regs->tbipa = TBIPA_VALUE;
306 /* Reset MII (due to new addresses) */
307 priv->phyregs->miimcfg = MIIMCFG_RESET;
309 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
311 while (priv->phyregs->miimind & MIIMIND_BUSY) ;
316 /* Get the cmd structure corresponding to the attached
318 curphy = get_phy_info(dev);
320 if (curphy == NULL) {
321 priv->phyinfo = NULL;
322 printf("%s: No PHY found\n", dev->name);
327 priv->phyinfo = curphy;
329 phy_run_commands(priv, priv->phyinfo->config);
335 * Returns which value to write to the control register.
336 * For 10/100, the value is slightly different
338 uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
340 if (priv->flags & TSEC_GIGABIT)
341 return MIIM_CONTROL_INIT;
346 /* Parse the status register for link, and then do
349 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
352 * Wait if PHY is capable of autonegotiation and autonegotiation
355 mii_reg = read_phy_reg(priv, MIIM_STATUS);
356 if ((mii_reg & PHY_BMSR_AUTN_ABLE)
357 && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
360 puts("Waiting for PHY auto negotiation to complete");
361 while (!((mii_reg & PHY_BMSR_AUTN_COMP)
362 && (mii_reg & MIIM_STATUS_LINK))) {
366 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
367 puts(" TIMEOUT !\n");
372 if ((i++ % 1000) == 0) {
375 udelay(1000); /* 1 ms */
376 mii_reg = read_phy_reg(priv, MIIM_STATUS);
380 udelay(500000); /* another 500 ms (results in faster booting) */
389 * Parse the BCM54xx status register for speed and duplex information.
390 * The linux sungem_phy has this information, but in a table format.
392 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
395 switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){
398 printf("Enet starting in 10BT/HD\n");
404 printf("Enet starting in 10BT/FD\n");
410 printf("Enet starting in 100BT/HD\n");
416 printf("Enet starting in 100BT/FD\n");
422 printf("Enet starting in 1000BT/HD\n");
428 printf("Enet starting in 1000BT/FD\n");
434 printf("Auto-neg error, defaulting to 10BT/HD\n");
443 /* Parse the 88E1011's status register for speed and duplex
446 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
450 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
452 if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
453 (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
456 puts("Waiting for PHY realtime link");
457 while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
458 (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
462 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
463 puts(" TIMEOUT !\n");
468 if ((i++ % 1000) == 0) {
471 udelay(1000); /* 1 ms */
472 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
475 udelay(500000); /* another 500 ms (results in faster booting) */
478 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
483 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
486 case MIIM_88E1011_PHYSTAT_GBIT:
489 case MIIM_88E1011_PHYSTAT_100:
499 /* Parse the cis8201's status register for speed and duplex
502 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
506 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
511 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
513 case MIIM_CIS8201_AUXCONSTAT_GBIT:
516 case MIIM_CIS8201_AUXCONSTAT_100:
527 /* Parse the vsc8244's status register for speed and duplex
530 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
534 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
539 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
541 case MIIM_VSC8244_AUXCONSTAT_GBIT:
544 case MIIM_VSC8244_AUXCONSTAT_100:
555 /* Parse the DM9161's status register for speed and duplex
558 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
560 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
565 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
574 * Hack to write all 4 PHYs with the LED values
576 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
579 volatile tsec_t *regbase = priv->phyregs;
580 int timeout = 1000000;
582 for (phyid = 0; phyid < 4; phyid++) {
583 regbase->miimadd = (phyid << 8) | mii_reg;
584 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
588 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
591 return MIIM_CIS8204_SLEDCON_INIT;
594 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
596 if (priv->flags & TSEC_REDUCED)
597 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
599 return MIIM_CIS8204_EPHYCON_INIT;
602 /* Initialized required registers to appropriate values, zeroing
603 * those we don't care about (unless zero is bad, in which case,
604 * choose a more appropriate value)
606 static void init_registers(volatile tsec_t * regs)
609 regs->ievent = IEVENT_INIT_CLEAR;
611 regs->imask = IMASK_INIT_CLEAR;
613 regs->hash.iaddr0 = 0;
614 regs->hash.iaddr1 = 0;
615 regs->hash.iaddr2 = 0;
616 regs->hash.iaddr3 = 0;
617 regs->hash.iaddr4 = 0;
618 regs->hash.iaddr5 = 0;
619 regs->hash.iaddr6 = 0;
620 regs->hash.iaddr7 = 0;
622 regs->hash.gaddr0 = 0;
623 regs->hash.gaddr1 = 0;
624 regs->hash.gaddr2 = 0;
625 regs->hash.gaddr3 = 0;
626 regs->hash.gaddr4 = 0;
627 regs->hash.gaddr5 = 0;
628 regs->hash.gaddr6 = 0;
629 regs->hash.gaddr7 = 0;
631 regs->rctrl = 0x00000000;
633 /* Init RMON mib registers */
634 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
636 regs->rmon.cam1 = 0xffffffff;
637 regs->rmon.cam2 = 0xffffffff;
639 regs->mrblr = MRBLR_INIT_SETTINGS;
641 regs->minflr = MINFLR_INIT_SETTINGS;
643 regs->attr = ATTR_INIT_SETTINGS;
644 regs->attreli = ATTRELI_INIT_SETTINGS;
648 /* Configure maccfg2 based on negotiated speed and duplex
649 * reported by PHY handling code
651 static void adjust_link(struct eth_device *dev)
653 struct tsec_private *priv = (struct tsec_private *)dev->priv;
654 volatile tsec_t *regs = priv->regs;
657 if (priv->duplexity != 0)
658 regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
660 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
662 switch (priv->speed) {
664 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
669 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
672 /* Set R100 bit in all modes although
673 * it is only used in RGMII mode
675 if (priv->speed == 100)
676 regs->ecntrl |= ECNTRL_R100;
678 regs->ecntrl &= ~(ECNTRL_R100);
681 printf("%s: Speed was bad\n", dev->name);
685 printf("Speed: %d, %s duplex\n", priv->speed,
686 (priv->duplexity) ? "full" : "half");
689 printf("%s: No link.\n", dev->name);
693 /* Set up the buffers and their descriptors, and bring up the
696 static void startup_tsec(struct eth_device *dev)
699 struct tsec_private *priv = (struct tsec_private *)dev->priv;
700 volatile tsec_t *regs = priv->regs;
702 /* Point to the buffer descriptors */
703 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
704 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
706 /* Initialize the Rx Buffer descriptors */
707 for (i = 0; i < PKTBUFSRX; i++) {
708 rtx.rxbd[i].status = RXBD_EMPTY;
709 rtx.rxbd[i].length = 0;
710 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
712 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
714 /* Initialize the TX Buffer Descriptors */
715 for (i = 0; i < TX_BUF_CNT; i++) {
716 rtx.txbd[i].status = 0;
717 rtx.txbd[i].length = 0;
718 rtx.txbd[i].bufPtr = 0;
720 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
722 /* Start up the PHY */
724 phy_run_commands(priv, priv->phyinfo->startup);
727 /* Enable Transmit and Receive */
728 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
730 /* Tell the DMA it is clear to go */
731 regs->dmactrl |= DMACTRL_INIT_SETTINGS;
732 regs->tstat = TSTAT_CLEAR_THALT;
733 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
736 /* This returns the status bits of the device. The return value
737 * is never checked, and this is what the 8260 driver did, so we
738 * do the same. Presumably, this would be zero if there were no
741 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
745 struct tsec_private *priv = (struct tsec_private *)dev->priv;
746 volatile tsec_t *regs = priv->regs;
748 /* Find an empty buffer descriptor */
749 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
750 if (i >= TOUT_LOOP) {
751 debug("%s: tsec: tx buffers full\n", dev->name);
756 rtx.txbd[txIdx].bufPtr = (uint) packet;
757 rtx.txbd[txIdx].length = length;
758 rtx.txbd[txIdx].status |=
759 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
761 /* Tell the DMA to go */
762 regs->tstat = TSTAT_CLEAR_THALT;
764 /* Wait for buffer to be transmitted */
765 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
766 if (i >= TOUT_LOOP) {
767 debug("%s: tsec: tx error\n", dev->name);
772 txIdx = (txIdx + 1) % TX_BUF_CNT;
773 result = rtx.txbd[txIdx].status & TXBD_STATS;
778 static int tsec_recv(struct eth_device *dev)
781 struct tsec_private *priv = (struct tsec_private *)dev->priv;
782 volatile tsec_t *regs = priv->regs;
784 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
786 length = rtx.rxbd[rxIdx].length;
788 /* Send the packet up if there were no errors */
789 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
790 NetReceive(NetRxPackets[rxIdx], length - 4);
792 printf("Got error %x\n",
793 (rtx.rxbd[rxIdx].status & RXBD_STATS));
796 rtx.rxbd[rxIdx].length = 0;
798 /* Set the wrap bit if this is the last element in the list */
799 rtx.rxbd[rxIdx].status =
800 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
802 rxIdx = (rxIdx + 1) % PKTBUFSRX;
805 if (regs->ievent & IEVENT_BSY) {
806 regs->ievent = IEVENT_BSY;
807 regs->rstat = RSTAT_CLEAR_RHALT;
814 /* Stop the interface */
815 static void tsec_halt(struct eth_device *dev)
817 struct tsec_private *priv = (struct tsec_private *)dev->priv;
818 volatile tsec_t *regs = priv->regs;
820 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
821 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
823 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
825 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
827 /* Shut down the PHY, as needed */
829 phy_run_commands(priv, priv->phyinfo->shutdown);
832 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
833 struct phy_info phy_info_BCM5461S = {
834 0x02060c1, /* 5461 ID */
836 0, /* not clear to me what minor revisions we can shift away */
837 (struct phy_cmd[]) { /* config */
838 /* Reset and configure the PHY */
839 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
840 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
841 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
842 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
843 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
846 (struct phy_cmd[]) { /* startup */
847 /* Status is read once to clear old link state */
848 {MIIM_STATUS, miim_read, NULL},
850 {MIIM_STATUS, miim_read, &mii_parse_sr},
851 /* Read the status */
852 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
855 (struct phy_cmd[]) { /* shutdown */
860 struct phy_info phy_info_M88E1011S = {
864 (struct phy_cmd[]){ /* config */
865 /* Reset and configure the PHY */
866 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
868 {0x1e, 0x200c, NULL},
872 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
873 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
874 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
875 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
878 (struct phy_cmd[]){ /* startup */
879 /* Status is read once to clear old link state */
880 {MIIM_STATUS, miim_read, NULL},
882 {MIIM_STATUS, miim_read, &mii_parse_sr},
883 /* Read the status */
884 {MIIM_88E1011_PHY_STATUS, miim_read,
885 &mii_parse_88E1011_psr},
888 (struct phy_cmd[]){ /* shutdown */
893 struct phy_info phy_info_M88E1111S = {
897 (struct phy_cmd[]){ /* config */
898 /* Reset and configure the PHY */
899 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
901 {0x1e, 0x200c, NULL},
905 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
906 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
907 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
908 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
909 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
912 (struct phy_cmd[]){ /* startup */
913 /* Status is read once to clear old link state */
914 {MIIM_STATUS, miim_read, NULL},
916 {MIIM_STATUS, miim_read, &mii_parse_sr},
917 /* Read the status */
918 {MIIM_88E1011_PHY_STATUS, miim_read,
919 &mii_parse_88E1011_psr},
922 (struct phy_cmd[]){ /* shutdown */
927 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
929 uint mii_data = read_phy_reg(priv, mii_reg);
931 /* Setting MIIM_88E1145_PHY_EXT_CR */
932 if (priv->flags & TSEC_REDUCED)
934 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
939 static struct phy_info phy_info_M88E1145 = {
943 (struct phy_cmd[]){ /* config */
950 /* Reset and configure the PHY */
951 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
952 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
953 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
954 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
956 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
957 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
958 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
961 (struct phy_cmd[]){ /* startup */
962 /* Status is read once to clear old link state */
963 {MIIM_STATUS, miim_read, NULL},
965 {MIIM_STATUS, miim_read, &mii_parse_sr},
966 {MIIM_88E1111_PHY_LED_CONTROL,
967 MIIM_88E1111_PHY_LED_DIRECT, NULL},
968 /* Read the Status */
969 {MIIM_88E1011_PHY_STATUS, miim_read,
970 &mii_parse_88E1011_psr},
973 (struct phy_cmd[]){ /* shutdown */
978 struct phy_info phy_info_cis8204 = {
982 (struct phy_cmd[]){ /* config */
983 /* Override PHY config settings */
984 {MIIM_CIS8201_AUX_CONSTAT,
985 MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
986 /* Configure some basic stuff */
987 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
988 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
989 &mii_cis8204_fixled},
990 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
991 &mii_cis8204_setmode},
994 (struct phy_cmd[]){ /* startup */
995 /* Read the Status (2x to make sure link is right) */
996 {MIIM_STATUS, miim_read, NULL},
998 {MIIM_STATUS, miim_read, &mii_parse_sr},
999 /* Read the status */
1000 {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1001 &mii_parse_cis8201},
1004 (struct phy_cmd[]){ /* shutdown */
1010 struct phy_info phy_info_cis8201 = {
1014 (struct phy_cmd[]){ /* config */
1015 /* Override PHY config settings */
1016 {MIIM_CIS8201_AUX_CONSTAT,
1017 MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1018 /* Set up the interface mode */
1019 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
1021 /* Configure some basic stuff */
1022 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1025 (struct phy_cmd[]){ /* startup */
1026 /* Read the Status (2x to make sure link is right) */
1027 {MIIM_STATUS, miim_read, NULL},
1028 /* Auto-negotiate */
1029 {MIIM_STATUS, miim_read, &mii_parse_sr},
1030 /* Read the status */
1031 {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1032 &mii_parse_cis8201},
1035 (struct phy_cmd[]){ /* shutdown */
1039 struct phy_info phy_info_VSC8244 = {
1043 (struct phy_cmd[]){ /* config */
1044 /* Override PHY config settings */
1045 /* Configure some basic stuff */
1046 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1049 (struct phy_cmd[]){ /* startup */
1050 /* Read the Status (2x to make sure link is right) */
1051 {MIIM_STATUS, miim_read, NULL},
1052 /* Auto-negotiate */
1053 {MIIM_STATUS, miim_read, &mii_parse_sr},
1054 /* Read the status */
1055 {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1056 &mii_parse_vsc8244},
1059 (struct phy_cmd[]){ /* shutdown */
1064 struct phy_info phy_info_dm9161 = {
1068 (struct phy_cmd[]){ /* config */
1069 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1070 /* Do not bypass the scrambler/descrambler */
1071 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1072 /* Clear 10BTCSR to default */
1073 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
1075 /* Configure some basic stuff */
1076 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1077 /* Restart Auto Negotiation */
1078 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1081 (struct phy_cmd[]){ /* startup */
1082 /* Status is read once to clear old link state */
1083 {MIIM_STATUS, miim_read, NULL},
1084 /* Auto-negotiate */
1085 {MIIM_STATUS, miim_read, &mii_parse_sr},
1086 /* Read the status */
1087 {MIIM_DM9161_SCSR, miim_read,
1088 &mii_parse_dm9161_scsr},
1091 (struct phy_cmd[]){ /* shutdown */
1096 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1100 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1103 case MIIM_LXT971_SR2_10HDX:
1105 priv->duplexity = 0;
1107 case MIIM_LXT971_SR2_10FDX:
1109 priv->duplexity = 1;
1111 case MIIM_LXT971_SR2_100HDX:
1113 priv->duplexity = 0;
1116 priv->duplexity = 1;
1121 priv->duplexity = 0;
1127 static struct phy_info phy_info_lxt971 = {
1131 (struct phy_cmd[]){ /* config */
1132 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */
1135 (struct phy_cmd[]){ /* startup - enable interrupts */
1136 /* { 0x12, 0x00f2, NULL }, */
1137 {MIIM_STATUS, miim_read, NULL},
1138 {MIIM_STATUS, miim_read, &mii_parse_sr},
1139 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1142 (struct phy_cmd[]){ /* shutdown - disable interrupts */
1147 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1150 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1152 switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1154 case MIIM_DP83865_SPD_1000:
1158 case MIIM_DP83865_SPD_100:
1168 if (mii_reg & MIIM_DP83865_DPX_FULL)
1169 priv->duplexity = 1;
1171 priv->duplexity = 0;
1176 struct phy_info phy_info_dp83865 = {
1180 (struct phy_cmd[]){ /* config */
1181 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1184 (struct phy_cmd[]){ /* startup */
1185 /* Status is read once to clear old link state */
1186 {MIIM_STATUS, miim_read, NULL},
1187 /* Auto-negotiate */
1188 {MIIM_STATUS, miim_read, &mii_parse_sr},
1189 /* Read the link and auto-neg status */
1190 {MIIM_DP83865_LANR, miim_read,
1191 &mii_parse_dp83865_lanr},
1194 (struct phy_cmd[]){ /* shutdown */
1199 struct phy_info *phy_info[] = {
1203 &phy_info_M88E1011S,
1204 &phy_info_M88E1111S,
1213 /* Grab the identifier of the device's PHY, and search through
1214 * all of the known PHYs to see if one matches. If so, return
1215 * it, if not, return NULL
1217 struct phy_info *get_phy_info(struct eth_device *dev)
1219 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1220 uint phy_reg, phy_ID;
1222 struct phy_info *theInfo = NULL;
1224 /* Grab the bits from PHYIR1, and put them in the upper half */
1225 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1226 phy_ID = (phy_reg & 0xffff) << 16;
1228 /* Grab the bits from PHYIR2, and put them in the lower half */
1229 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1230 phy_ID |= (phy_reg & 0xffff);
1232 /* loop through all the known PHY types, and find one that */
1233 /* matches the ID we read from the PHY. */
1234 for (i = 0; phy_info[i]; i++) {
1235 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
1236 theInfo = phy_info[i];
1239 if (theInfo == NULL) {
1240 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
1243 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1249 /* Execute the given series of commands on the given device's
1250 * PHY, running functions as necessary
1252 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1256 volatile tsec_t *phyregs = priv->phyregs;
1258 phyregs->miimcfg = MIIMCFG_RESET;
1260 phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1262 while (phyregs->miimind & MIIMIND_BUSY) ;
1264 for (i = 0; cmd->mii_reg != miim_end; i++) {
1265 if (cmd->mii_data == miim_read) {
1266 result = read_phy_reg(priv, cmd->mii_reg);
1268 if (cmd->funct != NULL)
1269 (*(cmd->funct)) (result, priv);
1272 if (cmd->funct != NULL)
1273 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1275 result = cmd->mii_data;
1277 write_phy_reg(priv, cmd->mii_reg, result);
1284 /* Relocate the function pointers in the phy cmd lists */
1285 static void relocate_cmds(void)
1287 struct phy_cmd **cmdlistptr;
1288 struct phy_cmd *cmd;
1291 for (i = 0; phy_info[i]; i++) {
1292 /* First thing's first: relocate the pointers to the
1293 * PHY command structures (the structs were done) */
1294 phy_info[i] = (struct phy_info *)((uint) phy_info[i]
1296 phy_info[i]->name += gd->reloc_off;
1297 phy_info[i]->config =
1298 (struct phy_cmd *)((uint) phy_info[i]->config
1300 phy_info[i]->startup =
1301 (struct phy_cmd *)((uint) phy_info[i]->startup
1303 phy_info[i]->shutdown =
1304 (struct phy_cmd *)((uint) phy_info[i]->shutdown
1307 cmdlistptr = &phy_info[i]->config;
1309 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
1311 for (cmd = *cmdlistptr;
1312 cmd->mii_reg != miim_end;
1314 /* Only relocate non-NULL pointers */
1316 cmd->funct += gd->reloc_off;
1327 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
1328 && !defined(BITBANGMII)
1330 struct tsec_private *get_priv_for_phy(unsigned char phyaddr)
1334 for (i = 0; i < MAXCONTROLLERS; i++) {
1335 if (privlist[i]->phyaddr == phyaddr)
1343 * Read a MII PHY register.
1348 static int tsec_miiphy_read(char *devname, unsigned char addr,
1349 unsigned char reg, unsigned short *value)
1352 struct tsec_private *priv = get_priv_for_phy(addr);
1355 printf("Can't read PHY at address %d\n", addr);
1359 ret = (unsigned short)read_phy_reg(priv, reg);
1366 * Write a MII PHY register.
1371 static int tsec_miiphy_write(char *devname, unsigned char addr,
1372 unsigned char reg, unsigned short value)
1374 struct tsec_private *priv = get_priv_for_phy(addr);
1377 printf("Can't write PHY at address %d\n", addr);
1381 write_phy_reg(priv, reg, value);
1386 #endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1387 && !defined(BITBANGMII) */
1389 #endif /* CONFIG_TSEC_ENET */