3 * Freescale Three Speed Ethernet Controller driver
5 * This software may be used and distributed according to the
6 * terms of the GNU Public License, Version 2, incorporated
9 * Copyright 2004 Freescale Semiconductor.
10 * (C) Copyright 2003, Motorola, Inc.
22 #if defined(CONFIG_TSEC_ENET)
27 static uint rxIdx; /* index of the current RX buffer */
28 static uint txIdx; /* index of the current TX buffer */
30 typedef volatile struct rtxbd {
31 txbd8_t txbd[TX_BUF_CNT];
32 rxbd8_t rxbd[PKTBUFSRX];
35 struct tsec_info_struct {
38 unsigned int phyregidx;
42 /* The tsec_info structure contains 3 values which the
43 * driver uses to determine how to operate a given ethernet
44 * device. For now, the structure is initialized with the
45 * knowledge that all current implementations have 2 TSEC
46 * devices, and one FEC. The information needed is:
47 * phyaddr - The address of the PHY which is attached to
50 * flags - This variable indicates whether the device
51 * supports gigabit speed ethernet, and whether it should be
54 * phyregidx - This variable specifies which ethernet device
55 * controls the MII Management registers which are connected
56 * to the PHY. For 8540/8560, only TSEC1 (index 0) has
57 * access to the PHYs, so all of the entries have "0".
59 * The values specified in the table are taken from the board's
60 * config file in include/configs/. When implementing a new
61 * board with ethernet capability, it is necessary to define:
71 static struct tsec_info_struct tsec_info[] = {
72 #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
73 {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
77 #if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
78 {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
82 #ifdef CONFIG_MPC85XX_FEC
83 {FEC_PHY_ADDR, 0, FEC_PHYIDX},
85 # if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3)
86 {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
90 # if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4)
91 {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX},
98 #define MAXCONTROLLERS (4)
100 static int relocated = 0;
102 static struct tsec_private *privlist[MAXCONTROLLERS];
105 static RTXBD rtx __attribute__ ((aligned(8)));
107 #error "rtx must be 64-bit aligned"
110 static int tsec_send(struct eth_device* dev, volatile void *packet, int length);
111 static int tsec_recv(struct eth_device* dev);
112 static int tsec_init(struct eth_device* dev, bd_t * bd);
113 static void tsec_halt(struct eth_device* dev);
114 static void init_registers(volatile tsec_t *regs);
115 static void startup_tsec(struct eth_device *dev);
116 static int init_phy(struct eth_device *dev);
117 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
118 uint read_phy_reg(struct tsec_private *priv, uint regnum);
119 struct phy_info * get_phy_info(struct eth_device *dev);
120 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
121 static void adjust_link(struct eth_device *dev);
122 static void relocate_cmds(void);
124 /* Initialize device structure. Returns success if PHY
125 * initialization succeeded (i.e. if it recognizes the PHY)
127 int tsec_initialize(bd_t *bis, int index, char *devname)
129 struct eth_device* dev;
131 struct tsec_private *priv;
133 dev = (struct eth_device*) malloc(sizeof *dev);
138 memset(dev, 0, sizeof *dev);
140 priv = (struct tsec_private *) malloc(sizeof(*priv));
145 privlist[index] = priv;
146 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index*TSEC_SIZE);
147 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
148 tsec_info[index].phyregidx*TSEC_SIZE);
150 priv->phyaddr = tsec_info[index].phyaddr;
151 priv->flags = tsec_info[index].flags;
153 sprintf(dev->name, devname);
156 dev->init = tsec_init;
157 dev->halt = tsec_halt;
158 dev->send = tsec_send;
159 dev->recv = tsec_recv;
161 /* Tell u-boot to get the addr from the env */
163 dev->enetaddr[i] = 0;
169 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
170 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
172 /* Try to initialize PHY here, and return */
173 return init_phy(dev);
177 /* Initializes data structures and registers for the controller,
178 * and brings the interface up. Returns the link status, meaning
179 * that it returns success if the link is up, failure otherwise.
180 * This allows u-boot to find the first active controller. */
181 int tsec_init(struct eth_device* dev, bd_t * bd)
184 char tmpbuf[MAC_ADDR_LEN];
186 struct tsec_private *priv = (struct tsec_private *)dev->priv;
187 volatile tsec_t *regs = priv->regs;
189 /* Make sure the controller is stopped */
192 /* Init MACCFG2. Defaults to GMII */
193 regs->maccfg2 = MACCFG2_INIT_SETTINGS;
196 regs->ecntrl = ECNTRL_INIT_SETTINGS;
198 /* Copy the station address into the address registers.
199 * Backwards, because little endian MACS are dumb */
200 for(i=0;i<MAC_ADDR_LEN;i++) {
201 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
203 (uint)(regs->macstnaddr1) = *((uint *)(tmpbuf));
205 tempval = *((uint *)(tmpbuf +4));
207 (uint)(regs->macstnaddr2) = tempval;
209 /* reset the indices to zero */
213 /* Clear out (for the most part) the other registers */
214 init_registers(regs);
216 /* Ready the device for tx/rx */
219 /* If there's no link, fail */
225 /* Write value to the device's PHY through the registers
226 * specified in priv, modifying the register specified in regnum.
227 * It will wait for the write to be done (or for a timeout to
228 * expire) before exiting
230 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
232 volatile tsec_t *regbase = priv->phyregs;
233 uint phyid = priv->phyaddr;
236 regbase->miimadd = (phyid << 8) | regnum;
237 regbase->miimcon = value;
241 while((regbase->miimind & MIIMIND_BUSY) && timeout--);
245 /* Reads register regnum on the device's PHY through the
246 * registers specified in priv. It lowers and raises the read
247 * command, and waits for the data to become valid (miimind
248 * notvalid bit cleared), and the bus to cease activity (miimind
249 * busy bit cleared), and then returns the value
251 uint read_phy_reg(struct tsec_private *priv, uint regnum)
254 volatile tsec_t *regbase = priv->phyregs;
255 uint phyid = priv->phyaddr;
257 /* Put the address of the phy, and the register
258 * number into MIIMADD */
259 regbase->miimadd = (phyid << 8) | regnum;
261 /* Clear the command register, and wait */
262 regbase->miimcom = 0;
265 /* Initiate a read command, and wait */
266 regbase->miimcom = MIIM_READ_COMMAND;
269 /* Wait for the the indication that the read is done */
270 while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
272 /* Grab the value read from the PHY */
273 value = regbase->miimstat;
279 /* Discover which PHY is attached to the device, and configure it
280 * properly. If the PHY is not recognized, then return 0
281 * (failure). Otherwise, return 1
283 static int init_phy(struct eth_device *dev)
285 struct tsec_private *priv = (struct tsec_private *)dev->priv;
286 struct phy_info *curphy;
288 /* Assign a Physical address to the TBI */
291 volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
292 regs->tbipa = TBIPA_VALUE;
293 regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
294 regs->tbipa = TBIPA_VALUE;
298 /* Reset MII (due to new addresses) */
299 priv->phyregs->miimcfg = MIIMCFG_RESET;
301 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
303 while(priv->phyregs->miimind & MIIMIND_BUSY);
308 /* Get the cmd structure corresponding to the attached
310 curphy = get_phy_info(dev);
313 printf("%s: No PHY found\n", dev->name);
318 priv->phyinfo = curphy;
320 phy_run_commands(priv, priv->phyinfo->config);
326 /* Returns which value to write to the control register. */
327 /* For 10/100, the value is slightly different */
328 uint mii_cr_init(uint mii_reg, struct tsec_private *priv)
330 if(priv->flags & TSEC_GIGABIT)
331 return MIIM_CONTROL_INIT;
337 /* Parse the status register for link, and then do
338 * auto-negotiation */
339 uint mii_parse_sr(uint mii_reg, struct tsec_private *priv)
341 uint timeout = TSEC_TIMEOUT;
343 if(mii_reg & MIIM_STATUS_LINK)
349 while((!(mii_reg & MIIM_STATUS_AN_DONE)) && timeout--)
350 mii_reg = read_phy_reg(priv, MIIM_STATUS);
357 /* Parse the 88E1011's status register for speed and duplex
359 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv)
363 if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
368 speed = (mii_reg &MIIM_88E1011_PHYSTAT_SPEED);
371 case MIIM_88E1011_PHYSTAT_GBIT:
374 case MIIM_88E1011_PHYSTAT_100:
385 /* Parse the cis8201's status register for speed and duplex
387 uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv)
391 if(mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
396 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
398 case MIIM_CIS8201_AUXCONSTAT_GBIT:
401 case MIIM_CIS8201_AUXCONSTAT_100:
413 /* Parse the DM9161's status register for speed and duplex
415 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv)
417 if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
422 if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
431 /* Hack to write all 4 PHYs with the LED values */
432 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv)
435 volatile tsec_t *regbase = priv->phyregs;
438 for(phyid=0;phyid<4;phyid++) {
439 regbase->miimadd = (phyid << 8) | mii_reg;
440 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
444 while((regbase->miimind & MIIMIND_BUSY) && timeout--);
447 return MIIM_CIS8204_SLEDCON_INIT;
450 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private *priv)
452 if (priv->flags & TSEC_REDUCED)
453 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
455 return MIIM_CIS8204_EPHYCON_INIT;
458 /* Initialized required registers to appropriate values, zeroing
459 * those we don't care about (unless zero is bad, in which case,
460 * choose a more appropriate value) */
461 static void init_registers(volatile tsec_t *regs)
464 regs->ievent = IEVENT_INIT_CLEAR;
466 regs->imask = IMASK_INIT_CLEAR;
468 regs->hash.iaddr0 = 0;
469 regs->hash.iaddr1 = 0;
470 regs->hash.iaddr2 = 0;
471 regs->hash.iaddr3 = 0;
472 regs->hash.iaddr4 = 0;
473 regs->hash.iaddr5 = 0;
474 regs->hash.iaddr6 = 0;
475 regs->hash.iaddr7 = 0;
477 regs->hash.gaddr0 = 0;
478 regs->hash.gaddr1 = 0;
479 regs->hash.gaddr2 = 0;
480 regs->hash.gaddr3 = 0;
481 regs->hash.gaddr4 = 0;
482 regs->hash.gaddr5 = 0;
483 regs->hash.gaddr6 = 0;
484 regs->hash.gaddr7 = 0;
486 regs->rctrl = 0x00000000;
488 /* Init RMON mib registers */
489 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
491 regs->rmon.cam1 = 0xffffffff;
492 regs->rmon.cam2 = 0xffffffff;
494 regs->mrblr = MRBLR_INIT_SETTINGS;
496 regs->minflr = MINFLR_INIT_SETTINGS;
498 regs->attr = ATTR_INIT_SETTINGS;
499 regs->attreli = ATTRELI_INIT_SETTINGS;
504 /* Configure maccfg2 based on negotiated speed and duplex
505 * reported by PHY handling code */
506 static void adjust_link(struct eth_device *dev)
508 struct tsec_private *priv = (struct tsec_private *)dev->priv;
509 volatile tsec_t *regs = priv->regs;
512 if(priv->duplexity != 0)
513 regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
515 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
517 switch(priv->speed) {
519 regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
524 regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
527 /* If We're in reduced mode, we need
528 * to say whether we're 10 or 100 MB.
530 if ((priv->speed == 100)
531 && (priv->flags & TSEC_REDUCED))
532 regs->ecntrl |= ECNTRL_R100;
534 regs->ecntrl &= ~(ECNTRL_R100);
537 printf("%s: Speed was bad\n", dev->name);
541 printf("Speed: %d, %s duplex\n", priv->speed,
542 (priv->duplexity) ? "full" : "half");
545 printf("%s: No link.\n", dev->name);
550 /* Set up the buffers and their descriptors, and bring up the
552 static void startup_tsec(struct eth_device *dev)
555 struct tsec_private *priv = (struct tsec_private *)dev->priv;
556 volatile tsec_t *regs = priv->regs;
558 /* Point to the buffer descriptors */
559 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
560 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
562 /* Initialize the Rx Buffer descriptors */
563 for (i = 0; i < PKTBUFSRX; i++) {
564 rtx.rxbd[i].status = RXBD_EMPTY;
565 rtx.rxbd[i].length = 0;
566 rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i];
568 rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP;
570 /* Initialize the TX Buffer Descriptors */
571 for(i=0; i<TX_BUF_CNT; i++) {
572 rtx.txbd[i].status = 0;
573 rtx.txbd[i].length = 0;
574 rtx.txbd[i].bufPtr = 0;
576 rtx.txbd[TX_BUF_CNT -1].status |= TXBD_WRAP;
578 /* Start up the PHY */
579 phy_run_commands(priv, priv->phyinfo->startup);
582 /* Enable Transmit and Receive */
583 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
585 /* Tell the DMA it is clear to go */
586 regs->dmactrl |= DMACTRL_INIT_SETTINGS;
587 regs->tstat = TSTAT_CLEAR_THALT;
588 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
591 /* This returns the status bits of the device. The return value
592 * is never checked, and this is what the 8260 driver did, so we
593 * do the same. Presumably, this would be zero if there were no
595 static int tsec_send(struct eth_device* dev, volatile void *packet, int length)
599 struct tsec_private *priv = (struct tsec_private *)dev->priv;
600 volatile tsec_t *regs = priv->regs;
602 /* Find an empty buffer descriptor */
603 for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
604 if (i >= TOUT_LOOP) {
605 debug ("%s: tsec: tx buffers full\n", dev->name);
610 rtx.txbd[txIdx].bufPtr = (uint)packet;
611 rtx.txbd[txIdx].length = length;
612 rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
614 /* Tell the DMA to go */
615 regs->tstat = TSTAT_CLEAR_THALT;
617 /* Wait for buffer to be transmitted */
618 for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
619 if (i >= TOUT_LOOP) {
620 debug ("%s: tsec: tx error\n", dev->name);
625 txIdx = (txIdx + 1) % TX_BUF_CNT;
626 result = rtx.txbd[txIdx].status & TXBD_STATS;
631 static int tsec_recv(struct eth_device* dev)
634 struct tsec_private *priv = (struct tsec_private *)dev->priv;
635 volatile tsec_t *regs = priv->regs;
637 while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
639 length = rtx.rxbd[rxIdx].length;
641 /* Send the packet up if there were no errors */
642 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
643 NetReceive(NetRxPackets[rxIdx], length - 4);
645 printf("Got error %x\n",
646 (rtx.rxbd[rxIdx].status & RXBD_STATS));
649 rtx.rxbd[rxIdx].length = 0;
651 /* Set the wrap bit if this is the last element in the list */
652 rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
654 rxIdx = (rxIdx + 1) % PKTBUFSRX;
657 if(regs->ievent&IEVENT_BSY) {
658 regs->ievent = IEVENT_BSY;
659 regs->rstat = RSTAT_CLEAR_RHALT;
667 /* Stop the interface */
668 static void tsec_halt(struct eth_device* dev)
670 struct tsec_private *priv = (struct tsec_private *)dev->priv;
671 volatile tsec_t *regs = priv->regs;
673 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
674 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
676 while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)));
678 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
680 /* Shut down the PHY, as needed */
681 phy_run_commands(priv, priv->phyinfo->shutdown);
685 struct phy_info phy_info_M88E1011S = {
689 (struct phy_cmd[]) { /* config */
690 /* Reset and configure the PHY */
691 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
693 {0x1e, 0x200c, NULL},
697 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
698 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
699 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
700 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
703 (struct phy_cmd[]) { /* startup */
704 /* Status is read once to clear old link state */
705 {MIIM_STATUS, miim_read, NULL},
707 {MIIM_STATUS, miim_read, &mii_parse_sr},
708 /* Read the status */
709 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
712 (struct phy_cmd[]) { /* shutdown */
717 struct phy_info phy_info_M88E1111S = {
721 (struct phy_cmd[]) { /* config */
722 /* Reset and configure the PHY */
723 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
725 {0x1e, 0x200c, NULL},
729 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
730 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
731 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
732 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
735 (struct phy_cmd[]) { /* startup */
736 /* Status is read once to clear old link state */
737 {MIIM_STATUS, miim_read, NULL},
739 {MIIM_STATUS, miim_read, &mii_parse_sr},
740 /* Read the status */
741 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
744 (struct phy_cmd[]) { /* shutdown */
749 struct phy_info phy_info_cis8204 = {
753 (struct phy_cmd[]) { /* config */
754 /* Override PHY config settings */
755 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
756 /* Configure some basic stuff */
757 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
758 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled},
759 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, &mii_cis8204_setmode},
762 (struct phy_cmd[]) { /* startup */
763 /* Read the Status (2x to make sure link is right) */
764 {MIIM_STATUS, miim_read, NULL},
766 {MIIM_STATUS, miim_read, &mii_parse_sr},
767 /* Read the status */
768 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
771 (struct phy_cmd[]) { /* shutdown */
777 struct phy_info phy_info_cis8201 = {
781 (struct phy_cmd[]) { /* config */
782 /* Override PHY config settings */
783 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
784 /* Set up the interface mode */
785 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
786 /* Configure some basic stuff */
787 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
790 (struct phy_cmd[]) { /* startup */
791 /* Read the Status (2x to make sure link is right) */
792 {MIIM_STATUS, miim_read, NULL},
794 {MIIM_STATUS, miim_read, &mii_parse_sr},
795 /* Read the status */
796 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
799 (struct phy_cmd[]) { /* shutdown */
805 struct phy_info phy_info_dm9161 = {
809 (struct phy_cmd[]) { /* config */
810 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
811 /* Do not bypass the scrambler/descrambler */
812 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
813 /* Clear 10BTCSR to default */
814 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL},
815 /* Configure some basic stuff */
816 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
817 /* Restart Auto Negotiation */
818 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
821 (struct phy_cmd[]) { /* startup */
822 /* Status is read once to clear old link state */
823 {MIIM_STATUS, miim_read, NULL},
825 {MIIM_STATUS, miim_read, &mii_parse_sr},
826 /* Read the status */
827 {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr},
830 (struct phy_cmd[]) { /* shutdown */
835 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
839 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
842 case MIIM_LXT971_SR2_10HDX:
846 case MIIM_LXT971_SR2_10FDX:
850 case MIIM_LXT971_SR2_100HDX:
866 static struct phy_info phy_info_lxt971 = {
870 (struct phy_cmd []) { /* config */
871 { MIIM_CR, MIIM_CR_INIT, mii_cr_init }, /* autonegotiate */
874 (struct phy_cmd []) { /* startup - enable interrupts */
875 /* { 0x12, 0x00f2, NULL }, */
876 { MIIM_STATUS, miim_read, NULL },
877 { MIIM_STATUS, miim_read, &mii_parse_sr },
878 { MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2 },
881 (struct phy_cmd []) { /* shutdown - disable interrupts */
886 struct phy_info *phy_info[] = {
899 /* Grab the identifier of the device's PHY, and search through
900 * all of the known PHYs to see if one matches. If so, return
901 * it, if not, return NULL */
902 struct phy_info * get_phy_info(struct eth_device *dev)
904 struct tsec_private *priv = (struct tsec_private *)dev->priv;
905 uint phy_reg, phy_ID;
907 struct phy_info *theInfo = NULL;
909 /* Grab the bits from PHYIR1, and put them in the upper half */
910 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
911 phy_ID = (phy_reg & 0xffff) << 16;
913 /* Grab the bits from PHYIR2, and put them in the lower half */
914 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
915 phy_ID |= (phy_reg & 0xffff);
917 /* loop through all the known PHY types, and find one that */
918 /* matches the ID we read from the PHY. */
919 for(i=0; phy_info[i]; i++) {
920 if(phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
921 theInfo = phy_info[i];
926 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
929 printf("%s: PHY is %s (%x)\n", dev->name, theInfo->name,
937 /* Execute the given series of commands on the given device's
938 * PHY, running functions as necessary*/
939 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
943 volatile tsec_t *phyregs = priv->phyregs;
945 phyregs->miimcfg = MIIMCFG_RESET;
947 phyregs->miimcfg = MIIMCFG_INIT_VALUE;
949 while(phyregs->miimind & MIIMIND_BUSY);
951 for(i=0;cmd->mii_reg != miim_end;i++) {
952 if(cmd->mii_data == miim_read) {
953 result = read_phy_reg(priv, cmd->mii_reg);
955 if(cmd->funct != NULL)
956 (*(cmd->funct))(result, priv);
959 if(cmd->funct != NULL)
960 result = (*(cmd->funct))(cmd->mii_reg, priv);
962 result = cmd->mii_data;
964 write_phy_reg(priv, cmd->mii_reg, result);
972 /* Relocate the function pointers in the phy cmd lists */
973 static void relocate_cmds(void)
975 struct phy_cmd **cmdlistptr;
978 DECLARE_GLOBAL_DATA_PTR;
980 for(i=0; phy_info[i]; i++) {
981 /* First thing's first: relocate the pointers to the
982 * PHY command structures (the structs were done) */
983 phy_info[i] = (struct phy_info *) ((uint)phy_info[i]
985 phy_info[i]->name += gd->reloc_off;
986 phy_info[i]->config =
987 (struct phy_cmd *)((uint)phy_info[i]->config
989 phy_info[i]->startup =
990 (struct phy_cmd *)((uint)phy_info[i]->startup
992 phy_info[i]->shutdown =
993 (struct phy_cmd *)((uint)phy_info[i]->shutdown
996 cmdlistptr = &phy_info[i]->config;
998 for(;cmdlistptr <= &phy_info[i]->shutdown;cmdlistptr++) {
1000 for(cmd=*cmdlistptr;cmd->mii_reg != miim_end;cmd++) {
1001 /* Only relocate non-NULL pointers */
1003 cmd->funct += gd->reloc_off;
1015 #ifndef CONFIG_BITBANGMII
1017 struct tsec_private * get_priv_for_phy(unsigned char phyaddr)
1021 for(i=0;i<MAXCONTROLLERS;i++) {
1022 if(privlist[i]->phyaddr == phyaddr)
1030 * Read a MII PHY register.
1035 int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
1038 struct tsec_private *priv = get_priv_for_phy(addr);
1041 printf("Can't read PHY at address %d\n", addr);
1045 ret = (unsigned short)read_phy_reg(priv, reg);
1052 * Write a MII PHY register.
1057 int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
1059 struct tsec_private *priv = get_priv_for_phy(addr);
1062 printf("Can't write PHY at address %d\n", addr);
1066 write_phy_reg(priv, reg, value);
1071 #endif /* CONFIG_BITBANGMII */
1073 #endif /* CONFIG_TSEC_ENET */