3 * Freescale Three Speed Ethernet Controller driver
5 * This software may be used and distributed according to the
6 * terms of the GNU Public License, Version 2, incorporated
9 * Copyright 2004 Freescale Semiconductor.
10 * (C) Copyright 2003, Motorola, Inc.
22 #if defined(CONFIG_TSEC_ENET)
27 static uint rxIdx; /* index of the current RX buffer */
28 static uint txIdx; /* index of the current TX buffer */
30 typedef volatile struct rtxbd {
31 txbd8_t txbd[TX_BUF_CNT];
32 rxbd8_t rxbd[PKTBUFSRX];
35 struct tsec_info_struct {
38 unsigned int phyregidx;
42 /* The tsec_info structure contains 3 values which the
43 * driver uses to determine how to operate a given ethernet
44 * device. For now, the structure is initialized with the
45 * knowledge that all current implementations have 2 TSEC
46 * devices, and one FEC. The information needed is:
47 * phyaddr - The address of the PHY which is attached to
50 * flags - This variable indicates whether the device
51 * supports gigabit speed ethernet, and whether it should be
54 * phyregidx - This variable specifies which ethernet device
55 * controls the MII Management registers which are connected
56 * to the PHY. For 8540/8560, only TSEC1 (index 0) has
57 * access to the PHYs, so all of the entries have "0".
59 * The values specified in the table are taken from the board's
60 * config file in include/configs/. When implementing a new
61 * board with ethernet capability, it is necessary to define:
71 static struct tsec_info_struct tsec_info[] = {
72 #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
73 {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
77 #if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
78 {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
82 #ifdef CONFIG_MPC85XX_FEC
83 {FEC_PHY_ADDR, 0, FEC_PHYIDX},
85 # if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3)
86 {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
90 # if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4)
91 {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX},
98 #define MAXCONTROLLERS (4)
100 static int relocated = 0;
102 static struct tsec_private *privlist[MAXCONTROLLERS];
105 static RTXBD rtx __attribute__ ((aligned(8)));
107 #error "rtx must be 64-bit aligned"
110 static int tsec_send(struct eth_device* dev, volatile void *packet, int length);
111 static int tsec_recv(struct eth_device* dev);
112 static int tsec_init(struct eth_device* dev, bd_t * bd);
113 static void tsec_halt(struct eth_device* dev);
114 static void init_registers(volatile tsec_t *regs);
115 static void startup_tsec(struct eth_device *dev);
116 static int init_phy(struct eth_device *dev);
117 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
118 uint read_phy_reg(struct tsec_private *priv, uint regnum);
119 struct phy_info * get_phy_info(struct eth_device *dev);
120 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
121 static void adjust_link(struct eth_device *dev);
122 static void relocate_cmds(void);
124 /* Initialize device structure. Returns success if PHY
125 * initialization succeeded (i.e. if it recognizes the PHY)
127 int tsec_initialize(bd_t *bis, int index, char *devname)
129 struct eth_device* dev;
131 struct tsec_private *priv;
133 dev = (struct eth_device*) malloc(sizeof *dev);
138 memset(dev, 0, sizeof *dev);
140 priv = (struct tsec_private *) malloc(sizeof(*priv));
145 privlist[index] = priv;
146 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index*TSEC_SIZE);
147 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
148 tsec_info[index].phyregidx*TSEC_SIZE);
150 priv->phyaddr = tsec_info[index].phyaddr;
151 priv->flags = tsec_info[index].flags;
153 sprintf(dev->name, devname);
156 dev->init = tsec_init;
157 dev->halt = tsec_halt;
158 dev->send = tsec_send;
159 dev->recv = tsec_recv;
161 /* Tell u-boot to get the addr from the env */
163 dev->enetaddr[i] = 0;
169 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
170 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
172 /* Try to initialize PHY here, and return */
173 return init_phy(dev);
177 /* Initializes data structures and registers for the controller,
178 * and brings the interface up. Returns the link status, meaning
179 * that it returns success if the link is up, failure otherwise.
180 * This allows u-boot to find the first active controller. */
181 int tsec_init(struct eth_device* dev, bd_t * bd)
184 char tmpbuf[MAC_ADDR_LEN];
186 struct tsec_private *priv = (struct tsec_private *)dev->priv;
187 volatile tsec_t *regs = priv->regs;
189 /* Make sure the controller is stopped */
192 /* Init MACCFG2. Defaults to GMII */
193 regs->maccfg2 = MACCFG2_INIT_SETTINGS;
196 regs->ecntrl = ECNTRL_INIT_SETTINGS;
198 /* Copy the station address into the address registers.
199 * Backwards, because little endian MACS are dumb */
200 for(i=0;i<MAC_ADDR_LEN;i++) {
201 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
203 (uint)(regs->macstnaddr1) = *((uint *)(tmpbuf));
205 tempval = *((uint *)(tmpbuf +4));
207 (uint)(regs->macstnaddr2) = tempval;
209 /* reset the indices to zero */
213 /* Clear out (for the most part) the other registers */
214 init_registers(regs);
216 /* Ready the device for tx/rx */
219 /* If there's no link, fail */
225 /* Write value to the device's PHY through the registers
226 * specified in priv, modifying the register specified in regnum.
227 * It will wait for the write to be done (or for a timeout to
228 * expire) before exiting
230 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
232 volatile tsec_t *regbase = priv->phyregs;
233 uint phyid = priv->phyaddr;
236 regbase->miimadd = (phyid << 8) | regnum;
237 regbase->miimcon = value;
241 while((regbase->miimind & MIIMIND_BUSY) && timeout--);
245 /* Reads register regnum on the device's PHY through the
246 * registers specified in priv. It lowers and raises the read
247 * command, and waits for the data to become valid (miimind
248 * notvalid bit cleared), and the bus to cease activity (miimind
249 * busy bit cleared), and then returns the value
251 uint read_phy_reg(struct tsec_private *priv, uint regnum)
254 volatile tsec_t *regbase = priv->phyregs;
255 uint phyid = priv->phyaddr;
257 /* Put the address of the phy, and the register
258 * number into MIIMADD */
259 regbase->miimadd = (phyid << 8) | regnum;
261 /* Clear the command register, and wait */
262 regbase->miimcom = 0;
265 /* Initiate a read command, and wait */
266 regbase->miimcom = MIIM_READ_COMMAND;
269 /* Wait for the the indication that the read is done */
270 while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
272 /* Grab the value read from the PHY */
273 value = regbase->miimstat;
279 /* Discover which PHY is attached to the device, and configure it
280 * properly. If the PHY is not recognized, then return 0
281 * (failure). Otherwise, return 1
283 static int init_phy(struct eth_device *dev)
285 struct tsec_private *priv = (struct tsec_private *)dev->priv;
286 struct phy_info *curphy;
288 /* Assign a Physical address to the TBI */
291 volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
292 regs->tbipa = TBIPA_VALUE;
293 regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
294 regs->tbipa = TBIPA_VALUE;
298 /* Reset MII (due to new addresses) */
299 priv->phyregs->miimcfg = MIIMCFG_RESET;
301 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
303 while(priv->phyregs->miimind & MIIMIND_BUSY);
308 /* Get the cmd structure corresponding to the attached
310 curphy = get_phy_info(dev);
313 printf("%s: No PHY found\n", dev->name);
318 priv->phyinfo = curphy;
320 phy_run_commands(priv, priv->phyinfo->config);
326 /* Returns which value to write to the control register. */
327 /* For 10/100, the value is slightly different */
328 uint mii_cr_init(uint mii_reg, struct tsec_private *priv)
330 if(priv->flags & TSEC_GIGABIT)
331 return MIIM_CONTROL_INIT;
337 /* Parse the status register for link, and then do
338 * auto-negotiation */
339 uint mii_parse_sr(uint mii_reg, struct tsec_private *priv)
342 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
344 mii_reg = read_phy_reg(priv, MIIM_STATUS);
345 if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
348 puts ("Waiting for PHY auto negotiation to complete");
349 while (!((mii_reg & PHY_BMSR_AUTN_COMP) && (mii_reg & MIIM_STATUS_LINK))) {
353 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
354 puts (" TIMEOUT !\n");
359 if ((i++ % 1000) == 0) {
362 udelay (1000); /* 1 ms */
363 mii_reg = read_phy_reg(priv, MIIM_STATUS);
367 udelay (500000); /* another 500 ms (results in faster booting) */
376 /* Parse the 88E1011's status register for speed and duplex
378 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv)
382 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
384 if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
385 (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
388 puts ("Waiting for PHY realtime link");
389 while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
390 (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
394 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
395 puts (" TIMEOUT !\n");
400 if ((i++ % 1000) == 0) {
403 udelay (1000); /* 1 ms */
404 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
407 udelay (500000); /* another 500 ms (results in faster booting) */
410 if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
415 speed = (mii_reg &MIIM_88E1011_PHYSTAT_SPEED);
418 case MIIM_88E1011_PHYSTAT_GBIT:
421 case MIIM_88E1011_PHYSTAT_100:
432 /* Parse the cis8201's status register for speed and duplex
434 uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv)
438 if(mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
443 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
445 case MIIM_CIS8201_AUXCONSTAT_GBIT:
448 case MIIM_CIS8201_AUXCONSTAT_100:
460 /* Parse the DM9161's status register for speed and duplex
462 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv)
464 if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
469 if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
478 /* Hack to write all 4 PHYs with the LED values */
479 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv)
482 volatile tsec_t *regbase = priv->phyregs;
485 for(phyid=0;phyid<4;phyid++) {
486 regbase->miimadd = (phyid << 8) | mii_reg;
487 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
491 while((regbase->miimind & MIIMIND_BUSY) && timeout--);
494 return MIIM_CIS8204_SLEDCON_INIT;
497 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private *priv)
499 if (priv->flags & TSEC_REDUCED)
500 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
502 return MIIM_CIS8204_EPHYCON_INIT;
505 /* Initialized required registers to appropriate values, zeroing
506 * those we don't care about (unless zero is bad, in which case,
507 * choose a more appropriate value) */
508 static void init_registers(volatile tsec_t *regs)
511 regs->ievent = IEVENT_INIT_CLEAR;
513 regs->imask = IMASK_INIT_CLEAR;
515 regs->hash.iaddr0 = 0;
516 regs->hash.iaddr1 = 0;
517 regs->hash.iaddr2 = 0;
518 regs->hash.iaddr3 = 0;
519 regs->hash.iaddr4 = 0;
520 regs->hash.iaddr5 = 0;
521 regs->hash.iaddr6 = 0;
522 regs->hash.iaddr7 = 0;
524 regs->hash.gaddr0 = 0;
525 regs->hash.gaddr1 = 0;
526 regs->hash.gaddr2 = 0;
527 regs->hash.gaddr3 = 0;
528 regs->hash.gaddr4 = 0;
529 regs->hash.gaddr5 = 0;
530 regs->hash.gaddr6 = 0;
531 regs->hash.gaddr7 = 0;
533 regs->rctrl = 0x00000000;
535 /* Init RMON mib registers */
536 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
538 regs->rmon.cam1 = 0xffffffff;
539 regs->rmon.cam2 = 0xffffffff;
541 regs->mrblr = MRBLR_INIT_SETTINGS;
543 regs->minflr = MINFLR_INIT_SETTINGS;
545 regs->attr = ATTR_INIT_SETTINGS;
546 regs->attreli = ATTRELI_INIT_SETTINGS;
551 /* Configure maccfg2 based on negotiated speed and duplex
552 * reported by PHY handling code */
553 static void adjust_link(struct eth_device *dev)
555 struct tsec_private *priv = (struct tsec_private *)dev->priv;
556 volatile tsec_t *regs = priv->regs;
559 if(priv->duplexity != 0)
560 regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
562 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
564 switch(priv->speed) {
566 regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
571 regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
574 /* If We're in reduced mode, we need
575 * to say whether we're 10 or 100 MB.
577 if ((priv->speed == 100)
578 && (priv->flags & TSEC_REDUCED))
579 regs->ecntrl |= ECNTRL_R100;
581 regs->ecntrl &= ~(ECNTRL_R100);
584 printf("%s: Speed was bad\n", dev->name);
588 printf("Speed: %d, %s duplex\n", priv->speed,
589 (priv->duplexity) ? "full" : "half");
592 printf("%s: No link.\n", dev->name);
597 /* Set up the buffers and their descriptors, and bring up the
599 static void startup_tsec(struct eth_device *dev)
602 struct tsec_private *priv = (struct tsec_private *)dev->priv;
603 volatile tsec_t *regs = priv->regs;
605 /* Point to the buffer descriptors */
606 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
607 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
609 /* Initialize the Rx Buffer descriptors */
610 for (i = 0; i < PKTBUFSRX; i++) {
611 rtx.rxbd[i].status = RXBD_EMPTY;
612 rtx.rxbd[i].length = 0;
613 rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i];
615 rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP;
617 /* Initialize the TX Buffer Descriptors */
618 for(i=0; i<TX_BUF_CNT; i++) {
619 rtx.txbd[i].status = 0;
620 rtx.txbd[i].length = 0;
621 rtx.txbd[i].bufPtr = 0;
623 rtx.txbd[TX_BUF_CNT -1].status |= TXBD_WRAP;
625 /* Start up the PHY */
626 phy_run_commands(priv, priv->phyinfo->startup);
629 /* Enable Transmit and Receive */
630 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
632 /* Tell the DMA it is clear to go */
633 regs->dmactrl |= DMACTRL_INIT_SETTINGS;
634 regs->tstat = TSTAT_CLEAR_THALT;
635 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
638 /* This returns the status bits of the device. The return value
639 * is never checked, and this is what the 8260 driver did, so we
640 * do the same. Presumably, this would be zero if there were no
642 static int tsec_send(struct eth_device* dev, volatile void *packet, int length)
646 struct tsec_private *priv = (struct tsec_private *)dev->priv;
647 volatile tsec_t *regs = priv->regs;
649 /* Find an empty buffer descriptor */
650 for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
651 if (i >= TOUT_LOOP) {
652 debug ("%s: tsec: tx buffers full\n", dev->name);
657 rtx.txbd[txIdx].bufPtr = (uint)packet;
658 rtx.txbd[txIdx].length = length;
659 rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
661 /* Tell the DMA to go */
662 regs->tstat = TSTAT_CLEAR_THALT;
664 /* Wait for buffer to be transmitted */
665 for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
666 if (i >= TOUT_LOOP) {
667 debug ("%s: tsec: tx error\n", dev->name);
672 txIdx = (txIdx + 1) % TX_BUF_CNT;
673 result = rtx.txbd[txIdx].status & TXBD_STATS;
678 static int tsec_recv(struct eth_device* dev)
681 struct tsec_private *priv = (struct tsec_private *)dev->priv;
682 volatile tsec_t *regs = priv->regs;
684 while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
686 length = rtx.rxbd[rxIdx].length;
688 /* Send the packet up if there were no errors */
689 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
690 NetReceive(NetRxPackets[rxIdx], length - 4);
692 printf("Got error %x\n",
693 (rtx.rxbd[rxIdx].status & RXBD_STATS));
696 rtx.rxbd[rxIdx].length = 0;
698 /* Set the wrap bit if this is the last element in the list */
699 rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
701 rxIdx = (rxIdx + 1) % PKTBUFSRX;
704 if(regs->ievent&IEVENT_BSY) {
705 regs->ievent = IEVENT_BSY;
706 regs->rstat = RSTAT_CLEAR_RHALT;
714 /* Stop the interface */
715 static void tsec_halt(struct eth_device* dev)
717 struct tsec_private *priv = (struct tsec_private *)dev->priv;
718 volatile tsec_t *regs = priv->regs;
720 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
721 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
723 while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)));
725 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
727 /* Shut down the PHY, as needed */
728 phy_run_commands(priv, priv->phyinfo->shutdown);
732 struct phy_info phy_info_M88E1011S = {
736 (struct phy_cmd[]) { /* config */
737 /* Reset and configure the PHY */
738 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
740 {0x1e, 0x200c, NULL},
744 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
745 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
746 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
747 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
750 (struct phy_cmd[]) { /* startup */
751 /* Status is read once to clear old link state */
752 {MIIM_STATUS, miim_read, NULL},
754 {MIIM_STATUS, miim_read, &mii_parse_sr},
755 /* Read the status */
756 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
759 (struct phy_cmd[]) { /* shutdown */
764 struct phy_info phy_info_M88E1111S = {
768 (struct phy_cmd[]) { /* config */
769 /* Reset and configure the PHY */
770 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
772 {0x1e, 0x200c, NULL},
776 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
777 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
778 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
779 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
782 (struct phy_cmd[]) { /* startup */
783 /* Status is read once to clear old link state */
784 {MIIM_STATUS, miim_read, NULL},
786 {MIIM_STATUS, miim_read, &mii_parse_sr},
787 /* Read the status */
788 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
791 (struct phy_cmd[]) { /* shutdown */
796 struct phy_info phy_info_cis8204 = {
800 (struct phy_cmd[]) { /* config */
801 /* Override PHY config settings */
802 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
803 /* Configure some basic stuff */
804 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
805 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled},
806 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, &mii_cis8204_setmode},
809 (struct phy_cmd[]) { /* startup */
810 /* Read the Status (2x to make sure link is right) */
811 {MIIM_STATUS, miim_read, NULL},
813 {MIIM_STATUS, miim_read, &mii_parse_sr},
814 /* Read the status */
815 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
818 (struct phy_cmd[]) { /* shutdown */
824 struct phy_info phy_info_cis8201 = {
828 (struct phy_cmd[]) { /* config */
829 /* Override PHY config settings */
830 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
831 /* Set up the interface mode */
832 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
833 /* Configure some basic stuff */
834 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
837 (struct phy_cmd[]) { /* startup */
838 /* Read the Status (2x to make sure link is right) */
839 {MIIM_STATUS, miim_read, NULL},
841 {MIIM_STATUS, miim_read, &mii_parse_sr},
842 /* Read the status */
843 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
846 (struct phy_cmd[]) { /* shutdown */
852 struct phy_info phy_info_dm9161 = {
856 (struct phy_cmd[]) { /* config */
857 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
858 /* Do not bypass the scrambler/descrambler */
859 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
860 /* Clear 10BTCSR to default */
861 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL},
862 /* Configure some basic stuff */
863 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
864 /* Restart Auto Negotiation */
865 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
868 (struct phy_cmd[]) { /* startup */
869 /* Status is read once to clear old link state */
870 {MIIM_STATUS, miim_read, NULL},
872 {MIIM_STATUS, miim_read, &mii_parse_sr},
873 /* Read the status */
874 {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr},
877 (struct phy_cmd[]) { /* shutdown */
882 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
886 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
889 case MIIM_LXT971_SR2_10HDX:
893 case MIIM_LXT971_SR2_10FDX:
897 case MIIM_LXT971_SR2_100HDX:
913 static struct phy_info phy_info_lxt971 = {
917 (struct phy_cmd []) { /* config */
918 { MIIM_CR, MIIM_CR_INIT, mii_cr_init }, /* autonegotiate */
921 (struct phy_cmd []) { /* startup - enable interrupts */
922 /* { 0x12, 0x00f2, NULL }, */
923 { MIIM_STATUS, miim_read, NULL },
924 { MIIM_STATUS, miim_read, &mii_parse_sr },
925 { MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2 },
928 (struct phy_cmd []) { /* shutdown - disable interrupts */
933 struct phy_info *phy_info[] = {
946 /* Grab the identifier of the device's PHY, and search through
947 * all of the known PHYs to see if one matches. If so, return
948 * it, if not, return NULL */
949 struct phy_info * get_phy_info(struct eth_device *dev)
951 struct tsec_private *priv = (struct tsec_private *)dev->priv;
952 uint phy_reg, phy_ID;
954 struct phy_info *theInfo = NULL;
956 /* Grab the bits from PHYIR1, and put them in the upper half */
957 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
958 phy_ID = (phy_reg & 0xffff) << 16;
960 /* Grab the bits from PHYIR2, and put them in the lower half */
961 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
962 phy_ID |= (phy_reg & 0xffff);
964 /* loop through all the known PHY types, and find one that */
965 /* matches the ID we read from the PHY. */
966 for(i=0; phy_info[i]; i++) {
967 if(phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
968 theInfo = phy_info[i];
973 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
976 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
983 /* Execute the given series of commands on the given device's
984 * PHY, running functions as necessary*/
985 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
989 volatile tsec_t *phyregs = priv->phyregs;
991 phyregs->miimcfg = MIIMCFG_RESET;
993 phyregs->miimcfg = MIIMCFG_INIT_VALUE;
995 while(phyregs->miimind & MIIMIND_BUSY);
997 for(i=0;cmd->mii_reg != miim_end;i++) {
998 if(cmd->mii_data == miim_read) {
999 result = read_phy_reg(priv, cmd->mii_reg);
1001 if(cmd->funct != NULL)
1002 (*(cmd->funct))(result, priv);
1005 if(cmd->funct != NULL)
1006 result = (*(cmd->funct))(cmd->mii_reg, priv);
1008 result = cmd->mii_data;
1010 write_phy_reg(priv, cmd->mii_reg, result);
1018 /* Relocate the function pointers in the phy cmd lists */
1019 static void relocate_cmds(void)
1021 struct phy_cmd **cmdlistptr;
1022 struct phy_cmd *cmd;
1024 DECLARE_GLOBAL_DATA_PTR;
1026 for(i=0; phy_info[i]; i++) {
1027 /* First thing's first: relocate the pointers to the
1028 * PHY command structures (the structs were done) */
1029 phy_info[i] = (struct phy_info *) ((uint)phy_info[i]
1031 phy_info[i]->name += gd->reloc_off;
1032 phy_info[i]->config =
1033 (struct phy_cmd *)((uint)phy_info[i]->config
1035 phy_info[i]->startup =
1036 (struct phy_cmd *)((uint)phy_info[i]->startup
1038 phy_info[i]->shutdown =
1039 (struct phy_cmd *)((uint)phy_info[i]->shutdown
1042 cmdlistptr = &phy_info[i]->config;
1044 for(;cmdlistptr <= &phy_info[i]->shutdown;cmdlistptr++) {
1046 for(cmd=*cmdlistptr;cmd->mii_reg != miim_end;cmd++) {
1047 /* Only relocate non-NULL pointers */
1049 cmd->funct += gd->reloc_off;
1061 #ifndef CONFIG_BITBANGMII
1063 struct tsec_private * get_priv_for_phy(unsigned char phyaddr)
1067 for(i=0;i<MAXCONTROLLERS;i++) {
1068 if(privlist[i]->phyaddr == phyaddr)
1076 * Read a MII PHY register.
1081 int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
1084 struct tsec_private *priv = get_priv_for_phy(addr);
1087 printf("Can't read PHY at address %d\n", addr);
1091 ret = (unsigned short)read_phy_reg(priv, reg);
1098 * Write a MII PHY register.
1103 int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
1105 struct tsec_private *priv = get_priv_for_phy(addr);
1108 printf("Can't write PHY at address %d\n", addr);
1112 write_phy_reg(priv, reg, value);
1117 #endif /* CONFIG_BITBANGMII */
1119 #endif /* CONFIG_TSEC_ENET */