drivers/tsec.c

   1 /*
   2  * Freescale Three Speed Ethernet Controller driver
   3  *
   4  * This software may be used and distributed according to the
   5  * terms of the GNU Public License, Version 2, incorporated
   6  * herein by reference.
   7  *
   8  * Copyright 2004, 2007 Freescale Semiconductor, Inc.
   9  * (C) Copyright 2003, Motorola, Inc.
  10  * author Andy Fleming
  11  *
  12  */
  13
  14 #include <config.h>
  15 #include <common.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <command.h>
  19
  20 #if defined(CONFIG_TSEC_ENET)
  21 #include "tsec.h"
  22 #include "miiphy.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define TX_BUF_CNT              2
  27
  28 static uint rxIdx;              /* index of the current RX buffer */
  29 static uint txIdx;              /* index of the current TX buffer */
  30
  31 typedef volatile struct rtxbd {
  32         txbd8_t txbd[TX_BUF_CNT];
  33         rxbd8_t rxbd[PKTBUFSRX];
  34 } RTXBD;
  35
  36 struct tsec_info_struct {
  37         unsigned int phyaddr;
  38         u32 flags;
  39         unsigned int phyregidx;
  40 };
  41
  42 /* The tsec_info structure contains 3 values which the
  43  * driver uses to determine how to operate a given ethernet
  44  * device. The information needed is:
  45  *  phyaddr - The address of the PHY which is attached to
  46  *      the given device.
  47  *
  48  *  flags - This variable indicates whether the device
  49  *      supports gigabit speed ethernet, and whether it should be
  50  *      in reduced mode.
  51  *
  52  *  phyregidx - This variable specifies which ethernet device
  53  *      controls the MII Management registers which are connected
  54  *      to the PHY.  For now, only TSEC1 (index 0) has
  55  *      access to the PHYs, so all of the entries have "0".
  56  *
  57  * The values specified in the table are taken from the board's
  58  * config file in include/configs/.  When implementing a new
  59  * board with ethernet capability, it is necessary to define:
  60  *   TSECn_PHY_ADDR
  61  *   TSECn_PHYIDX
  62  *
  63  * for n = 1,2,3, etc.  And for FEC:
  64  *   FEC_PHY_ADDR
  65  *   FEC_PHYIDX
  66  */
  67 static struct tsec_info_struct tsec_info[] = {
  68 #ifdef CONFIG_TSEC1
  69         {TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX},
  70 #else
  71         {0, 0, 0},
  72 #endif
  73 #ifdef CONFIG_TSEC2
  74         {TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX},
  75 #else
  76         {0, 0, 0},
  77 #endif
  78 #ifdef CONFIG_MPC85XX_FEC
  79         {FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX},
  80 #else
  81 #ifdef CONFIG_TSEC3
  82         {TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX},
  83 #else
  84         {0, 0, 0},
  85 #endif
  86 #ifdef CONFIG_TSEC4
  87         {TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX},
  88 #else
  89         {0, 0, 0},
  90 #endif  /* CONFIG_TSEC4 */
  91 #endif  /* CONFIG_MPC85XX_FEC */
  92 };
  93
  94 #define MAXCONTROLLERS  (4)
  95
  96 static int relocated = 0;
  97
  98 static struct tsec_private *privlist[MAXCONTROLLERS];
  99
 100 #ifdef __GNUC__
 101 static RTXBD rtx __attribute__ ((aligned(8)));
 102 #else
 103 #error "rtx must be 64-bit aligned"
 104 #endif
 105
 106 static int tsec_send(struct eth_device *dev,
 107                      volatile void *packet, int length);
 108 static int tsec_recv(struct eth_device *dev);
 109 static int tsec_init(struct eth_device *dev, bd_t * bd);
 110 static void tsec_halt(struct eth_device *dev);
 111 static void init_registers(volatile tsec_t * regs);
 112 static void startup_tsec(struct eth_device *dev);
 113 static int init_phy(struct eth_device *dev);
 114 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
 115 uint read_phy_reg(struct tsec_private *priv, uint regnum);
 116 struct phy_info *get_phy_info(struct eth_device *dev);
 117 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
 118 static void adjust_link(struct eth_device *dev);
 119 static void relocate_cmds(void);
 120 static int tsec_miiphy_write(char *devname, unsigned char addr,
 121                              unsigned char reg, unsigned short value);
 122 static int tsec_miiphy_read(char *devname, unsigned char addr,
 123                             unsigned char reg, unsigned short *value);
 124 #ifdef CONFIG_MCAST_TFTP
 125 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
 126 #endif
 127
 128 /* Initialize device structure. Returns success if PHY
 129  * initialization succeeded (i.e. if it recognizes the PHY)
 130  */
 131 int tsec_initialize(bd_t * bis, int index, char *devname)
 132 {
 133         struct eth_device *dev;
 134         int i;
 135         struct tsec_private *priv;
 136
 137         dev = (struct eth_device *)malloc(sizeof *dev);
 138
 139         if (NULL == dev)
 140                 return 0;
 141
 142         memset(dev, 0, sizeof *dev);
 143
 144         priv = (struct tsec_private *)malloc(sizeof(*priv));
 145
 146         if (NULL == priv)
 147                 return 0;
 148
 149         privlist[index] = priv;
 150         priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
 151         priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
 152                                             tsec_info[index].phyregidx *
 153                                             TSEC_SIZE);
 154
 155         priv->phyaddr = tsec_info[index].phyaddr;
 156         priv->flags = tsec_info[index].flags;
 157
 158         sprintf(dev->name, devname);
 159         dev->iobase = 0;
 160         dev->priv = priv;
 161         dev->init = tsec_init;
 162         dev->halt = tsec_halt;
 163         dev->send = tsec_send;
 164         dev->recv = tsec_recv;
 165 #ifdef CONFIG_MCAST_TFTP
 166         dev->mcast = tsec_mcast_addr;
 167 #endif
 168
 169         /* Tell u-boot to get the addr from the env */
 170         for (i = 0; i < 6; i++)
 171                 dev->enetaddr[i] = 0;
 172
 173         eth_register(dev);
 174
 175         /* Reset the MAC */
 176         priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
 177         priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
 178
 179 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
 180         && !defined(BITBANGMII)
 181         miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
 182 #endif
 183
 184         /* Try to initialize PHY here, and return */
 185         return init_phy(dev);
 186 }
 187
 188 /* Initializes data structures and registers for the controller,
 189  * and brings the interface up.  Returns the link status, meaning
 190  * that it returns success if the link is up, failure otherwise.
 191  * This allows u-boot to find the first active controller.
 192  */
 193 int tsec_init(struct eth_device *dev, bd_t * bd)
 194 {
 195         uint tempval;
 196         char tmpbuf[MAC_ADDR_LEN];
 197         int i;
 198         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 199         volatile tsec_t *regs = priv->regs;
 200
 201         /* Make sure the controller is stopped */
 202         tsec_halt(dev);
 203
 204         /* Init MACCFG2.  Defaults to GMII */
 205         regs->maccfg2 = MACCFG2_INIT_SETTINGS;
 206
 207         /* Init ECNTRL */
 208         regs->ecntrl = ECNTRL_INIT_SETTINGS;
 209
 210         /* Copy the station address into the address registers.
 211          * Backwards, because little endian MACS are dumb */
 212         for (i = 0; i < MAC_ADDR_LEN; i++) {
 213                 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
 214         }
 215         regs->macstnaddr1 = *((uint *) (tmpbuf));
 216
 217         tempval = *((uint *) (tmpbuf + 4));
 218
 219         regs->macstnaddr2 = tempval;
 220
 221         /* reset the indices to zero */
 222         rxIdx = 0;
 223         txIdx = 0;
 224
 225         /* Clear out (for the most part) the other registers */
 226         init_registers(regs);
 227
 228         /* Ready the device for tx/rx */
 229         startup_tsec(dev);
 230
 231         /* If there's no link, fail */
 232         return priv->link;
 233
 234 }
 235
 236 /* Write value to the device's PHY through the registers
 237  * specified in priv, modifying the register specified in regnum.
 238  * It will wait for the write to be done (or for a timeout to
 239  * expire) before exiting
 240  */
 241 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
 242 {
 243         volatile tsec_t *regbase = priv->phyregs;
 244         uint phyid = priv->phyaddr;
 245         int timeout = 1000000;
 246
 247         regbase->miimadd = (phyid << 8) | regnum;
 248         regbase->miimcon = value;
 249         asm("sync");
 250
 251         timeout = 1000000;
 252         while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
 253 }
 254
 255 /* Reads register regnum on the device's PHY through the
 256  * registers specified in priv.  It lowers and raises the read
 257  * command, and waits for the data to become valid (miimind
 258  * notvalid bit cleared), and the bus to cease activity (miimind
 259  * busy bit cleared), and then returns the value
 260  */
 261 uint read_phy_reg(struct tsec_private *priv, uint regnum)
 262 {
 263         uint value;
 264         volatile tsec_t *regbase = priv->phyregs;
 265         uint phyid = priv->phyaddr;
 266
 267         /* Put the address of the phy, and the register
 268          * number into MIIMADD */
 269         regbase->miimadd = (phyid << 8) | regnum;
 270
 271         /* Clear the command register, and wait */
 272         regbase->miimcom = 0;
 273         asm("sync");
 274
 275         /* Initiate a read command, and wait */
 276         regbase->miimcom = MIIM_READ_COMMAND;
 277         asm("sync");
 278
 279         /* Wait for the the indication that the read is done */
 280         while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
 281
 282         /* Grab the value read from the PHY */
 283         value = regbase->miimstat;
 284
 285         return value;
 286 }
 287
 288 /* Discover which PHY is attached to the device, and configure it
 289  * properly.  If the PHY is not recognized, then return 0
 290  * (failure).  Otherwise, return 1
 291  */
 292 static int init_phy(struct eth_device *dev)
 293 {
 294         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 295         struct phy_info *curphy;
 296         volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
 297
 298         /* Assign a Physical address to the TBI */
 299         regs->tbipa = CFG_TBIPA_VALUE;
 300         regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
 301         regs->tbipa = CFG_TBIPA_VALUE;
 302         asm("sync");
 303
 304         /* Reset MII (due to new addresses) */
 305         priv->phyregs->miimcfg = MIIMCFG_RESET;
 306         asm("sync");
 307         priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
 308         asm("sync");
 309         while (priv->phyregs->miimind & MIIMIND_BUSY) ;
 310
 311         if (0 == relocated)
 312                 relocate_cmds();
 313
 314         /* Get the cmd structure corresponding to the attached
 315          * PHY */
 316         curphy = get_phy_info(dev);
 317
 318         if (curphy == NULL) {
 319                 priv->phyinfo = NULL;
 320                 printf("%s: No PHY found\n", dev->name);
 321
 322                 return 0;
 323         }
 324
 325         priv->phyinfo = curphy;
 326
 327         phy_run_commands(priv, priv->phyinfo->config);
 328
 329         return 1;
 330 }
 331
 332 /*
 333  * Returns which value to write to the control register.
 334  * For 10/100, the value is slightly different
 335  */
 336 uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
 337 {
 338         if (priv->flags & TSEC_GIGABIT)
 339                 return MIIM_CONTROL_INIT;
 340         else
 341                 return MIIM_CR_INIT;
 342 }
 343
 344 /* Parse the status register for link, and then do
 345  * auto-negotiation
 346  */
 347 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
 348 {
 349         /*
 350          * Wait if the link is up, and autonegotiation is in progress
 351          * (ie - we're capable and it's not done)
 352          */
 353         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 354         if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE)
 355             && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
 356                 int i = 0;
 357
 358                 puts("Waiting for PHY auto negotiation to complete");
 359                 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) {
 360                         /*
 361                          * Timeout reached ?
 362                          */
 363                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 364                                 puts(" TIMEOUT !\n");
 365                                 priv->link = 0;
 366                                 return 0;
 367                         }
 368
 369                         if ((i++ % 1000) == 0) {
 370                                 putc('.');
 371                         }
 372                         udelay(1000);   /* 1 ms */
 373                         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 374                 }
 375                 puts(" done\n");
 376                 priv->link = 1;
 377                 udelay(500000); /* another 500 ms (results in faster booting) */
 378         } else {
 379                 if (mii_reg & MIIM_STATUS_LINK)
 380                         priv->link = 1;
 381                 else
 382                         priv->link = 0;
 383         }
 384
 385         return 0;
 386 }
 387
 388 /* Generic function which updates the speed and duplex.  If
 389  * autonegotiation is enabled, it uses the AND of the link
 390  * partner's advertised capabilities and our advertised
 391  * capabilities.  If autonegotiation is disabled, we use the
 392  * appropriate bits in the control register.
 393  *
 394  * Stolen from Linux's mii.c and phy_device.c
 395  */
 396 uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
 397 {
 398         /* We're using autonegotiation */
 399         if (mii_reg & PHY_BMSR_AUTN_ABLE) {
 400                 uint lpa = 0;
 401                 uint gblpa = 0;
 402
 403                 /* Check for gigabit capability */
 404                 if (mii_reg & PHY_BMSR_EXT) {
 405                         /* We want a list of states supported by
 406                          * both PHYs in the link
 407                          */
 408                         gblpa = read_phy_reg(priv, PHY_1000BTSR);
 409                         gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
 410                 }
 411
 412                 /* Set the baseline so we only have to set them
 413                  * if they're different
 414                  */
 415                 priv->speed = 10;
 416                 priv->duplexity = 0;
 417
 418                 /* Check the gigabit fields */
 419                 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
 420                         priv->speed = 1000;
 421
 422                         if (gblpa & PHY_1000BTSR_1000FD)
 423                                 priv->duplexity = 1;
 424
 425                         /* We're done! */
 426                         return 0;
 427                 }
 428
 429                 lpa = read_phy_reg(priv, PHY_ANAR);
 430                 lpa &= read_phy_reg(priv, PHY_ANLPAR);
 431
 432                 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
 433                         priv->speed = 100;
 434
 435                         if (lpa & PHY_ANLPAR_TXFD)
 436                                 priv->duplexity = 1;
 437
 438                 } else if (lpa & PHY_ANLPAR_10FD)
 439                         priv->duplexity = 1;
 440         } else {
 441                 uint bmcr = read_phy_reg(priv, PHY_BMCR);
 442
 443                 priv->speed = 10;
 444                 priv->duplexity = 0;
 445
 446                 if (bmcr & PHY_BMCR_DPLX)
 447                         priv->duplexity = 1;
 448
 449                 if (bmcr & PHY_BMCR_1000_MBPS)
 450                         priv->speed = 1000;
 451                 else if (bmcr & PHY_BMCR_100_MBPS)
 452                         priv->speed = 100;
 453         }
 454
 455         return 0;
 456 }
 457
 458 /*
 459  * Parse the BCM54xx status register for speed and duplex information.
 460  * The linux sungem_phy has this information, but in a table format.
 461  */
 462 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
 463 {
 464
 465         switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){
 466
 467                 case 1:
 468                         printf("Enet starting in 10BT/HD\n");
 469                         priv->duplexity = 0;
 470                         priv->speed = 10;
 471                         break;
 472
 473                 case 2:
 474                         printf("Enet starting in 10BT/FD\n");
 475                         priv->duplexity = 1;
 476                         priv->speed = 10;
 477                         break;
 478
 479                 case 3:
 480                         printf("Enet starting in 100BT/HD\n");
 481                         priv->duplexity = 0;
 482                         priv->speed = 100;
 483                         break;
 484
 485                 case 5:
 486                         printf("Enet starting in 100BT/FD\n");
 487                         priv->duplexity = 1;
 488                         priv->speed = 100;
 489                         break;
 490
 491                 case 6:
 492                         printf("Enet starting in 1000BT/HD\n");
 493                         priv->duplexity = 0;
 494                         priv->speed = 1000;
 495                         break;
 496
 497                 case 7:
 498                         printf("Enet starting in 1000BT/FD\n");
 499                         priv->duplexity = 1;
 500                         priv->speed = 1000;
 501                         break;
 502
 503                 default:
 504                         printf("Auto-neg error, defaulting to 10BT/HD\n");
 505                         priv->duplexity = 0;
 506                         priv->speed = 10;
 507                         break;
 508         }
 509
 510         return 0;
 511
 512 }
 513 /* Parse the 88E1011's status register for speed and duplex
 514  * information
 515  */
 516 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
 517 {
 518         uint speed;
 519
 520         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 521
 522         if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
 523                 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
 524                 int i = 0;
 525
 526                 puts("Waiting for PHY realtime link");
 527                 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
 528                         /* Timeout reached ? */
 529                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 530                                 puts(" TIMEOUT !\n");
 531                                 priv->link = 0;
 532                                 break;
 533                         }
 534
 535                         if ((i++ % 1000) == 0) {
 536                                 putc('.');
 537                         }
 538                         udelay(1000);   /* 1 ms */
 539                         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 540                 }
 541                 puts(" done\n");
 542                 udelay(500000); /* another 500 ms (results in faster booting) */
 543         } else {
 544                 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
 545                         priv->link = 1;
 546                 else
 547                         priv->link = 0;
 548         }
 549
 550         if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
 551                 priv->duplexity = 1;
 552         else
 553                 priv->duplexity = 0;
 554
 555         speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
 556
 557         switch (speed) {
 558         case MIIM_88E1011_PHYSTAT_GBIT:
 559                 priv->speed = 1000;
 560                 break;
 561         case MIIM_88E1011_PHYSTAT_100:
 562                 priv->speed = 100;
 563                 break;
 564         default:
 565                 priv->speed = 10;
 566         }
 567
 568         return 0;
 569 }
 570
 571 /* Parse the cis8201's status register for speed and duplex
 572  * information
 573  */
 574 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
 575 {
 576         uint speed;
 577
 578         if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
 579                 priv->duplexity = 1;
 580         else
 581                 priv->duplexity = 0;
 582
 583         speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
 584         switch (speed) {
 585         case MIIM_CIS8201_AUXCONSTAT_GBIT:
 586                 priv->speed = 1000;
 587                 break;
 588         case MIIM_CIS8201_AUXCONSTAT_100:
 589                 priv->speed = 100;
 590                 break;
 591         default:
 592                 priv->speed = 10;
 593                 break;
 594         }
 595
 596         return 0;
 597 }
 598
 599 /* Parse the vsc8244's status register for speed and duplex
 600  * information
 601  */
 602 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
 603 {
 604         uint speed;
 605
 606         if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
 607                 priv->duplexity = 1;
 608         else
 609                 priv->duplexity = 0;
 610
 611         speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
 612         switch (speed) {
 613         case MIIM_VSC8244_AUXCONSTAT_GBIT:
 614                 priv->speed = 1000;
 615                 break;
 616         case MIIM_VSC8244_AUXCONSTAT_100:
 617                 priv->speed = 100;
 618                 break;
 619         default:
 620                 priv->speed = 10;
 621                 break;
 622         }
 623
 624         return 0;
 625 }
 626
 627 /* Parse the DM9161's status register for speed and duplex
 628  * information
 629  */
 630 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
 631 {
 632         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
 633                 priv->speed = 100;
 634         else
 635                 priv->speed = 10;
 636
 637         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
 638                 priv->duplexity = 1;
 639         else
 640                 priv->duplexity = 0;
 641
 642         return 0;
 643 }
 644
 645 /*
 646  * Hack to write all 4 PHYs with the LED values
 647  */
 648 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
 649 {
 650         uint phyid;
 651         volatile tsec_t *regbase = priv->phyregs;
 652         int timeout = 1000000;
 653
 654         for (phyid = 0; phyid < 4; phyid++) {
 655                 regbase->miimadd = (phyid << 8) | mii_reg;
 656                 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
 657                 asm("sync");
 658
 659                 timeout = 1000000;
 660                 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
 661         }
 662
 663         return MIIM_CIS8204_SLEDCON_INIT;
 664 }
 665
 666 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
 667 {
 668         if (priv->flags & TSEC_REDUCED)
 669                 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
 670         else
 671                 return MIIM_CIS8204_EPHYCON_INIT;
 672 }
 673
 674 /* Initialized required registers to appropriate values, zeroing
 675  * those we don't care about (unless zero is bad, in which case,
 676  * choose a more appropriate value)
 677  */
 678 static void init_registers(volatile tsec_t * regs)
 679 {
 680         /* Clear IEVENT */
 681         regs->ievent = IEVENT_INIT_CLEAR;
 682
 683         regs->imask = IMASK_INIT_CLEAR;
 684
 685         regs->hash.iaddr0 = 0;
 686         regs->hash.iaddr1 = 0;
 687         regs->hash.iaddr2 = 0;
 688         regs->hash.iaddr3 = 0;
 689         regs->hash.iaddr4 = 0;
 690         regs->hash.iaddr5 = 0;
 691         regs->hash.iaddr6 = 0;
 692         regs->hash.iaddr7 = 0;
 693
 694         regs->hash.gaddr0 = 0;
 695         regs->hash.gaddr1 = 0;
 696         regs->hash.gaddr2 = 0;
 697         regs->hash.gaddr3 = 0;
 698         regs->hash.gaddr4 = 0;
 699         regs->hash.gaddr5 = 0;
 700         regs->hash.gaddr6 = 0;
 701         regs->hash.gaddr7 = 0;
 702
 703         regs->rctrl = 0x00000000;
 704
 705         /* Init RMON mib registers */
 706         memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
 707
 708         regs->rmon.cam1 = 0xffffffff;
 709         regs->rmon.cam2 = 0xffffffff;
 710
 711         regs->mrblr = MRBLR_INIT_SETTINGS;
 712
 713         regs->minflr = MINFLR_INIT_SETTINGS;
 714
 715         regs->attr = ATTR_INIT_SETTINGS;
 716         regs->attreli = ATTRELI_INIT_SETTINGS;
 717
 718 }
 719
 720 /* Configure maccfg2 based on negotiated speed and duplex
 721  * reported by PHY handling code
 722  */
 723 static void adjust_link(struct eth_device *dev)
 724 {
 725         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 726         volatile tsec_t *regs = priv->regs;
 727
 728         if (priv->link) {
 729                 if (priv->duplexity != 0)
 730                         regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
 731                 else
 732                         regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
 733
 734                 switch (priv->speed) {
 735                 case 1000:
 736                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 737                                          | MACCFG2_GMII);
 738                         break;
 739                 case 100:
 740                 case 10:
 741                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 742                                          | MACCFG2_MII);
 743
 744                         /* Set R100 bit in all modes although
 745                          * it is only used in RGMII mode
 746                          */
 747                         if (priv->speed == 100)
 748                                 regs->ecntrl |= ECNTRL_R100;
 749                         else
 750                                 regs->ecntrl &= ~(ECNTRL_R100);
 751                         break;
 752                 default:
 753                         printf("%s: Speed was bad\n", dev->name);
 754                         break;
 755                 }
 756
 757                 printf("Speed: %d, %s duplex\n", priv->speed,
 758                        (priv->duplexity) ? "full" : "half");
 759
 760         } else {
 761                 printf("%s: No link.\n", dev->name);
 762         }
 763 }
 764
 765 /* Set up the buffers and their descriptors, and bring up the
 766  * interface
 767  */
 768 static void startup_tsec(struct eth_device *dev)
 769 {
 770         int i;
 771         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 772         volatile tsec_t *regs = priv->regs;
 773
 774         /* Point to the buffer descriptors */
 775         regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
 776         regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
 777
 778         /* Initialize the Rx Buffer descriptors */
 779         for (i = 0; i < PKTBUFSRX; i++) {
 780                 rtx.rxbd[i].status = RXBD_EMPTY;
 781                 rtx.rxbd[i].length = 0;
 782                 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
 783         }
 784         rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
 785
 786         /* Initialize the TX Buffer Descriptors */
 787         for (i = 0; i < TX_BUF_CNT; i++) {
 788                 rtx.txbd[i].status = 0;
 789                 rtx.txbd[i].length = 0;
 790                 rtx.txbd[i].bufPtr = 0;
 791         }
 792         rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
 793
 794         /* Start up the PHY */
 795         if(priv->phyinfo)
 796                 phy_run_commands(priv, priv->phyinfo->startup);
 797
 798         adjust_link(dev);
 799
 800         /* Enable Transmit and Receive */
 801         regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 802
 803         /* Tell the DMA it is clear to go */
 804         regs->dmactrl |= DMACTRL_INIT_SETTINGS;
 805         regs->tstat = TSTAT_CLEAR_THALT;
 806         regs->rstat = RSTAT_CLEAR_RHALT;
 807         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 808 }
 809
 810 /* This returns the status bits of the device.  The return value
 811  * is never checked, and this is what the 8260 driver did, so we
 812  * do the same.  Presumably, this would be zero if there were no
 813  * errors
 814  */
 815 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
 816 {
 817         int i;
 818         int result = 0;
 819         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 820         volatile tsec_t *regs = priv->regs;
 821
 822         /* Find an empty buffer descriptor */
 823         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 824                 if (i >= TOUT_LOOP) {
 825                         debug("%s: tsec: tx buffers full\n", dev->name);
 826                         return result;
 827                 }
 828         }
 829
 830         rtx.txbd[txIdx].bufPtr = (uint) packet;
 831         rtx.txbd[txIdx].length = length;
 832         rtx.txbd[txIdx].status |=
 833             (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
 834
 835         /* Tell the DMA to go */
 836         regs->tstat = TSTAT_CLEAR_THALT;
 837
 838         /* Wait for buffer to be transmitted */
 839         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 840                 if (i >= TOUT_LOOP) {
 841                         debug("%s: tsec: tx error\n", dev->name);
 842                         return result;
 843                 }
 844         }
 845
 846         txIdx = (txIdx + 1) % TX_BUF_CNT;
 847         result = rtx.txbd[txIdx].status & TXBD_STATS;
 848
 849         return result;
 850 }
 851
 852 static int tsec_recv(struct eth_device *dev)
 853 {
 854         int length;
 855         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 856         volatile tsec_t *regs = priv->regs;
 857
 858         while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
 859
 860                 length = rtx.rxbd[rxIdx].length;
 861
 862                 /* Send the packet up if there were no errors */
 863                 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
 864                         NetReceive(NetRxPackets[rxIdx], length - 4);
 865                 } else {
 866                         printf("Got error %x\n",
 867                                (rtx.rxbd[rxIdx].status & RXBD_STATS));
 868                 }
 869
 870                 rtx.rxbd[rxIdx].length = 0;
 871
 872                 /* Set the wrap bit if this is the last element in the list */
 873                 rtx.rxbd[rxIdx].status =
 874                     RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
 875
 876                 rxIdx = (rxIdx + 1) % PKTBUFSRX;
 877         }
 878
 879         if (regs->ievent & IEVENT_BSY) {
 880                 regs->ievent = IEVENT_BSY;
 881                 regs->rstat = RSTAT_CLEAR_RHALT;
 882         }
 883
 884         return -1;
 885
 886 }
 887
 888 /* Stop the interface */
 889 static void tsec_halt(struct eth_device *dev)
 890 {
 891         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 892         volatile tsec_t *regs = priv->regs;
 893
 894         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 895         regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
 896
 897         while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
 898
 899         regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
 900
 901         /* Shut down the PHY, as needed */
 902         if(priv->phyinfo)
 903                 phy_run_commands(priv, priv->phyinfo->shutdown);
 904 }
 905
 906 struct phy_info phy_info_M88E1149S = {
 907         0x1410ca,
 908         "Marvell 88E1149S",
 909         4,
 910         (struct phy_cmd[]){     /* config */
 911                 /* Reset and configure the PHY */
 912                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 913                 {0x1d, 0x1f, NULL},
 914                 {0x1e, 0x200c, NULL},
 915                 {0x1d, 0x5, NULL},
 916                 {0x1e, 0x0, NULL},
 917                 {0x1e, 0x100, NULL},
 918                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 919                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 920                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 921                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 922                 {miim_end,}
 923         },
 924         (struct phy_cmd[]){     /* startup */
 925                 /* Status is read once to clear old link state */
 926                 {MIIM_STATUS, miim_read, NULL},
 927                 /* Auto-negotiate */
 928                 {MIIM_STATUS, miim_read, &mii_parse_sr},
 929                 /* Read the status */
 930                 {MIIM_88E1011_PHY_STATUS, miim_read,
 931                  &mii_parse_88E1011_psr},
 932                 {miim_end,}
 933         },
 934         (struct phy_cmd[]){     /* shutdown */
 935                 {miim_end,}
 936         },
 937 };
 938
 939 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
 940 struct phy_info phy_info_BCM5461S = {
 941         0x02060c1,      /* 5461 ID */
 942         "Broadcom BCM5461S",
 943         0, /* not clear to me what minor revisions we can shift away */
 944         (struct phy_cmd[]) { /* config */
 945                 /* Reset and configure the PHY */
 946                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 947                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 948                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 949                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 950                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 951                 {miim_end,}
 952         },
 953         (struct phy_cmd[]) { /* startup */
 954                 /* Status is read once to clear old link state */
 955                 {MIIM_STATUS, miim_read, NULL},
 956                 /* Auto-negotiate */
 957                 {MIIM_STATUS, miim_read, &mii_parse_sr},
 958                 /* Read the status */
 959                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
 960                 {miim_end,}
 961         },
 962         (struct phy_cmd[]) { /* shutdown */
 963                 {miim_end,}
 964         },
 965 };
 966
 967 struct phy_info phy_info_BCM5464S = {
 968         0x02060b1,      /* 5464 ID */
 969         "Broadcom BCM5464S",
 970         0, /* not clear to me what minor revisions we can shift away */
 971         (struct phy_cmd[]) { /* config */
 972                 /* Reset and configure the PHY */
 973                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 974                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 975                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 976                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 977                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 978                 {miim_end,}
 979         },
 980         (struct phy_cmd[]) { /* startup */
 981                 /* Status is read once to clear old link state */
 982                 {MIIM_STATUS, miim_read, NULL},
 983                 /* Auto-negotiate */
 984                 {MIIM_STATUS, miim_read, &mii_parse_sr},
 985                 /* Read the status */
 986                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
 987                 {miim_end,}
 988         },
 989         (struct phy_cmd[]) { /* shutdown */
 990                 {miim_end,}
 991         },
 992 };
 993
 994 struct phy_info phy_info_M88E1011S = {
 995         0x01410c6,
 996         "Marvell 88E1011S",
 997         4,
 998         (struct phy_cmd[]){     /* config */
 999                            /* Reset and configure the PHY */
1000                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1001                            {0x1d, 0x1f, NULL},
1002                            {0x1e, 0x200c, NULL},
1003                            {0x1d, 0x5, NULL},
1004                            {0x1e, 0x0, NULL},
1005                            {0x1e, 0x100, NULL},
1006                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1007                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1008                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1009                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1010                            {miim_end,}
1011                            },
1012         (struct phy_cmd[]){     /* startup */
1013                            /* Status is read once to clear old link state */
1014                            {MIIM_STATUS, miim_read, NULL},
1015                            /* Auto-negotiate */
1016                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1017                            /* Read the status */
1018                            {MIIM_88E1011_PHY_STATUS, miim_read,
1019                             &mii_parse_88E1011_psr},
1020                            {miim_end,}
1021                            },
1022         (struct phy_cmd[]){     /* shutdown */
1023                            {miim_end,}
1024                            },
1025 };
1026
1027 struct phy_info phy_info_M88E1111S = {
1028         0x01410cc,
1029         "Marvell 88E1111S",
1030         4,
1031         (struct phy_cmd[]){     /* config */
1032                            /* Reset and configure the PHY */
1033                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1034                            {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
1035                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1036                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1037                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1038                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1039                            {miim_end,}
1040                            },
1041         (struct phy_cmd[]){     /* startup */
1042                            /* Status is read once to clear old link state */
1043                            {MIIM_STATUS, miim_read, NULL},
1044                            /* Auto-negotiate */
1045                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1046                            /* Read the status */
1047                            {MIIM_88E1011_PHY_STATUS, miim_read,
1048                             &mii_parse_88E1011_psr},
1049                            {miim_end,}
1050                            },
1051         (struct phy_cmd[]){     /* shutdown */
1052                            {miim_end,}
1053                            },
1054 };
1055
1056 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
1057 {
1058         uint mii_data = read_phy_reg(priv, mii_reg);
1059
1060         /* Setting MIIM_88E1145_PHY_EXT_CR */
1061         if (priv->flags & TSEC_REDUCED)
1062                 return mii_data |
1063                     MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
1064         else
1065                 return mii_data;
1066 }
1067
1068 static struct phy_info phy_info_M88E1145 = {
1069         0x01410cd,
1070         "Marvell 88E1145",
1071         4,
1072         (struct phy_cmd[]){     /* config */
1073                            /* Reset the PHY */
1074                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1075
1076                            /* Errata E0, E1 */
1077                            {29, 0x001b, NULL},
1078                            {30, 0x418f, NULL},
1079                            {29, 0x0016, NULL},
1080                            {30, 0xa2da, NULL},
1081
1082                            /* Configure the PHY */
1083                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1084                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1085                            {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
1086                             NULL},
1087                            {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
1088                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1089                            {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
1090                            {miim_end,}
1091                            },
1092         (struct phy_cmd[]){     /* startup */
1093                            /* Status is read once to clear old link state */
1094                            {MIIM_STATUS, miim_read, NULL},
1095                            /* Auto-negotiate */
1096                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1097                            {MIIM_88E1111_PHY_LED_CONTROL,
1098                             MIIM_88E1111_PHY_LED_DIRECT, NULL},
1099                            /* Read the Status */
1100                            {MIIM_88E1011_PHY_STATUS, miim_read,
1101                             &mii_parse_88E1011_psr},
1102                            {miim_end,}
1103                            },
1104         (struct phy_cmd[]){     /* shutdown */
1105                            {miim_end,}
1106                            },
1107 };
1108
1109 struct phy_info phy_info_cis8204 = {
1110         0x3f11,
1111         "Cicada Cis8204",
1112         6,
1113         (struct phy_cmd[]){     /* config */
1114                            /* Override PHY config settings */
1115                            {MIIM_CIS8201_AUX_CONSTAT,
1116                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1117                            /* Configure some basic stuff */
1118                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1119                            {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
1120                             &mii_cis8204_fixled},
1121                            {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
1122                             &mii_cis8204_setmode},
1123                            {miim_end,}
1124                            },
1125         (struct phy_cmd[]){     /* startup */
1126                            /* Read the Status (2x to make sure link is right) */
1127                            {MIIM_STATUS, miim_read, NULL},
1128                            /* Auto-negotiate */
1129                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1130                            /* Read the status */
1131                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1132                             &mii_parse_cis8201},
1133                            {miim_end,}
1134                            },
1135         (struct phy_cmd[]){     /* shutdown */
1136                            {miim_end,}
1137                            },
1138 };
1139
1140 /* Cicada 8201 */
1141 struct phy_info phy_info_cis8201 = {
1142         0xfc41,
1143         "CIS8201",
1144         4,
1145         (struct phy_cmd[]){     /* config */
1146                            /* Override PHY config settings */
1147                            {MIIM_CIS8201_AUX_CONSTAT,
1148                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1149                            /* Set up the interface mode */
1150                            {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
1151                             NULL},
1152                            /* Configure some basic stuff */
1153                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1154                            {miim_end,}
1155                            },
1156         (struct phy_cmd[]){     /* startup */
1157                            /* Read the Status (2x to make sure link is right) */
1158                            {MIIM_STATUS, miim_read, NULL},
1159                            /* Auto-negotiate */
1160                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1161                            /* Read the status */
1162                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1163                             &mii_parse_cis8201},
1164                            {miim_end,}
1165                            },
1166         (struct phy_cmd[]){     /* shutdown */
1167                            {miim_end,}
1168                            },
1169 };
1170 struct phy_info phy_info_VSC8244 = {
1171         0x3f1b,
1172         "Vitesse VSC8244",
1173         6,
1174         (struct phy_cmd[]){     /* config */
1175                            /* Override PHY config settings */
1176                            /* Configure some basic stuff */
1177                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1178                            {miim_end,}
1179                            },
1180         (struct phy_cmd[]){     /* startup */
1181                            /* Read the Status (2x to make sure link is right) */
1182                            {MIIM_STATUS, miim_read, NULL},
1183                            /* Auto-negotiate */
1184                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1185                            /* Read the status */
1186                            {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1187                             &mii_parse_vsc8244},
1188                            {miim_end,}
1189                            },
1190         (struct phy_cmd[]){     /* shutdown */
1191                            {miim_end,}
1192                            },
1193 };
1194
1195 struct phy_info phy_info_dm9161 = {
1196         0x0181b88,
1197         "Davicom DM9161E",
1198         4,
1199         (struct phy_cmd[]){     /* config */
1200                            {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1201                            /* Do not bypass the scrambler/descrambler */
1202                            {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1203                            /* Clear 10BTCSR to default */
1204                            {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
1205                             NULL},
1206                            /* Configure some basic stuff */
1207                            {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1208                            /* Restart Auto Negotiation */
1209                            {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1210                            {miim_end,}
1211                            },
1212         (struct phy_cmd[]){     /* startup */
1213                            /* Status is read once to clear old link state */
1214                            {MIIM_STATUS, miim_read, NULL},
1215                            /* Auto-negotiate */
1216                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1217                            /* Read the status */
1218                            {MIIM_DM9161_SCSR, miim_read,
1219                             &mii_parse_dm9161_scsr},
1220                            {miim_end,}
1221                            },
1222         (struct phy_cmd[]){     /* shutdown */
1223                            {miim_end,}
1224                            },
1225 };
1226 /* a generic flavor.  */
1227 struct phy_info phy_info_generic =  {
1228         0,
1229         "Unknown/Generic PHY",
1230         32,
1231         (struct phy_cmd[]) { /* config */
1232                 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1233                 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1234                 {miim_end,}
1235         },
1236         (struct phy_cmd[]) { /* startup */
1237                 {PHY_BMSR, miim_read, NULL},
1238                 {PHY_BMSR, miim_read, &mii_parse_sr},
1239                 {PHY_BMSR, miim_read, &mii_parse_link},
1240                 {miim_end,}
1241         },
1242         (struct phy_cmd[]) { /* shutdown */
1243                 {miim_end,}
1244         }
1245 };
1246
1247
1248 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1249 {
1250         unsigned int speed;
1251         if (priv->link) {
1252                 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1253
1254                 switch (speed) {
1255                 case MIIM_LXT971_SR2_10HDX:
1256                         priv->speed = 10;
1257                         priv->duplexity = 0;
1258                         break;
1259                 case MIIM_LXT971_SR2_10FDX:
1260                         priv->speed = 10;
1261                         priv->duplexity = 1;
1262                         break;
1263                 case MIIM_LXT971_SR2_100HDX:
1264                         priv->speed = 100;
1265                         priv->duplexity = 0;
1266                         break;
1267                 default:
1268                         priv->speed = 100;
1269                         priv->duplexity = 1;
1270                 }
1271         } else {
1272                 priv->speed = 0;
1273                 priv->duplexity = 0;
1274         }
1275
1276         return 0;
1277 }
1278
1279 static struct phy_info phy_info_lxt971 = {
1280         0x0001378e,
1281         "LXT971",
1282         4,
1283         (struct phy_cmd[]){     /* config */
1284                            {MIIM_CR, MIIM_CR_INIT, mii_cr_init},        /* autonegotiate */
1285                            {miim_end,}
1286                            },
1287         (struct phy_cmd[]){     /* startup - enable interrupts */
1288                            /* { 0x12, 0x00f2, NULL }, */
1289                            {MIIM_STATUS, miim_read, NULL},
1290                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1291                            {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1292                            {miim_end,}
1293                            },
1294         (struct phy_cmd[]){     /* shutdown - disable interrupts */
1295                            {miim_end,}
1296                            },
1297 };
1298
1299 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1300  * information
1301  */
1302 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1303 {
1304         switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1305
1306         case MIIM_DP83865_SPD_1000:
1307                 priv->speed = 1000;
1308                 break;
1309
1310         case MIIM_DP83865_SPD_100:
1311                 priv->speed = 100;
1312                 break;
1313
1314         default:
1315                 priv->speed = 10;
1316                 break;
1317
1318         }
1319
1320         if (mii_reg & MIIM_DP83865_DPX_FULL)
1321                 priv->duplexity = 1;
1322         else
1323                 priv->duplexity = 0;
1324
1325         return 0;
1326 }
1327
1328 struct phy_info phy_info_dp83865 = {
1329         0x20005c7,
1330         "NatSemi DP83865",
1331         4,
1332         (struct phy_cmd[]){     /* config */
1333                            {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1334                            {miim_end,}
1335                            },
1336         (struct phy_cmd[]){     /* startup */
1337                            /* Status is read once to clear old link state */
1338                            {MIIM_STATUS, miim_read, NULL},
1339                            /* Auto-negotiate */
1340                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1341                            /* Read the link and auto-neg status */
1342                            {MIIM_DP83865_LANR, miim_read,
1343                             &mii_parse_dp83865_lanr},
1344                            {miim_end,}
1345                            },
1346         (struct phy_cmd[]){     /* shutdown */
1347                            {miim_end,}
1348                            },
1349 };
1350
1351 struct phy_info *phy_info[] = {
1352         &phy_info_cis8204,
1353         &phy_info_cis8201,
1354         &phy_info_BCM5461S,
1355         &phy_info_BCM5464S,
1356         &phy_info_M88E1011S,
1357         &phy_info_M88E1111S,
1358         &phy_info_M88E1145,
1359         &phy_info_M88E1149S,
1360         &phy_info_dm9161,
1361         &phy_info_lxt971,
1362         &phy_info_VSC8244,
1363         &phy_info_dp83865,
1364         &phy_info_generic,
1365         NULL
1366 };
1367
1368 /* Grab the identifier of the device's PHY, and search through
1369  * all of the known PHYs to see if one matches.  If so, return
1370  * it, if not, return NULL
1371  */
1372 struct phy_info *get_phy_info(struct eth_device *dev)
1373 {
1374         struct tsec_private *priv = (struct tsec_private *)dev->priv;
1375         uint phy_reg, phy_ID;
1376         int i;
1377         struct phy_info *theInfo = NULL;
1378
1379         /* Grab the bits from PHYIR1, and put them in the upper half */
1380         phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1381         phy_ID = (phy_reg & 0xffff) << 16;
1382
1383         /* Grab the bits from PHYIR2, and put them in the lower half */
1384         phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1385         phy_ID |= (phy_reg & 0xffff);
1386
1387         /* loop through all the known PHY types, and find one that */
1388         /* matches the ID we read from the PHY. */
1389         for (i = 0; phy_info[i]; i++) {
1390                 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
1391                         theInfo = phy_info[i];
1392                         break;
1393                 }
1394         }
1395
1396         if (theInfo == NULL) {
1397                 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
1398                 return NULL;
1399         } else {
1400                 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1401         }
1402
1403         return theInfo;
1404 }
1405
1406 /* Execute the given series of commands on the given device's
1407  * PHY, running functions as necessary
1408  */
1409 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1410 {
1411         int i;
1412         uint result;
1413         volatile tsec_t *phyregs = priv->phyregs;
1414
1415         phyregs->miimcfg = MIIMCFG_RESET;
1416
1417         phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1418
1419         while (phyregs->miimind & MIIMIND_BUSY) ;
1420
1421         for (i = 0; cmd->mii_reg != miim_end; i++) {
1422                 if (cmd->mii_data == miim_read) {
1423                         result = read_phy_reg(priv, cmd->mii_reg);
1424
1425                         if (cmd->funct != NULL)
1426                                 (*(cmd->funct)) (result, priv);
1427
1428                 } else {
1429                         if (cmd->funct != NULL)
1430                                 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1431                         else
1432                                 result = cmd->mii_data;
1433
1434                         write_phy_reg(priv, cmd->mii_reg, result);
1435
1436                 }
1437                 cmd++;
1438         }
1439 }
1440
1441 /* Relocate the function pointers in the phy cmd lists */
1442 static void relocate_cmds(void)
1443 {
1444         struct phy_cmd **cmdlistptr;
1445         struct phy_cmd *cmd;
1446         int i, j, k;
1447
1448         for (i = 0; phy_info[i]; i++) {
1449                 /* First thing's first: relocate the pointers to the
1450                  * PHY command structures (the structs were done) */
1451                 phy_info[i] = (struct phy_info *)((uint) phy_info[i]
1452                                                   + gd->reloc_off);
1453                 phy_info[i]->name += gd->reloc_off;
1454                 phy_info[i]->config =
1455                     (struct phy_cmd *)((uint) phy_info[i]->config
1456                                        + gd->reloc_off);
1457                 phy_info[i]->startup =
1458                     (struct phy_cmd *)((uint) phy_info[i]->startup
1459                                        + gd->reloc_off);
1460                 phy_info[i]->shutdown =
1461                     (struct phy_cmd *)((uint) phy_info[i]->shutdown
1462                                        + gd->reloc_off);
1463
1464                 cmdlistptr = &phy_info[i]->config;
1465                 j = 0;
1466                 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
1467                         k = 0;
1468                         for (cmd = *cmdlistptr;
1469                              cmd->mii_reg != miim_end;
1470                              cmd++) {
1471                                 /* Only relocate non-NULL pointers */
1472                                 if (cmd->funct)
1473                                         cmd->funct += gd->reloc_off;
1474
1475                                 k++;
1476                         }
1477                         j++;
1478                 }
1479         }
1480
1481         relocated = 1;
1482 }
1483
1484 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1485         && !defined(BITBANGMII)
1486
1487 struct tsec_private *get_priv_for_phy(unsigned char phyaddr)
1488 {
1489         int i;
1490
1491         for (i = 0; i < MAXCONTROLLERS; i++) {
1492                 if (privlist[i]->phyaddr == phyaddr)
1493                         return privlist[i];
1494         }
1495
1496         return NULL;
1497 }
1498
1499 /*
1500  * Read a MII PHY register.
1501  *
1502  * Returns:
1503  *  0 on success
1504  */
1505 static int tsec_miiphy_read(char *devname, unsigned char addr,
1506                             unsigned char reg, unsigned short *value)
1507 {
1508         unsigned short ret;
1509         struct tsec_private *priv = get_priv_for_phy(addr);
1510
1511         if (NULL == priv) {
1512                 printf("Can't read PHY at address %d\n", addr);
1513                 return -1;
1514         }
1515
1516         ret = (unsigned short)read_phy_reg(priv, reg);
1517         *value = ret;
1518
1519         return 0;
1520 }
1521
1522 /*
1523  * Write a MII PHY register.
1524  *
1525  * Returns:
1526  *  0 on success
1527  */
1528 static int tsec_miiphy_write(char *devname, unsigned char addr,
1529                              unsigned char reg, unsigned short value)
1530 {
1531         struct tsec_private *priv = get_priv_for_phy(addr);
1532
1533         if (NULL == priv) {
1534                 printf("Can't write PHY at address %d\n", addr);
1535                 return -1;
1536         }
1537
1538         write_phy_reg(priv, reg, value);
1539
1540         return 0;
1541 }
1542
1543 #endif
1544
1545 #ifdef CONFIG_MCAST_TFTP
1546
1547 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
1548
1549 /* Set the appropriate hash bit for the given addr */
1550
1551 /* The algorithm works like so:
1552  * 1) Take the Destination Address (ie the multicast address), and
1553  * do a CRC on it (little endian), and reverse the bits of the
1554  * result.
1555  * 2) Use the 8 most significant bits as a hash into a 256-entry
1556  * table.  The table is controlled through 8 32-bit registers:
1557  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1558  * gaddr7.  This means that the 3 most significant bits in the
1559  * hash index which gaddr register to use, and the 5 other bits
1560  * indicate which bit (assuming an IBM numbering scheme, which
1561  * for PowerPC (tm) is usually the case) in the tregister holds
1562  * the entry. */
1563 static int
1564 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
1565 {
1566  struct tsec_private *priv = privlist[1];
1567  volatile tsec_t *regs = priv->regs;
1568  volatile u32  *reg_array, value;
1569  u8 result, whichbit, whichreg;
1570
1571         result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
1572         whichbit = result & 0x1f;       /* the 5 LSB = which bit to set */
1573         whichreg = result >> 5;         /* the 3 MSB = which reg to set it in */
1574         value = (1 << (31-whichbit));
1575
1576         reg_array = &(regs->hash.gaddr0);
1577
1578         if (set) {
1579                 reg_array[whichreg] |= value;
1580         } else {
1581                 reg_array[whichreg] &= ~value;
1582         }
1583         return 0;
1584 }
1585 #endif /* Multicast TFTP ? */
1586
1587 #endif /* CONFIG_TSEC_ENET */