1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2012 The Chromium OS Authors.
5 * TSC calibration codes are adapted from Linux kernel
6 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
16 #include <asm/i8254.h>
17 #include <asm/ibmpc.h>
19 #include <asm/u-boot-x86.h>
21 #define MAX_NUM_FREQS 9
23 #define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
24 #define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
25 #define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
26 #define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
27 #define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
28 #define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
30 DECLARE_GLOBAL_DATA_PTR;
33 * native_calibrate_tsc
34 * Determine TSC frequency via CPUID, else return 0.
36 static unsigned long native_calibrate_tsc(void)
38 struct cpuid_result tsc_info;
39 unsigned int crystal_freq;
41 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
44 if (cpuid_eax(0) < 0x15)
47 tsc_info = cpuid(0x15);
49 if (tsc_info.ebx == 0 || tsc_info.eax == 0)
52 crystal_freq = tsc_info.ecx / 1000;
55 switch (gd->arch.x86_model) {
56 case INTEL_FAM6_SKYLAKE_MOBILE:
57 case INTEL_FAM6_SKYLAKE_DESKTOP:
58 case INTEL_FAM6_KABYLAKE_MOBILE:
59 case INTEL_FAM6_KABYLAKE_DESKTOP:
60 crystal_freq = 24000; /* 24.0 MHz */
62 case INTEL_FAM6_ATOM_GOLDMONT_X:
63 crystal_freq = 25000; /* 25.0 MHz */
65 case INTEL_FAM6_ATOM_GOLDMONT:
66 crystal_freq = 19200; /* 19.2 MHz */
73 return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
76 static unsigned long cpu_mhz_from_cpuid(void)
78 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
81 if (cpuid_eax(0) < 0x16)
84 return cpuid_eax(0x16);
88 * According to Intel 64 and IA-32 System Programming Guide,
89 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
90 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
91 * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
92 * so we need manually differentiate SoC families. This is what the
93 * field msr_plat does.
96 u8 x86_family; /* CPU family */
97 u8 x86_model; /* model */
98 /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
100 u32 freqs[MAX_NUM_FREQS];
103 static struct freq_desc freq_desc_tables[] = {
105 { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
107 { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
108 /* TNG - Intel Atom processor Z3400 series */
109 { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
110 /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
111 { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
112 /* ANN - Intel Atom processor Z3500 series */
113 { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
114 /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
115 { 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
116 80000, 93300, 90000, 88900, 87500 } },
118 { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
121 static int match_cpu(u8 family, u8 model)
125 for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
126 if ((family == freq_desc_tables[i].x86_family) &&
127 (model == freq_desc_tables[i].x86_model))
134 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
135 #define id_to_freq(cpu_index, freq_id) \
136 (freq_desc_tables[cpu_index].freqs[freq_id])
139 * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
140 * reliable and the frequency is known (provided by HW).
142 * On these platforms PIT/HPET is generally not available so calibration won't
143 * work at all and there is no other clocksource to act as a watchdog for the
144 * TSC, so we have no other choice than to trust it.
146 * Returns the TSC frequency in MHz or 0 if HW does not provide it.
148 static unsigned long __maybe_unused cpu_mhz_from_msr(void)
150 u32 lo, hi, ratio, freq_id, freq;
154 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
157 cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
161 if (freq_desc_tables[cpu_index].msr_plat) {
162 rdmsr(MSR_PLATFORM_INFO, lo, hi);
163 ratio = (lo >> 8) & 0xff;
165 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
166 ratio = (hi >> 8) & 0x1f;
168 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
170 if (freq_desc_tables[cpu_index].msr_plat == 2) {
171 /* TODO: Figure out how best to deal with this */
173 debug("Using frequency: %u KHz\n", freq);
175 /* Get FSB FREQ ID */
176 rdmsr(MSR_FSB_FREQ, lo, hi);
178 freq = id_to_freq(cpu_index, freq_id);
179 debug("Resolved frequency ID: %u, frequency: %u KHz\n",
183 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
184 res = freq * ratio / 1000;
185 debug("TSC runs at %lu MHz\n", res);
191 * This reads the current MSB of the PIT counter, and
192 * checks if we are running on sufficiently fast and
193 * non-virtualized hardware.
195 * Our expectations are:
197 * - the PIT is running at roughly 1.19MHz
199 * - each IO is going to take about 1us on real hardware,
200 * but we allow it to be much faster (by a factor of 10) or
201 * _slightly_ slower (ie we allow up to a 2us read+counter
202 * update - anything else implies a unacceptably slow CPU
203 * or PIT for the fast calibration to work.
205 * - with 256 PIT ticks to read the value, we have 214us to
206 * see the same MSB (and overhead like doing a single TSC
207 * read per MSB value etc).
209 * - We're doing 2 reads per loop (LSB, MSB), and we expect
210 * them each to take about a microsecond on real hardware.
211 * So we expect a count value of around 100. But we'll be
212 * generous, and accept anything over 50.
214 * - if the PIT is stuck, and we see *many* more reads, we
215 * return early (and the next caller of pit_expect_msb()
216 * then consider it a failure when they don't see the
217 * next expected value).
219 * These expectations mean that we know that we have seen the
220 * transition from one expected value to another with a fairly
221 * high accuracy, and we didn't miss any events. We can thus
222 * use the TSC value at the transitions to calculate a pretty
223 * good value for the TSC frequencty.
225 static inline int pit_verify_msb(unsigned char val)
229 return inb(0x42) == val;
232 static inline int pit_expect_msb(unsigned char val, u64 *tscp,
233 unsigned long *deltap)
236 u64 tsc = 0, prev_tsc = 0;
238 for (count = 0; count < 50000; count++) {
239 if (!pit_verify_msb(val))
244 *deltap = rdtsc() - prev_tsc;
248 * We require _some_ success, but the quality control
249 * will be based on the error terms on the TSC values.
255 * How many MSB values do we want to see? We aim for
256 * a maximum error rate of 500ppm (in practice the
257 * real error is much smaller), but refuse to spend
258 * more than 50ms on it.
260 #define MAX_QUICK_PIT_MS 50
261 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
263 static unsigned long __maybe_unused quick_pit_calibrate(void)
267 unsigned long d1, d2;
269 /* Set the Gate high, disable speaker */
270 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
273 * Counter 2, mode 0 (one-shot), binary count
275 * NOTE! Mode 2 decrements by two (and then the
276 * output is flipped each time, giving the same
277 * final output frequency as a decrement-by-one),
278 * so mode 0 is much better when looking at the
283 /* Start at 0xffff */
288 * The PIT starts counting at the next edge, so we
289 * need to delay for a microsecond. The easiest way
290 * to do that is to just read back the 16-bit counter
295 if (pit_expect_msb(0xff, &tsc, &d1)) {
296 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
297 if (!pit_expect_msb(0xff-i, &delta, &d2))
301 * Iterate until the error is less than 500 ppm
304 if (d1+d2 >= delta >> 11)
308 * Check the PIT one more time to verify that
309 * all TSC reads were stable wrt the PIT.
311 * This also guarantees serialization of the
312 * last cycle read ('d2') in pit_expect_msb.
314 if (!pit_verify_msb(0xfe - i))
319 debug("Fast TSC calibration failed\n");
324 * Ok, if we get here, then we've seen the
325 * MSB of the PIT decrement 'i' times, and the
326 * error has shrunk to less than 500 ppm.
328 * As a result, we can depend on there not being
329 * any odd delays anywhere, and the TSC reads are
330 * reliable (within the error).
332 * kHz = ticks / time-in-seconds / 1000;
333 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
334 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
336 delta *= PIT_TICK_RATE;
337 delta /= (i*256*1000);
338 debug("Fast TSC calibration using PIT\n");
342 /* Get the speed of the TSC timer in MHz */
343 unsigned notrace long get_tbclk_mhz(void)
345 return get_tbclk() / 1000000;
348 static ulong get_ms_timer(void)
350 return (get_ticks() * 1000) / get_tbclk();
353 ulong get_timer(ulong base)
355 return get_ms_timer() - base;
358 ulong notrace timer_get_us(void)
360 return get_ticks() / get_tbclk_mhz();
363 ulong timer_get_boot_us(void)
365 return timer_get_us();
368 void __udelay(unsigned long usec)
370 u64 now = get_ticks();
373 stop = now + usec * get_tbclk_mhz();
375 while ((int64_t)(stop - get_ticks()) > 0)
376 #if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
378 * Add a 'pause' instruction on qemu target,
379 * to give other VCPUs a chance to run.
381 asm volatile("pause");
387 static int tsc_timer_get_count(struct udevice *dev, u64 *count)
389 u64 now_tick = rdtsc();
391 *count = now_tick - gd->arch.tsc_base;
396 static void tsc_timer_ensure_setup(bool early)
398 if (gd->arch.tsc_inited)
400 if (IS_ENABLED(CONFIG_X86_TSC_READ_BASE))
401 gd->arch.tsc_base = rdtsc();
403 if (!gd->arch.clock_rate) {
404 unsigned long fast_calibrate;
406 fast_calibrate = native_calibrate_tsc();
410 fast_calibrate = cpu_mhz_from_cpuid();
414 fast_calibrate = cpu_mhz_from_msr();
418 fast_calibrate = quick_pit_calibrate();
423 fast_calibrate = CONFIG_X86_TSC_TIMER_EARLY_FREQ;
428 gd->arch.clock_rate = fast_calibrate * 1000000;
430 gd->arch.tsc_inited = true;
433 static int tsc_timer_probe(struct udevice *dev)
435 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
437 /* Try hardware calibration first */
438 tsc_timer_ensure_setup(false);
439 if (!gd->arch.clock_rate) {
441 * Use the clock frequency specified in the
442 * device tree as last resort
444 if (!uc_priv->clock_rate)
445 panic("TSC frequency is ZERO");
447 uc_priv->clock_rate = gd->arch.clock_rate;
453 unsigned long notrace timer_early_get_rate(void)
456 * When TSC timer is used as the early timer, be warned that the timer
457 * clock rate can only be calibrated via some hardware ways. Specifying
458 * it in the device tree won't work for the early timer.
460 tsc_timer_ensure_setup(true);
462 return gd->arch.clock_rate;
465 u64 notrace timer_early_get_count(void)
467 tsc_timer_ensure_setup(true);
469 return rdtsc() - gd->arch.tsc_base;
472 static const struct timer_ops tsc_timer_ops = {
473 .get_count = tsc_timer_get_count,
476 static const struct udevice_id tsc_timer_ids[] = {
477 { .compatible = "x86,tsc-timer", },
481 U_BOOT_DRIVER(tsc_timer) = {
484 .of_match = tsc_timer_ids,
485 .probe = tsc_timer_probe,
486 .ops = &tsc_timer_ops,