1 // SPDX-License-Identifier: GPL-2.0+
3 * Designware APB Timer driver
5 * Copyright (C) 2018 Marek Vasut <marex@denx.de>
15 #include <asm/arch/timer.h>
17 #define DW_APB_LOAD_VAL 0x0
18 #define DW_APB_CURR_VAL 0x4
19 #define DW_APB_CTRL 0x8
21 struct dw_apb_timer_priv {
23 struct reset_ctl_bulk resets;
26 static int dw_apb_timer_get_count(struct udevice *dev, u64 *count)
28 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
31 * The DW APB counter counts down, but this function
32 * requires the count to be incrementing. Invert the
35 *count = timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL));
40 static int dw_apb_timer_probe(struct udevice *dev)
42 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
43 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
47 ret = reset_get_bulk(dev, &priv->resets);
49 dev_warn(dev, "Can't get reset: %d\n", ret);
51 reset_deassert_bulk(&priv->resets);
53 ret = clk_get_by_index(dev, 0, &clk);
57 uc_priv->clock_rate = clk_get_rate(&clk);
62 writel(0xffffffff, priv->regs + DW_APB_LOAD_VAL);
63 writel(0xffffffff, priv->regs + DW_APB_CURR_VAL);
64 setbits_le32(priv->regs + DW_APB_CTRL, 0x3);
69 static int dw_apb_timer_ofdata_to_platdata(struct udevice *dev)
71 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
73 priv->regs = dev_read_addr(dev);
78 static int dw_apb_timer_remove(struct udevice *dev)
80 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
82 return reset_release_bulk(&priv->resets);
85 static const struct timer_ops dw_apb_timer_ops = {
86 .get_count = dw_apb_timer_get_count,
89 static const struct udevice_id dw_apb_timer_ids[] = {
90 { .compatible = "snps,dw-apb-timer" },
94 U_BOOT_DRIVER(dw_apb_timer) = {
95 .name = "dw_apb_timer",
97 .ops = &dw_apb_timer_ops,
98 .probe = dw_apb_timer_probe,
99 .of_match = dw_apb_timer_ids,
100 .ofdata_to_platdata = dw_apb_timer_ofdata_to_platdata,
101 .remove = dw_apb_timer_remove,
102 .priv_auto_alloc_size = sizeof(struct dw_apb_timer_priv),