1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017~2020 NXP
10 #include <asm/arch/clock.h>
11 #include <asm/arch/sys_proto.h>
13 #include <dm/device-internal.h>
14 #include <dm/device.h>
20 DECLARE_GLOBAL_DATA_PTR;
23 #define FLAGS_VER2 0x1
25 #define TMR_DISABLE 0x0
26 #define TMR_ME 0x80000000
27 #define TMR_ALPF 0x0c000000
28 #define TMTMIR_DEFAULT 0x00000002
29 #define TIER_DISABLE 0x0
31 #define TER_EN 0x80000000
32 #define TER_ADC_PD 0x40000000
36 struct imx_tmu_site_regs {
37 u32 tritsr; /* Immediate Temperature Site Register */
38 u32 tratsr; /* Average Temperature Site Register */
43 u32 tmr; /* Mode Register */
44 u32 tsr; /* Status Register */
45 u32 tmtmir; /* Temperature measurement interval Register */
47 u32 tier; /* Interrupt Enable Register */
48 u32 tidr; /* Interrupt Detect Register */
49 u32 tiscr; /* Interrupt Site Capture Register */
50 u32 ticscr; /* Interrupt Critical Site Capture Register */
52 u32 tmhtcrh; /* High Temperature Capture Register */
53 u32 tmhtcrl; /* Low Temperature Capture Register */
55 u32 tmhtitr; /* High Temperature Immediate Threshold */
56 u32 tmhtatr; /* High Temperature Average Threshold */
57 u32 tmhtactr; /* High Temperature Average Crit Threshold */
59 u32 ttcfgr; /* Temperature Configuration Register */
60 u32 tscfgr; /* Sensor Configuration Register */
62 struct imx_tmu_site_regs site[SITES_MAX];
64 u32 ipbrr0; /* IP Block Revision Register 0 */
65 u32 ipbrr1; /* IP Block Revision Register 1 */
67 u32 ttr0cr; /* Temperature Range 0 Control Register */
68 u32 ttr1cr; /* Temperature Range 1 Control Register */
69 u32 ttr2cr; /* Temperature Range 2 Control Register */
70 u32 ttr3cr; /* Temperature Range 3 Control Register */
73 struct imx_tmu_regs_v2 {
74 u32 ter; /* TMU enable Register */
75 u32 tsr; /* Status Register */
76 u32 tier; /* Interrupt enable register */
77 u32 tidr; /* Interrupt detect register */
78 u32 tmhtitr; /* Monitor high temperature immediate threshold register */
79 u32 tmhtatr; /* Monitor high temperature average threshold register */
80 u32 tmhtactr; /* TMU monitor high temperature average critical threshold register */
81 u32 tscr; /* Sensor value capture register */
82 u32 tritsr; /* Report immediate temperature site register 0 */
83 u32 tratsr; /* Report average temperature site register 0 */
84 u32 tasr; /* Amplifier setting register */
85 u32 ttmc; /* Test MUX control */
90 struct imx_tmu_regs regs_v1;
91 struct imx_tmu_regs_v2 regs_v2;
100 union tmu_regs *regs;
103 static int read_temperature(struct udevice *dev, int *temp)
105 struct imx_tmu_plat *pdata = dev_get_platdata(dev);
106 ulong drv_data = dev_get_driver_data(dev);
115 if (drv_data & FLAGS_VER2) {
116 val = readl(&pdata->regs->regs_v2.tritsr);
118 * Check if TEMP is in valid range, the V bit in TRITSR
119 * only reflects the RAW uncalibrated data
121 valid = ((val & 0xff) < 10 || (val & 0xff) > 125) ? 0 : 1;
123 val = readl(&pdata->regs->regs_v1.site[pdata->id].tritsr);
124 valid = val & 0x80000000;
126 } while (!valid && retry > 0);
129 *temp = (val & 0xff) * 1000;
136 int imx_tmu_get_temp(struct udevice *dev, int *temp)
138 struct imx_tmu_plat *pdata = dev_get_platdata(dev);
142 ret = read_temperature(dev, &cpu_tmp);
146 while (cpu_tmp >= pdata->alert) {
147 printf("CPU Temperature (%dC) has beyond alert (%dC), close to critical (%dC)", cpu_tmp, pdata->alert, pdata->critical);
148 puts(" waiting...\n");
149 mdelay(pdata->polling_delay);
150 ret = read_temperature(dev, &cpu_tmp);
155 *temp = cpu_tmp / 1000;
160 static const struct dm_thermal_ops imx_tmu_ops = {
161 .get_temp = imx_tmu_get_temp,
164 static int imx_tmu_calibration(struct udevice *dev)
166 int i, val, len, ret;
168 const fdt32_t *calibration;
169 struct imx_tmu_plat *pdata = dev_get_platdata(dev);
170 ulong drv_data = dev_get_driver_data(dev);
172 debug("%s\n", __func__);
174 if (drv_data & FLAGS_VER2)
177 ret = dev_read_u32_array(dev, "fsl,tmu-range", range, 4);
179 printf("TMU: missing calibration range, ret = %d.\n", ret);
183 /* Init temperature range registers */
184 writel(range[0], &pdata->regs->regs_v1.ttr0cr);
185 writel(range[1], &pdata->regs->regs_v1.ttr1cr);
186 writel(range[2], &pdata->regs->regs_v1.ttr2cr);
187 writel(range[3], &pdata->regs->regs_v1.ttr3cr);
189 calibration = dev_read_prop(dev, "fsl,tmu-calibration", &len);
190 if (!calibration || len % 8) {
191 printf("TMU: invalid calibration data.\n");
195 for (i = 0; i < len; i += 8, calibration += 2) {
196 val = fdt32_to_cpu(*calibration);
197 writel(val, &pdata->regs->regs_v1.ttcfgr);
198 val = fdt32_to_cpu(*(calibration + 1));
199 writel(val, &pdata->regs->regs_v1.tscfgr);
205 void __weak imx_tmu_arch_init(void *reg_base)
209 static void imx_tmu_init(struct udevice *dev)
211 struct imx_tmu_plat *pdata = dev_get_platdata(dev);
212 ulong drv_data = dev_get_driver_data(dev);
214 debug("%s\n", __func__);
216 if (drv_data & FLAGS_VER2) {
217 /* Disable monitoring */
218 writel(0x0, &pdata->regs->regs_v2.ter);
220 /* Disable interrupt, using polling instead */
221 writel(0x0, &pdata->regs->regs_v2.tier);
223 /* Disable monitoring */
224 writel(TMR_DISABLE, &pdata->regs->regs_v1.tmr);
226 /* Disable interrupt, using polling instead */
227 writel(TIER_DISABLE, &pdata->regs->regs_v1.tier);
229 /* Set update_interval */
230 writel(TMTMIR_DEFAULT, &pdata->regs->regs_v1.tmtmir);
233 imx_tmu_arch_init((void *)pdata->regs);
236 static int imx_tmu_enable_msite(struct udevice *dev)
238 struct imx_tmu_plat *pdata = dev_get_platdata(dev);
239 ulong drv_data = dev_get_driver_data(dev);
242 debug("%s\n", __func__);
247 if (drv_data & FLAGS_VER2) {
248 reg = readl(&pdata->regs->regs_v2.ter);
250 writel(reg, &pdata->regs->regs_v2.ter);
254 writel(reg, &pdata->regs->regs_v2.ter);
258 writel(reg, &pdata->regs->regs_v2.ter);
260 /* Clear the ME before setting MSITE and ALPF*/
261 reg = readl(&pdata->regs->regs_v1.tmr);
263 writel(reg, &pdata->regs->regs_v1.tmr);
265 reg |= 1 << (15 - pdata->id);
267 writel(reg, &pdata->regs->regs_v1.tmr);
271 writel(reg, &pdata->regs->regs_v1.tmr);
277 static int imx_tmu_bind(struct udevice *dev)
279 struct imx_tmu_plat *pdata = dev_get_platdata(dev);
285 debug("%s dev name %s\n", __func__, dev->name);
287 prop = dev_read_prop(dev, "compatible", NULL);
291 pdata->zone_node = 1;
293 node = ofnode_path("/thermal-zones");
294 ofnode_for_each_subnode(offset, node) {
295 /* Bind the subnode to this driver */
296 name = ofnode_get_name(offset);
298 ret = device_bind_with_driver_data(dev, dev->driver, name,
299 dev->driver_data, offset,
302 printf("Error binding driver '%s': %d\n",
303 dev->driver->name, ret);
309 static int imx_tmu_parse_fdt(struct udevice *dev)
311 struct imx_tmu_plat *pdata = dev_get_platdata(dev), *p_parent_data;
312 struct ofnode_phandle_args args;
316 debug("%s dev name %s\n", __func__, dev->name);
318 if (pdata->zone_node) {
319 pdata->regs = (union tmu_regs *)dev_read_addr_ptr(dev);
326 p_parent_data = dev_get_platdata(dev->parent);
327 if (p_parent_data->zone_node)
328 pdata->regs = p_parent_data->regs;
330 ret = dev_read_phandle_with_args(dev, "thermal-sensors",
331 "#thermal-sensor-cells",
336 if (!ofnode_equal(args.node, dev_ofnode(dev->parent)))
339 if (args.args_count >= 1)
340 pdata->id = args.args[0];
344 debug("args.args_count %d, id %d\n", args.args_count, pdata->id);
346 pdata->polling_delay = dev_read_u32_default(dev, "polling-delay", 1000);
348 trips_np = ofnode_path("/thermal-zones/cpu-thermal/trips");
349 ofnode_for_each_subnode(trips_np, trips_np) {
352 type = ofnode_get_property(trips_np, "type", NULL);
355 if (!strcmp(type, "critical"))
356 pdata->critical = ofnode_read_u32_default(trips_np, "temperature", 85);
357 else if (strcmp(type, "passive") == 0)
358 pdata->alert = ofnode_read_u32_default(trips_np, "temperature", 80);
363 debug("id %d polling_delay %d, critical %d, alert %d\n",
364 pdata->id, pdata->polling_delay, pdata->critical, pdata->alert);
369 static int imx_tmu_probe(struct udevice *dev)
371 struct imx_tmu_plat *pdata = dev_get_platdata(dev);
374 ret = imx_tmu_parse_fdt(dev);
376 printf("Error in parsing TMU FDT %d\n", ret);
380 if (pdata->zone_node) {
382 imx_tmu_calibration(dev);
384 imx_tmu_enable_msite(dev);
390 static const struct udevice_id imx_tmu_ids[] = {
391 { .compatible = "fsl,imx8mq-tmu", },
392 { .compatible = "fsl,imx8mm-tmu", .data = FLAGS_VER2, },
396 U_BOOT_DRIVER(imx_tmu) = {
398 .id = UCLASS_THERMAL,
400 .of_match = imx_tmu_ids,
401 .bind = imx_tmu_bind,
402 .probe = imx_tmu_probe,
403 .platdata_auto_alloc_size = sizeof(struct imx_tmu_plat),
404 .flags = DM_FLAG_PRE_RELOC,