drivers/staging/vt6655/mac.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * File: mac.h
   7  *
   8  * Purpose: MAC routines
   9  *
  10  * Author: Tevin Chen
  11  *
  12  * Date: May 21, 1996
  13  *
  14  * Revision History:
  15  *      07-01-2003 Bryan YC Fan:  Re-write codes to support VT3253 spec.
  16  *      08-25-2003 Kyle Hsu:      Porting MAC functions from sim53.
  17  *      09-03-2003 Bryan YC Fan:  Add MACvDisableProtectMD & MACvEnableProtectMD
  18  */
  19
  20 #ifndef __MAC_H__
  21 #define __MAC_H__
  22
  23 #include "tmacro.h"
  24 #include "upc.h"
  25
  26 /*---------------------  Export Definitions -------------------------*/
  27 /* Registers in the MAC */
  28 #define MAC_MAX_CONTEXT_SIZE_PAGE0  256
  29 #define MAC_MAX_CONTEXT_SIZE_PAGE1  128
  30
  31 /* Registers not related to 802.11b */
  32 #define MAC_REG_BCFG0       0x00
  33 #define MAC_REG_BCFG1       0x01
  34 #define MAC_REG_FCR0        0x02
  35 #define MAC_REG_FCR1        0x03
  36 #define MAC_REG_BISTCMD     0x04
  37 #define MAC_REG_BISTSR0     0x05
  38 #define MAC_REG_BISTSR1     0x06
  39 #define MAC_REG_BISTSR2     0x07
  40 #define MAC_REG_I2MCSR      0x08
  41 #define MAC_REG_I2MTGID     0x09
  42 #define MAC_REG_I2MTGAD     0x0A
  43 #define MAC_REG_I2MCFG      0x0B
  44 #define MAC_REG_I2MDIPT     0x0C
  45 #define MAC_REG_I2MDOPT     0x0E
  46 #define MAC_REG_PMC0        0x10
  47 #define MAC_REG_PMC1        0x11
  48 #define MAC_REG_STICKHW     0x12
  49 #define MAC_REG_LOCALID     0x14
  50 #define MAC_REG_TESTCFG     0x15
  51 #define MAC_REG_JUMPER0     0x16
  52 #define MAC_REG_JUMPER1     0x17
  53 #define MAC_REG_TMCTL0      0x18
  54 #define MAC_REG_TMCTL1      0x19
  55 #define MAC_REG_TMDATA0     0x1C
  56
  57 /* MAC Parameter related */
  58 #define MAC_REG_LRT         0x20
  59 #define MAC_REG_SRT         0x21
  60 #define MAC_REG_SIFS        0x22
  61 #define MAC_REG_DIFS        0x23
  62 #define MAC_REG_EIFS        0x24
  63 #define MAC_REG_SLOT        0x25
  64 #define MAC_REG_BI          0x26
  65 #define MAC_REG_CWMAXMIN0   0x28
  66 #define MAC_REG_LINKOFFTOTM 0x2A
  67 #define MAC_REG_SWTMOT      0x2B
  68 #define MAC_REG_MIBCNTR     0x2C
  69 #define MAC_REG_RTSOKCNT    0x2C
  70 #define MAC_REG_RTSFAILCNT  0x2D
  71 #define MAC_REG_ACKFAILCNT  0x2E
  72 #define MAC_REG_FCSERRCNT   0x2F
  73
  74 /* TSF Related */
  75 #define MAC_REG_TSFCNTR     0x30
  76 #define MAC_REG_NEXTTBTT    0x38
  77 #define MAC_REG_TSFOFST     0x40
  78 #define MAC_REG_TFTCTL      0x48
  79
  80 /* WMAC Control/Status Related */
  81 #define MAC_REG_ENCFG       0x4C
  82 #define MAC_REG_PAGE1SEL    0x4F
  83 #define MAC_REG_CFG         0x50
  84 #define MAC_REG_TEST        0x52
  85 #define MAC_REG_HOSTCR      0x54
  86 #define MAC_REG_MACCR       0x55
  87 #define MAC_REG_RCR         0x56
  88 #define MAC_REG_TCR         0x57
  89 #define MAC_REG_IMR         0x58
  90 #define MAC_REG_ISR         0x5C
  91
  92 /* Power Saving Related */
  93 #define MAC_REG_PSCFG       0x60
  94 #define MAC_REG_PSCTL       0x61
  95 #define MAC_REG_PSPWRSIG    0x62
  96 #define MAC_REG_BBCR13      0x63
  97 #define MAC_REG_AIDATIM     0x64
  98 #define MAC_REG_PWBT        0x66
  99 #define MAC_REG_WAKEOKTMR   0x68
 100 #define MAC_REG_CALTMR      0x69
 101 #define MAC_REG_SYNSPACCNT  0x6A
 102 #define MAC_REG_WAKSYNOPT   0x6B
 103
 104 /* Baseband/IF Control Group */
 105 #define MAC_REG_BBREGCTL    0x6C
 106 #define MAC_REG_CHANNEL     0x6D
 107 #define MAC_REG_BBREGADR    0x6E
 108 #define MAC_REG_BBREGDATA   0x6F
 109 #define MAC_REG_IFREGCTL    0x70
 110 #define MAC_REG_IFDATA      0x71
 111 #define MAC_REG_ITRTMSET    0x74
 112 #define MAC_REG_PAPEDELAY   0x77
 113 #define MAC_REG_SOFTPWRCTL  0x78
 114 #define MAC_REG_GPIOCTL0    0x7A
 115 #define MAC_REG_GPIOCTL1    0x7B
 116
 117 /* MAC DMA Related Group */
 118 #define MAC_REG_TXDMACTL0   0x7C
 119 #define MAC_REG_TXDMAPTR0   0x80
 120 #define MAC_REG_AC0DMACTL   0x84
 121 #define MAC_REG_AC0DMAPTR   0x88
 122 #define MAC_REG_BCNDMACTL   0x8C
 123 #define MAC_REG_BCNDMAPTR   0x90
 124 #define MAC_REG_RXDMACTL0   0x94
 125 #define MAC_REG_RXDMAPTR0   0x98
 126 #define MAC_REG_RXDMACTL1   0x9C
 127 #define MAC_REG_RXDMAPTR1   0xA0
 128 #define MAC_REG_SYNCDMACTL  0xA4
 129 #define MAC_REG_SYNCDMAPTR  0xA8
 130 #define MAC_REG_ATIMDMACTL  0xAC
 131 #define MAC_REG_ATIMDMAPTR  0xB0
 132
 133 /* MiscFF PIO related */
 134 #define MAC_REG_MISCFFNDEX  0xB4
 135 #define MAC_REG_MISCFFCTL   0xB6
 136 #define MAC_REG_MISCFFDATA  0xB8
 137
 138 /* Extend SW Timer */
 139 #define MAC_REG_TMDATA1     0xBC
 140
 141 /* WOW Related Group */
 142 #define MAC_REG_WAKEUPEN0   0xC0
 143 #define MAC_REG_WAKEUPEN1   0xC1
 144 #define MAC_REG_WAKEUPSR0   0xC2
 145 #define MAC_REG_WAKEUPSR1   0xC3
 146 #define MAC_REG_WAKE128_0   0xC4
 147 #define MAC_REG_WAKE128_1   0xD4
 148 #define MAC_REG_WAKE128_2   0xE4
 149 #define MAC_REG_WAKE128_3   0xF4
 150
 151 /************** Page 1 ******************/
 152 #define MAC_REG_CRC_128_0   0x04
 153 #define MAC_REG_CRC_128_1   0x06
 154 #define MAC_REG_CRC_128_2   0x08
 155 #define MAC_REG_CRC_128_3   0x0A
 156
 157 /* MAC Configuration Group */
 158 #define MAC_REG_PAR0        0x0C
 159 #define MAC_REG_PAR4        0x10
 160 #define MAC_REG_BSSID0      0x14
 161 #define MAC_REG_BSSID4      0x18
 162 #define MAC_REG_MAR0        0x1C
 163 #define MAC_REG_MAR4        0x20
 164
 165 /* MAC RSPPKT INFO Group */
 166 #define MAC_REG_RSPINF_B_1  0x24
 167 #define MAC_REG_RSPINF_B_2  0x28
 168 #define MAC_REG_RSPINF_B_5  0x2C
 169 #define MAC_REG_RSPINF_B_11 0x30
 170 #define MAC_REG_RSPINF_A_6  0x34
 171 #define MAC_REG_RSPINF_A_9  0x36
 172 #define MAC_REG_RSPINF_A_12 0x38
 173 #define MAC_REG_RSPINF_A_18 0x3A
 174 #define MAC_REG_RSPINF_A_24 0x3C
 175 #define MAC_REG_RSPINF_A_36 0x3E
 176 #define MAC_REG_RSPINF_A_48 0x40
 177 #define MAC_REG_RSPINF_A_54 0x42
 178 #define MAC_REG_RSPINF_A_72 0x44
 179
 180 /* 802.11h relative */
 181 #define MAC_REG_QUIETINIT   0x60
 182 #define MAC_REG_QUIETGAP    0x62
 183 #define MAC_REG_QUIETDUR    0x64
 184 #define MAC_REG_MSRCTL      0x66
 185 #define MAC_REG_MSRBBSTS    0x67
 186 #define MAC_REG_MSRSTART    0x68
 187 #define MAC_REG_MSRDURATION 0x70
 188 #define MAC_REG_CCAFRACTION 0x72
 189 #define MAC_REG_PWRCCK      0x73
 190 #define MAC_REG_PWROFDM     0x7C
 191
 192 /* Bits in the BCFG0 register */
 193 #define BCFG0_PERROFF       0x40
 194 #define BCFG0_MRDMDIS       0x20
 195 #define BCFG0_MRDLDIS       0x10
 196 #define BCFG0_MWMEN         0x08
 197 #define BCFG0_VSERREN       0x02
 198 #define BCFG0_LATMEN        0x01
 199
 200 /* Bits in the BCFG1 register */
 201 #define BCFG1_CFUNOPT       0x80
 202 #define BCFG1_CREQOPT       0x40
 203 #define BCFG1_DMA8          0x10
 204 #define BCFG1_ARBITOPT      0x08
 205 #define BCFG1_PCIMEN        0x04
 206 #define BCFG1_MIOEN         0x02
 207 #define BCFG1_CISDLYEN      0x01
 208
 209 /* Bits in RAMBIST registers */
 210 #define BISTCMD_TSTPAT5     0x00
 211 #define BISTCMD_TSTPATA     0x80
 212 #define BISTCMD_TSTERR      0x20
 213 #define BISTCMD_TSTPATF     0x18
 214 #define BISTCMD_TSTPAT0     0x10
 215 #define BISTCMD_TSTMODE     0x04
 216 #define BISTCMD_TSTITTX     0x03
 217 #define BISTCMD_TSTATRX     0x02
 218 #define BISTCMD_TSTATTX     0x01
 219 #define BISTCMD_TSTRX       0x00
 220 #define BISTSR0_BISTGO      0x01
 221 #define BISTSR1_TSTSR       0x01
 222 #define BISTSR2_CMDPRTEN    0x02
 223 #define BISTSR2_RAMTSTEN    0x01
 224
 225 /* Bits in the I2MCFG EEPROM register */
 226 #define I2MCFG_BOUNDCTL     0x80
 227 #define I2MCFG_WAITCTL      0x20
 228 #define I2MCFG_SCLOECTL     0x10
 229 #define I2MCFG_WBUSYCTL     0x08
 230 #define I2MCFG_NORETRY      0x04
 231 #define I2MCFG_I2MLDSEQ     0x02
 232 #define I2MCFG_I2CMFAST     0x01
 233
 234 /* Bits in the I2MCSR EEPROM register */
 235 #define I2MCSR_EEMW         0x80
 236 #define I2MCSR_EEMR         0x40
 237 #define I2MCSR_AUTOLD       0x08
 238 #define I2MCSR_NACK         0x02
 239 #define I2MCSR_DONE         0x01
 240
 241 /* Bits in the PMC1 register */
 242 #define SPS_RST             0x80
 243 #define PCISTIKY            0x40
 244 #define PME_OVR             0x02
 245
 246 /* Bits in the STICKYHW register */
 247 #define STICKHW_DS1_SHADOW  0x02
 248 #define STICKHW_DS0_SHADOW  0x01
 249
 250 /* Bits in the TMCTL register */
 251 #define TMCTL_TSUSP         0x04
 252 #define TMCTL_TMD           0x02
 253 #define TMCTL_TE            0x01
 254
 255 /* Bits in the TFTCTL register */
 256 #define TFTCTL_HWUTSF       0x80
 257 #define TFTCTL_TBTTSYNC     0x40
 258 #define TFTCTL_HWUTSFEN     0x20
 259 #define TFTCTL_TSFCNTRRD    0x10
 260 #define TFTCTL_TBTTSYNCEN   0x08
 261 #define TFTCTL_TSFSYNCEN    0x04
 262 #define TFTCTL_TSFCNTRST    0x02
 263 #define TFTCTL_TSFCNTREN    0x01
 264
 265 /* Bits in the EnhanceCFG register */
 266 #define EnCFG_BarkerPream   0x00020000
 267 #define EnCFG_NXTBTTCFPSTR  0x00010000
 268 #define EnCFG_BcnSusClr     0x00000200
 269 #define EnCFG_BcnSusInd     0x00000100
 270 #define EnCFG_CFP_ProtectEn 0x00000040
 271 #define EnCFG_ProtectMd     0x00000020
 272 #define EnCFG_HwParCFP      0x00000010
 273 #define EnCFG_CFNULRSP      0x00000004
 274 #define EnCFG_BBType_MASK   0x00000003
 275 #define EnCFG_BBType_g      0x00000002
 276 #define EnCFG_BBType_b      0x00000001
 277 #define EnCFG_BBType_a      0x00000000
 278
 279 /* Bits in the Page1Sel register */
 280 #define PAGE1_SEL           0x01
 281
 282 /* Bits in the CFG register */
 283 #define CFG_TKIPOPT         0x80
 284 #define CFG_RXDMAOPT        0x40
 285 #define CFG_TMOT_SW         0x20
 286 #define CFG_TMOT_HWLONG     0x10
 287 #define CFG_TMOT_HW         0x00
 288 #define CFG_CFPENDOPT       0x08
 289 #define CFG_BCNSUSEN        0x04
 290 #define CFG_NOTXTIMEOUT     0x02
 291 #define CFG_NOBUFOPT        0x01
 292
 293 /* Bits in the TEST register */
 294 #define TEST_LBEXT          0x80
 295 #define TEST_LBINT          0x40
 296 #define TEST_LBNONE         0x00
 297 #define TEST_SOFTINT        0x20
 298 #define TEST_CONTTX         0x10
 299 #define TEST_TXPE           0x08
 300 #define TEST_NAVDIS         0x04
 301 #define TEST_NOCTS          0x02
 302 #define TEST_NOACK          0x01
 303
 304 /* Bits in the HOSTCR register */
 305 #define HOSTCR_TXONST       0x80
 306 #define HOSTCR_RXONST       0x40
 307 #define HOSTCR_ADHOC        0x20 /* Network Type 1 = Ad-hoc */
 308 #define HOSTCR_AP           0x10 /* Port Type 1 = AP */
 309 #define HOSTCR_TXON         0x08 /* 0000 1000 */
 310 #define HOSTCR_RXON         0x04 /* 0000 0100 */
 311 #define HOSTCR_MACEN        0x02 /* 0000 0010 */
 312 #define HOSTCR_SOFTRST      0x01 /* 0000 0001 */
 313
 314 /* Bits in the MACCR register */
 315 #define MACCR_SYNCFLUSHOK   0x04
 316 #define MACCR_SYNCFLUSH     0x02
 317 #define MACCR_CLRNAV        0x01
 318
 319 /* Bits in the MAC_REG_GPIOCTL0 register */
 320 #define LED_ACTSET           0x01
 321 #define LED_RFOFF            0x02
 322 #define LED_NOCONNECT        0x04
 323
 324 /* Bits in the RCR register */
 325 #define RCR_SSID            0x80
 326 #define RCR_RXALLTYPE       0x40
 327 #define RCR_UNICAST         0x20
 328 #define RCR_BROADCAST       0x10
 329 #define RCR_MULTICAST       0x08
 330 #define RCR_WPAERR          0x04
 331 #define RCR_ERRCRC          0x02
 332 #define RCR_BSSID           0x01
 333
 334 /* Bits in the TCR register */
 335 #define TCR_SYNCDCFOPT      0x02
 336 #define TCR_AUTOBCNTX       0x01 /* Beacon automatically transmit enable */
 337
 338 /* Bits in the IMR register */
 339 #define IMR_MEASURESTART    0x80000000
 340 #define IMR_QUIETSTART      0x20000000
 341 #define IMR_RADARDETECT     0x10000000
 342 #define IMR_MEASUREEND      0x08000000
 343 #define IMR_SOFTTIMER1      0x00200000
 344 #define IMR_RXDMA1          0x00001000 /* 0000 0000 0001 0000 0000 0000 */
 345 #define IMR_RXNOBUF         0x00000800
 346 #define IMR_MIBNEARFULL     0x00000400
 347 #define IMR_SOFTINT         0x00000200
 348 #define IMR_FETALERR        0x00000100
 349 #define IMR_WATCHDOG        0x00000080
 350 #define IMR_SOFTTIMER       0x00000040
 351 #define IMR_GPIO            0x00000020
 352 #define IMR_TBTT            0x00000010
 353 #define IMR_RXDMA0          0x00000008
 354 #define IMR_BNTX            0x00000004
 355 #define IMR_AC0DMA          0x00000002
 356 #define IMR_TXDMA0          0x00000001
 357
 358 /* Bits in the ISR register */
 359 #define ISR_MEASURESTART    0x80000000
 360 #define ISR_QUIETSTART      0x20000000
 361 #define ISR_RADARDETECT     0x10000000
 362 #define ISR_MEASUREEND      0x08000000
 363 #define ISR_SOFTTIMER1      0x00200000
 364 #define ISR_RXDMA1          0x00001000 /* 0000 0000 0001 0000 0000 0000 */
 365 #define ISR_RXNOBUF         0x00000800 /* 0000 0000 0000 1000 0000 0000 */
 366 #define ISR_MIBNEARFULL     0x00000400 /* 0000 0000 0000 0100 0000 0000 */
 367 #define ISR_SOFTINT         0x00000200
 368 #define ISR_FETALERR        0x00000100
 369 #define ISR_WATCHDOG        0x00000080
 370 #define ISR_SOFTTIMER       0x00000040
 371 #define ISR_GPIO            0x00000020
 372 #define ISR_TBTT            0x00000010
 373 #define ISR_RXDMA0          0x00000008
 374 #define ISR_BNTX            0x00000004
 375 #define ISR_AC0DMA          0x00000002
 376 #define ISR_TXDMA0          0x00000001
 377
 378 /* Bits in the PSCFG register */
 379 #define PSCFG_PHILIPMD      0x40
 380 #define PSCFG_WAKECALEN     0x20
 381 #define PSCFG_WAKETMREN     0x10
 382 #define PSCFG_BBPSPROG      0x08
 383 #define PSCFG_WAKESYN       0x04
 384 #define PSCFG_SLEEPSYN      0x02
 385 #define PSCFG_AUTOSLEEP     0x01
 386
 387 /* Bits in the PSCTL register */
 388 #define PSCTL_WAKEDONE      0x20
 389 #define PSCTL_PS            0x10
 390 #define PSCTL_GO2DOZE       0x08
 391 #define PSCTL_LNBCN         0x04
 392 #define PSCTL_ALBCN         0x02
 393 #define PSCTL_PSEN          0x01
 394
 395 /* Bits in the PSPWSIG register */
 396 #define PSSIG_WPE3          0x80
 397 #define PSSIG_WPE2          0x40
 398 #define PSSIG_WPE1          0x20
 399 #define PSSIG_WRADIOPE      0x10
 400 #define PSSIG_SPE3          0x08
 401 #define PSSIG_SPE2          0x04
 402 #define PSSIG_SPE1          0x02
 403 #define PSSIG_SRADIOPE      0x01
 404
 405 /* Bits in the BBREGCTL register */
 406 #define BBREGCTL_DONE       0x04
 407 #define BBREGCTL_REGR       0x02
 408 #define BBREGCTL_REGW       0x01
 409
 410 /* Bits in the IFREGCTL register */
 411 #define IFREGCTL_DONE       0x04
 412 #define IFREGCTL_IFRF       0x02
 413 #define IFREGCTL_REGW       0x01
 414
 415 /* Bits in the SOFTPWRCTL register */
 416 #define SOFTPWRCTL_RFLEOPT      0x0800
 417 #define SOFTPWRCTL_TXPEINV      0x0200
 418 #define SOFTPWRCTL_SWPECTI      0x0100
 419 #define SOFTPWRCTL_SWPAPE       0x0020
 420 #define SOFTPWRCTL_SWCALEN      0x0010
 421 #define SOFTPWRCTL_SWRADIO_PE   0x0008
 422 #define SOFTPWRCTL_SWPE2        0x0004
 423 #define SOFTPWRCTL_SWPE1        0x0002
 424 #define SOFTPWRCTL_SWPE3        0x0001
 425
 426 /* Bits in the GPIOCTL1 register */
 427 #define GPIO1_DATA1             0x20
 428 #define GPIO1_MD1               0x10
 429 #define GPIO1_DATA0             0x02
 430 #define GPIO1_MD0               0x01
 431
 432 /* Bits in the DMACTL register */
 433 #define DMACTL_CLRRUN       0x00080000
 434 #define DMACTL_RUN          0x00000008
 435 #define DMACTL_WAKE         0x00000004
 436 #define DMACTL_DEAD         0x00000002
 437 #define DMACTL_ACTIVE       0x00000001
 438
 439 /* Bits in the RXDMACTL0 register */
 440 #define RX_PERPKT           0x00000100
 441 #define RX_PERPKTCLR        0x01000000
 442
 443 /* Bits in the BCNDMACTL register */
 444 #define BEACON_READY        0x01
 445
 446 /* Bits in the MISCFFCTL register */
 447 #define MISCFFCTL_WRITE     0x0001
 448
 449 /* Bits in WAKEUPEN0 */
 450 #define WAKEUPEN0_DIRPKT    0x10
 451 #define WAKEUPEN0_LINKOFF   0x08
 452 #define WAKEUPEN0_ATIMEN    0x04
 453 #define WAKEUPEN0_TIMEN     0x02
 454 #define WAKEUPEN0_MAGICEN   0x01
 455
 456 /* Bits in WAKEUPEN1 */
 457 #define WAKEUPEN1_128_3     0x08
 458 #define WAKEUPEN1_128_2     0x04
 459 #define WAKEUPEN1_128_1     0x02
 460 #define WAKEUPEN1_128_0     0x01
 461
 462 /* Bits in WAKEUPSR0 */
 463 #define WAKEUPSR0_DIRPKT    0x10
 464 #define WAKEUPSR0_LINKOFF   0x08
 465 #define WAKEUPSR0_ATIMEN    0x04
 466 #define WAKEUPSR0_TIMEN     0x02
 467 #define WAKEUPSR0_MAGICEN   0x01
 468
 469 /* Bits in WAKEUPSR1 */
 470 #define WAKEUPSR1_128_3     0x08
 471 #define WAKEUPSR1_128_2     0x04
 472 #define WAKEUPSR1_128_1     0x02
 473 #define WAKEUPSR1_128_0     0x01
 474
 475 /* Bits in the MAC_REG_GPIOCTL register */
 476 #define GPIO0_MD            0x01
 477 #define GPIO0_DATA          0x02
 478 #define GPIO0_INTMD         0x04
 479 #define GPIO1_MD            0x10
 480 #define GPIO1_DATA          0x20
 481
 482 /* Bits in the MSRCTL register */
 483 #define MSRCTL_FINISH       0x80
 484 #define MSRCTL_READY        0x40
 485 #define MSRCTL_RADARDETECT  0x20
 486 #define MSRCTL_EN           0x10
 487 #define MSRCTL_QUIETTXCHK   0x08
 488 #define MSRCTL_QUIETRPT     0x04
 489 #define MSRCTL_QUIETINT     0x02
 490 #define MSRCTL_QUIETEN      0x01
 491
 492 /* Bits in the MSRCTL1 register */
 493 #define MSRCTL1_TXPWR       0x08
 494 #define MSRCTL1_CSAPAREN    0x04
 495 #define MSRCTL1_TXPAUSE     0x01
 496
 497 /* Loopback mode */
 498 #define MAC_LB_EXT          0x02
 499 #define MAC_LB_INTERNAL     0x01
 500 #define MAC_LB_NONE         0x00
 501
 502 #define Default_BI              0x200
 503
 504 /* MiscFIFO Offset */
 505 #define MISCFIFO_KEYETRY0       32
 506 #define MISCFIFO_KEYENTRYSIZE   22
 507 #define MISCFIFO_SYNINFO_IDX    10
 508 #define MISCFIFO_SYNDATA_IDX    11
 509 #define MISCFIFO_SYNDATASIZE    21
 510
 511 /* enabled mask value of irq */
 512 #define IMR_MASK_VALUE     (IMR_SOFTTIMER1 |    \
 513                             IMR_RXDMA1 |        \
 514                             IMR_RXNOBUF |       \
 515                             IMR_MIBNEARFULL |   \
 516                             IMR_SOFTINT |       \
 517                             IMR_FETALERR |      \
 518                             IMR_WATCHDOG |      \
 519                             IMR_SOFTTIMER |     \
 520                             IMR_GPIO |          \
 521                             IMR_TBTT |          \
 522                             IMR_RXDMA0 |        \
 523                             IMR_BNTX |          \
 524                             IMR_AC0DMA |        \
 525                             IMR_TXDMA0)
 526
 527 /* max time out delay time */
 528 #define W_MAX_TIMEOUT       0xFFF0U
 529
 530 /* wait time within loop */
 531 #define CB_DELAY_LOOP_WAIT  10 /* 10ms */
 532
 533 /* revision id */
 534 #define REV_ID_VT3253_A0    0x00
 535 #define REV_ID_VT3253_A1    0x01
 536 #define REV_ID_VT3253_B0    0x08
 537 #define REV_ID_VT3253_B1    0x09
 538
 539 /*---------------------  Export Types  ------------------------------*/
 540
 541 /*---------------------  Export Macros ------------------------------*/
 542
 543 #define MACvRegBitsOn(iobase, byRegOfs, byBits)                 \
 544 do {                                                                    \
 545         unsigned char byData;                                           \
 546         VNSvInPortB(iobase + byRegOfs, &byData);                        \
 547         VNSvOutPortB(iobase + byRegOfs, byData | (byBits));             \
 548 } while (0)
 549
 550 #define MACvWordRegBitsOn(iobase, byRegOfs, wBits)                      \
 551 do {                                                                    \
 552         unsigned short wData;                                           \
 553         VNSvInPortW(iobase + byRegOfs, &wData);                 \
 554         VNSvOutPortW(iobase + byRegOfs, wData | (wBits));               \
 555 } while (0)
 556
 557 #define MACvDWordRegBitsOn(iobase, byRegOfs, dwBits)                    \
 558 do {                                                                    \
 559         unsigned long dwData;                                           \
 560         VNSvInPortD(iobase + byRegOfs, &dwData);                        \
 561         VNSvOutPortD(iobase + byRegOfs, dwData | (dwBits));             \
 562 } while (0)
 563
 564 #define MACvRegBitsOnEx(iobase, byRegOfs, byMask, byBits)               \
 565 do {                                                                    \
 566         unsigned char byData;                                           \
 567         VNSvInPortB(iobase + byRegOfs, &byData);                        \
 568         byData &= byMask;                                               \
 569         VNSvOutPortB(iobase + byRegOfs, byData | (byBits));             \
 570 } while (0)
 571
 572 #define MACvRegBitsOff(iobase, byRegOfs, byBits)                        \
 573 do {                                                                    \
 574         unsigned char byData;                                           \
 575         VNSvInPortB(iobase + byRegOfs, &byData);                        \
 576         VNSvOutPortB(iobase + byRegOfs, byData & ~(byBits));            \
 577 } while (0)
 578
 579 #define MACvWordRegBitsOff(iobase, byRegOfs, wBits)                     \
 580 do {                                                                    \
 581         unsigned short wData;                                           \
 582         VNSvInPortW(iobase + byRegOfs, &wData);                 \
 583         VNSvOutPortW(iobase + byRegOfs, wData & ~(wBits));              \
 584 } while (0)
 585
 586 #define MACvDWordRegBitsOff(iobase, byRegOfs, dwBits)                   \
 587 do {                                                                    \
 588         unsigned long dwData;                                           \
 589         VNSvInPortD(iobase + byRegOfs, &dwData);                        \
 590         VNSvOutPortD(iobase + byRegOfs, dwData & ~(dwBits));            \
 591 } while (0)
 592
 593 #define MACvGetCurrRx0DescAddr(iobase, pdwCurrDescAddr) \
 594         VNSvInPortD(iobase + MAC_REG_RXDMAPTR0,         \
 595                     (unsigned long *)pdwCurrDescAddr)
 596
 597 #define MACvGetCurrRx1DescAddr(iobase, pdwCurrDescAddr) \
 598         VNSvInPortD(iobase + MAC_REG_RXDMAPTR1,         \
 599                     (unsigned long *)pdwCurrDescAddr)
 600
 601 #define MACvGetCurrTx0DescAddr(iobase, pdwCurrDescAddr) \
 602         VNSvInPortD(iobase + MAC_REG_TXDMAPTR0,         \
 603                     (unsigned long *)pdwCurrDescAddr)
 604
 605 #define MACvGetCurrAC0DescAddr(iobase, pdwCurrDescAddr) \
 606         VNSvInPortD(iobase + MAC_REG_AC0DMAPTR,         \
 607                     (unsigned long *)pdwCurrDescAddr)
 608
 609 #define MACvGetCurrSyncDescAddr(iobase, pdwCurrDescAddr)        \
 610         VNSvInPortD(iobase + MAC_REG_SYNCDMAPTR,                \
 611                     (unsigned long *)pdwCurrDescAddr)
 612
 613 #define MACvGetCurrATIMDescAddr(iobase, pdwCurrDescAddr)        \
 614         VNSvInPortD(iobase + MAC_REG_ATIMDMAPTR,                \
 615                     (unsigned long *)pdwCurrDescAddr)
 616
 617 /* set the chip with current BCN tx descriptor address */
 618 #define MACvSetCurrBCNTxDescAddr(iobase, dwCurrDescAddr)        \
 619         VNSvOutPortD(iobase + MAC_REG_BCNDMAPTR,                \
 620                      dwCurrDescAddr)
 621
 622 /* set the chip with current BCN length */
 623 #define MACvSetCurrBCNLength(iobase, wCurrBCNLength)            \
 624         VNSvOutPortW(iobase + MAC_REG_BCNDMACTL+2,              \
 625                      wCurrBCNLength)
 626
 627 #define MACvReadBSSIDAddress(iobase, pbyEtherAddr)              \
 628 do {                                                            \
 629         VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1);             \
 630         VNSvInPortB(iobase + MAC_REG_BSSID0,                    \
 631                     (unsigned char *)pbyEtherAddr);             \
 632         VNSvInPortB(iobase + MAC_REG_BSSID0 + 1,                \
 633                     pbyEtherAddr + 1);                          \
 634         VNSvInPortB(iobase + MAC_REG_BSSID0 + 2,                \
 635                     pbyEtherAddr + 2);                          \
 636         VNSvInPortB(iobase + MAC_REG_BSSID0 + 3,                \
 637                     pbyEtherAddr + 3);                          \
 638         VNSvInPortB(iobase + MAC_REG_BSSID0 + 4,                \
 639                     pbyEtherAddr + 4);                          \
 640         VNSvInPortB(iobase + MAC_REG_BSSID0 + 5,                \
 641                     pbyEtherAddr + 5);                          \
 642         VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0);             \
 643 } while (0)
 644
 645 #define MACvWriteBSSIDAddress(iobase, pbyEtherAddr)             \
 646 do {                                                            \
 647         VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1);             \
 648         VNSvOutPortB(iobase + MAC_REG_BSSID0,                   \
 649                      *(pbyEtherAddr));                          \
 650         VNSvOutPortB(iobase + MAC_REG_BSSID0 + 1,               \
 651                      *(pbyEtherAddr + 1));                      \
 652         VNSvOutPortB(iobase + MAC_REG_BSSID0 + 2,               \
 653                      *(pbyEtherAddr + 2));                      \
 654         VNSvOutPortB(iobase + MAC_REG_BSSID0 + 3,               \
 655                      *(pbyEtherAddr + 3));                      \
 656         VNSvOutPortB(iobase + MAC_REG_BSSID0 + 4,               \
 657                      *(pbyEtherAddr + 4));                      \
 658         VNSvOutPortB(iobase + MAC_REG_BSSID0 + 5,               \
 659                      *(pbyEtherAddr + 5));                      \
 660         VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0);             \
 661 } while (0)
 662
 663 #define MACvReadEtherAddress(iobase, pbyEtherAddr)              \
 664 do {                                                            \
 665         VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1);             \
 666         VNSvInPortB(iobase + MAC_REG_PAR0,                      \
 667                     (unsigned char *)pbyEtherAddr);             \
 668         VNSvInPortB(iobase + MAC_REG_PAR0 + 1,          \
 669                     pbyEtherAddr + 1);                          \
 670         VNSvInPortB(iobase + MAC_REG_PAR0 + 2,          \
 671                     pbyEtherAddr + 2);                          \
 672         VNSvInPortB(iobase + MAC_REG_PAR0 + 3,          \
 673                     pbyEtherAddr + 3);                          \
 674         VNSvInPortB(iobase + MAC_REG_PAR0 + 4,          \
 675                     pbyEtherAddr + 4);                          \
 676         VNSvInPortB(iobase + MAC_REG_PAR0 + 5,          \
 677                     pbyEtherAddr + 5);                          \
 678         VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0);             \
 679 } while (0)
 680
 681 #define MACvWriteEtherAddress(iobase, pbyEtherAddr)             \
 682 do {                                                            \
 683         VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1);             \
 684         VNSvOutPortB(iobase + MAC_REG_PAR0,                     \
 685                      *pbyEtherAddr);                            \
 686         VNSvOutPortB(iobase + MAC_REG_PAR0 + 1,         \
 687                      *(pbyEtherAddr + 1));                      \
 688         VNSvOutPortB(iobase + MAC_REG_PAR0 + 2,         \
 689                      *(pbyEtherAddr + 2));                      \
 690         VNSvOutPortB(iobase + MAC_REG_PAR0 + 3,         \
 691                      *(pbyEtherAddr + 3));                      \
 692         VNSvOutPortB(iobase + MAC_REG_PAR0 + 4,         \
 693                      *(pbyEtherAddr + 4));                      \
 694         VNSvOutPortB(iobase + MAC_REG_PAR0 + 5,         \
 695                      *(pbyEtherAddr + 5));                      \
 696         VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0);             \
 697 } while (0)
 698
 699 #define MACvClearISR(iobase)                                            \
 700         VNSvOutPortD(iobase + MAC_REG_ISR, IMR_MASK_VALUE)
 701
 702 #define MACvStart(iobase)                                               \
 703         VNSvOutPortB(iobase + MAC_REG_HOSTCR,                           \
 704                      (HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON))
 705
 706 #define MACvRx0PerPktMode(iobase)                                       \
 707         VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, RX_PERPKT)
 708
 709 #define MACvRx0BufferFillMode(iobase)                                   \
 710         VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, RX_PERPKTCLR)
 711
 712 #define MACvRx1PerPktMode(iobase)                                       \
 713         VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, RX_PERPKT)
 714
 715 #define MACvRx1BufferFillMode(iobase)                                   \
 716         VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, RX_PERPKTCLR)
 717
 718 #define MACvRxOn(iobase)                                                \
 719         MACvRegBitsOn(iobase, MAC_REG_HOSTCR, HOSTCR_RXON)
 720
 721 #define MACvReceive0(iobase)                                            \
 722 do {                                                                    \
 723         unsigned long dwData;                                           \
 724         VNSvInPortD(iobase + MAC_REG_RXDMACTL0, &dwData);               \
 725         if (dwData & DMACTL_RUN)                                        \
 726                 VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, DMACTL_WAKE); \
 727         else                                                            \
 728                 VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, DMACTL_RUN); \
 729 } while (0)
 730
 731 #define MACvReceive1(iobase)                                            \
 732 do {                                                                    \
 733         unsigned long dwData;                                           \
 734         VNSvInPortD(iobase + MAC_REG_RXDMACTL1, &dwData);               \
 735         if (dwData & DMACTL_RUN)                                        \
 736                 VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, DMACTL_WAKE); \
 737         else                                                            \
 738                 VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, DMACTL_RUN); \
 739 } while (0)
 740
 741 #define MACvTxOn(iobase)                                                \
 742         MACvRegBitsOn(iobase, MAC_REG_HOSTCR, HOSTCR_TXON)
 743
 744 #define MACvTransmit0(iobase)                                           \
 745 do {                                                                    \
 746         unsigned long dwData;                                           \
 747         VNSvInPortD(iobase + MAC_REG_TXDMACTL0, &dwData);               \
 748         if (dwData & DMACTL_RUN)                                        \
 749                 VNSvOutPortD(iobase + MAC_REG_TXDMACTL0, DMACTL_WAKE); \
 750         else                                                            \
 751                 VNSvOutPortD(iobase + MAC_REG_TXDMACTL0, DMACTL_RUN); \
 752 } while (0)
 753
 754 #define MACvTransmitAC0(iobase)                                 \
 755 do {                                                                    \
 756         unsigned long dwData;                                           \
 757         VNSvInPortD(iobase + MAC_REG_AC0DMACTL, &dwData);               \
 758         if (dwData & DMACTL_RUN)                                        \
 759                 VNSvOutPortD(iobase + MAC_REG_AC0DMACTL, DMACTL_WAKE); \
 760         else                                                            \
 761                 VNSvOutPortD(iobase + MAC_REG_AC0DMACTL, DMACTL_RUN); \
 762 } while (0)
 763
 764 #define MACvTransmitSYNC(iobase)                                        \
 765 do {                                                                    \
 766         unsigned long dwData;                                           \
 767         VNSvInPortD(iobase + MAC_REG_SYNCDMACTL, &dwData);              \
 768         if (dwData & DMACTL_RUN)                                        \
 769                 VNSvOutPortD(iobase + MAC_REG_SYNCDMACTL, DMACTL_WAKE); \
 770         else                                                            \
 771                 VNSvOutPortD(iobase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \
 772 } while (0)
 773
 774 #define MACvTransmitATIM(iobase)                                        \
 775 do {                                                                    \
 776         unsigned long dwData;                                           \
 777         VNSvInPortD(iobase + MAC_REG_ATIMDMACTL, &dwData);              \
 778         if (dwData & DMACTL_RUN)                                        \
 779                 VNSvOutPortD(iobase + MAC_REG_ATIMDMACTL, DMACTL_WAKE); \
 780         else                                                            \
 781                 VNSvOutPortD(iobase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \
 782 } while (0)
 783
 784 #define MACvTransmitBCN(iobase)                                 \
 785         VNSvOutPortB(iobase + MAC_REG_BCNDMACTL, BEACON_READY)
 786
 787 #define MACvClearStckDS(iobase)                                 \
 788 do {                                                                    \
 789         unsigned char byOrgValue;                                       \
 790         VNSvInPortB(iobase + MAC_REG_STICKHW, &byOrgValue);             \
 791         byOrgValue = byOrgValue & 0xFC;                                 \
 792         VNSvOutPortB(iobase + MAC_REG_STICKHW, byOrgValue);             \
 793 } while (0)
 794
 795 #define MACvReadISR(iobase, pdwValue)                           \
 796         VNSvInPortD(iobase + MAC_REG_ISR, pdwValue)
 797
 798 #define MACvWriteISR(iobase, dwValue)                           \
 799         VNSvOutPortD(iobase + MAC_REG_ISR, dwValue)
 800
 801 #define MACvIntEnable(iobase, dwMask)                           \
 802         VNSvOutPortD(iobase + MAC_REG_IMR, dwMask)
 803
 804 #define MACvIntDisable(iobase)                          \
 805         VNSvOutPortD(iobase + MAC_REG_IMR, 0)
 806
 807 #define MACvSelectPage0(iobase)                         \
 808                 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0)
 809
 810 #define MACvSelectPage1(iobase)                         \
 811         VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1)
 812
 813 #define MACvReadMIBCounter(iobase, pdwCounter)                  \
 814         VNSvInPortD(iobase + MAC_REG_MIBCNTR, pdwCounter)
 815
 816 #define MACvPwrEvntDisable(iobase)                                      \
 817         VNSvOutPortW(iobase + MAC_REG_WAKEUPEN0, 0x0000)
 818
 819 #define MACvEnableProtectMD(iobase)                                     \
 820 do {                                                                    \
 821         unsigned long dwOrgValue;                                       \
 822         VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue);               \
 823         dwOrgValue = dwOrgValue | EnCFG_ProtectMd;                      \
 824         VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue);               \
 825 } while (0)
 826
 827 #define MACvDisableProtectMD(iobase)                                    \
 828 do {                                                                    \
 829         unsigned long dwOrgValue;                                       \
 830         VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue);               \
 831         dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd;                     \
 832         VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue);               \
 833 } while (0)
 834
 835 #define MACvEnableBarkerPreambleMd(iobase)                              \
 836 do {                                                                    \
 837         unsigned long dwOrgValue;                                       \
 838         VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue);               \
 839         dwOrgValue = dwOrgValue | EnCFG_BarkerPream;                    \
 840         VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue);               \
 841 } while (0)
 842
 843 #define MACvDisableBarkerPreambleMd(iobase)                             \
 844 do {                                                                    \
 845         unsigned long dwOrgValue;                                       \
 846         VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue);               \
 847         dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream;                   \
 848         VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue);               \
 849 } while (0)
 850
 851 #define MACvSetBBType(iobase, byTyp)                                    \
 852 do {                                                                    \
 853         unsigned long dwOrgValue;                                       \
 854         VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue);               \
 855         dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK;                   \
 856         dwOrgValue = dwOrgValue | (unsigned long)byTyp;                 \
 857         VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue);               \
 858 } while (0)
 859
 860 #define MACvReadATIMW(iobase, pwCounter)                                \
 861         VNSvInPortW(iobase + MAC_REG_AIDATIM, pwCounter)
 862
 863 #define MACvWriteATIMW(iobase, wCounter)                                \
 864         VNSvOutPortW(iobase + MAC_REG_AIDATIM, wCounter)
 865
 866 #define MACvWriteCRC16_128(iobase, byRegOfs, wCRC)              \
 867 do {                                                            \
 868         VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1);             \
 869         VNSvOutPortW(iobase + byRegOfs, wCRC);          \
 870         VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0);             \
 871 } while (0)
 872
 873 #define MACvGPIOIn(iobase, pbyValue)                                    \
 874         VNSvInPortB(iobase + MAC_REG_GPIOCTL1, pbyValue)
 875
 876 #define MACvSetRFLE_LatchBase(iobase)                                 \
 877         MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT)
 878
 879 bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs,
 880                       unsigned char byTestBits);
 881
 882 bool MACbIsIntDisable(struct vnt_private *priv);
 883
 884 void MACvSetShortRetryLimit(struct vnt_private *priv,
 885                             unsigned char byRetryLimit);
 886
 887 void MACvSetLongRetryLimit(struct vnt_private *priv, unsigned char byRetryLimit);
 888
 889 void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode);
 890
 891 void MACvSaveContext(struct vnt_private *priv, unsigned char *pbyCxtBuf);
 892 void MACvRestoreContext(struct vnt_private *priv, unsigned char *pbyCxtBuf);
 893
 894 bool MACbSoftwareReset(struct vnt_private *priv);
 895 bool MACbSafeSoftwareReset(struct vnt_private *priv);
 896 bool MACbSafeRxOff(struct vnt_private *priv);
 897 bool MACbSafeTxOff(struct vnt_private *priv);
 898 bool MACbSafeStop(struct vnt_private *priv);
 899 bool MACbShutdown(struct vnt_private *priv);
 900 void MACvInitialize(struct vnt_private *priv);
 901 void MACvSetCurrRx0DescAddr(struct vnt_private *priv,
 902                             u32 curr_desc_addr);
 903 void MACvSetCurrRx1DescAddr(struct vnt_private *priv,
 904                             u32 curr_desc_addr);
 905 void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv,
 906                            u32 curr_desc_addr);
 907 void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv,
 908                               u32 curr_desc_addr);
 909 void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv,
 910                               u32 curr_desc_addr);
 911 void MACvSetCurrSyncDescAddrEx(struct vnt_private *priv,
 912                                u32 curr_desc_addr);
 913 void MACvSetCurrATIMDescAddrEx(struct vnt_private *priv,
 914                                u32 curr_desc_addr);
 915 void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay);
 916 void MACvOneShotTimer1MicroSec(struct vnt_private *priv, unsigned int uDelayTime);
 917
 918 void MACvSetMISCFifo(struct vnt_private *priv, unsigned short wOffset,
 919                      u32 dwData);
 920
 921 bool MACbPSWakeup(struct vnt_private *priv);
 922
 923 void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl,
 924                      unsigned int uEntryIdx, unsigned int uKeyIdx,
 925                      unsigned char *pbyAddr, u32 *pdwKey,
 926                      unsigned char byLocalID);
 927 void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx);
 928
 929 #endif /* __MAC_H__ */