1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
8 * Purpose: Implement functions to access baseband
15 * BBuGetFrameTime - Calculate data frame transmitting time
16 * BBvCalculateParameter - Calculate PhyLength, PhyService and Phy Signal
17 * parameter for baseband Tx
18 * BBbReadEmbedded - Embedded read baseband register via MAC
19 * BBbWriteEmbedded - Embedded write baseband register via MAC
20 * BBbVT3253Init - VIA VT3253 baseband chip init code
23 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
24 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
25 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and
26 * BBvCalculateParameter().
27 * cancel the setting of MAC_REG_SOFTPWRCTL on
30 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
31 * Modified BBvLoopbackOn & BBvLoopbackOff().
42 /*--------------------- Static Classes ----------------------------*/
44 /*--------------------- Static Variables --------------------------*/
46 /*--------------------- Static Functions --------------------------*/
48 /*--------------------- Export Variables --------------------------*/
50 /*--------------------- Static Definitions -------------------------*/
52 /*--------------------- Static Classes ----------------------------*/
54 /*--------------------- Static Variables --------------------------*/
56 #define CB_VT3253_INIT_FOR_RFMD 446
57 static const unsigned char byVT3253InitTab_RFMD[CB_VT3253_INIT_FOR_RFMD][2] = {
506 #define CB_VT3253B0_INIT_FOR_RFMD 256
507 static const unsigned char byVT3253B0_RFMD[CB_VT3253B0_INIT_FOR_RFMD][2] = {
766 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
769 unsigned char byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = {
967 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
970 unsigned char byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = {
1079 {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */
1229 #define CB_VT3253B0_INIT_FOR_UW2451 256
1231 static unsigned char byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = {
1340 {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */
1490 #define CB_VT3253B0_AGC 193
1492 static unsigned char byVT3253B0_AGC[CB_VT3253B0_AGC][2] = {
1688 static const unsigned short awcFrameTime[MAX_RATE] = {
1689 10, 20, 55, 110, 24, 36, 48, 72, 96, 144, 192, 216
1692 /*--------------------- Export Variables --------------------------*/
1694 * Description: Calculate data frame transmitting time
1698 * byPreambleType - Preamble Type
1699 * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1700 * cbFrameLength - Baseband Type
1704 * Return Value: FrameTime
1707 unsigned int BBuGetFrameTime(unsigned char byPreambleType,
1708 unsigned char byPktType,
1709 unsigned int cbFrameLength, unsigned short wRate)
1711 unsigned int uFrameTime;
1712 unsigned int uPreamble;
1714 unsigned int uRateIdx = (unsigned int)wRate;
1715 unsigned int uRate = 0;
1717 if (uRateIdx > RATE_54M)
1720 uRate = (unsigned int)awcFrameTime[uRateIdx];
1722 if (uRateIdx <= 3) { /* CCK mode */
1723 if (byPreambleType == 1) /* Short */
1728 uFrameTime = (cbFrameLength * 80) / uRate; /* ????? */
1729 uTmp = (uFrameTime * uRate) / 80;
1730 if (cbFrameLength != uTmp)
1733 return uPreamble + uFrameTime;
1735 uFrameTime = (cbFrameLength * 8 + 22) / uRate; /* ???????? */
1736 uTmp = ((uFrameTime * uRate) - 22) / 8;
1737 if (cbFrameLength != uTmp)
1740 uFrameTime = uFrameTime * 4; /* ??????? */
1741 if (byPktType != PK_TYPE_11A)
1742 uFrameTime += 6; /* ?????? */
1744 return 20 + uFrameTime; /* ?????? */
1748 * Description: Calculate Length, Service, and Signal fields of Phy for Tx
1752 * priv - Device Structure
1753 * frame_length - Tx Frame Length
1756 * struct vnt_phy_field *phy
1757 * - pointer to Phy Length field
1758 * - pointer to Phy Service field
1759 * - pointer to Phy Signal field
1761 * Return Value: none
1764 void vnt_get_phy_field(struct vnt_private *priv, u32 frame_length,
1765 u16 tx_rate, u8 pkt_type, struct vnt_phy_field *phy)
1771 u8 preamble_type = priv->byPreambleType;
1773 bit_count = frame_length * 8;
1784 count = bit_count / 2;
1786 if (preamble_type == 1)
1793 count = (bit_count * 10) / 55;
1794 tmp = (count * 55) / 10;
1796 if (tmp != bit_count)
1799 if (preamble_type == 1)
1806 count = bit_count / 11;
1809 if (tmp != bit_count) {
1812 if ((bit_count - tmp) <= 3)
1816 if (preamble_type == 1)
1823 if (pkt_type == PK_TYPE_11A)
1830 if (pkt_type == PK_TYPE_11A)
1837 if (pkt_type == PK_TYPE_11A)
1844 if (pkt_type == PK_TYPE_11A)
1851 if (pkt_type == PK_TYPE_11A)
1858 if (pkt_type == PK_TYPE_11A)
1865 if (pkt_type == PK_TYPE_11A)
1872 if (pkt_type == PK_TYPE_11A)
1878 if (pkt_type == PK_TYPE_11A)
1885 if (pkt_type == PK_TYPE_11B) {
1886 phy->service = 0x00;
1888 phy->service |= 0x80;
1889 phy->len = cpu_to_le16((u16)count);
1891 phy->service = 0x00;
1892 phy->len = cpu_to_le16((u16)frame_length);
1897 * Description: Read a byte from BASEBAND, by embedded programming
1901 * iobase - I/O base address
1902 * byBBAddr - address of register in Baseband
1904 * pbyData - data read
1906 * Return Value: true if succeeded; false if failed.
1909 bool BBbReadEmbedded(struct vnt_private *priv,
1910 unsigned char byBBAddr, unsigned char *pbyData)
1912 void __iomem *iobase = priv->PortOffset;
1914 unsigned char byValue;
1917 VNSvOutPortB(iobase + MAC_REG_BBREGADR, byBBAddr);
1920 MACvRegBitsOn(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGR);
1921 /* W_MAX_TIMEOUT is the timeout period */
1922 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1923 VNSvInPortB(iobase + MAC_REG_BBREGCTL, &byValue);
1924 if (byValue & BBREGCTL_DONE)
1929 VNSvInPortB(iobase + MAC_REG_BBREGDATA, pbyData);
1931 if (ww == W_MAX_TIMEOUT) {
1932 pr_debug(" DBG_PORT80(0x30)\n");
1939 * Description: Write a Byte to BASEBAND, by embedded programming
1943 * iobase - I/O base address
1944 * byBBAddr - address of register in Baseband
1945 * byData - data to write
1949 * Return Value: true if succeeded; false if failed.
1952 bool BBbWriteEmbedded(struct vnt_private *priv,
1953 unsigned char byBBAddr, unsigned char byData)
1955 void __iomem *iobase = priv->PortOffset;
1957 unsigned char byValue;
1960 VNSvOutPortB(iobase + MAC_REG_BBREGADR, byBBAddr);
1962 VNSvOutPortB(iobase + MAC_REG_BBREGDATA, byData);
1964 /* turn on BBREGCTL_REGW */
1965 MACvRegBitsOn(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGW);
1966 /* W_MAX_TIMEOUT is the timeout period */
1967 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1968 VNSvInPortB(iobase + MAC_REG_BBREGCTL, &byValue);
1969 if (byValue & BBREGCTL_DONE)
1973 if (ww == W_MAX_TIMEOUT) {
1974 pr_debug(" DBG_PORT80(0x31)\n");
1981 * Description: VIA VT3253 Baseband chip init function
1985 * iobase - I/O base address
1986 * byRevId - Revision ID
1987 * byRFType - RF type
1991 * Return Value: true if succeeded; false if failed.
1995 bool BBbVT3253Init(struct vnt_private *priv)
1997 bool bResult = true;
1999 void __iomem *iobase = priv->PortOffset;
2000 unsigned char byRFType = priv->byRFType;
2001 unsigned char byLocalID = priv->byLocalID;
2003 if (byRFType == RF_RFMD2959) {
2004 if (byLocalID <= REV_ID_VT3253_A1) {
2005 for (ii = 0; ii < CB_VT3253_INIT_FOR_RFMD; ii++)
2006 bResult &= BBbWriteEmbedded(priv,
2007 byVT3253InitTab_RFMD[ii][0],
2008 byVT3253InitTab_RFMD[ii][1]);
2011 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_RFMD; ii++)
2012 bResult &= BBbWriteEmbedded(priv,
2013 byVT3253B0_RFMD[ii][0],
2014 byVT3253B0_RFMD[ii][1]);
2016 for (ii = 0; ii < CB_VT3253B0_AGC_FOR_RFMD2959; ii++)
2017 bResult &= BBbWriteEmbedded(priv,
2018 byVT3253B0_AGC4_RFMD2959[ii][0],
2019 byVT3253B0_AGC4_RFMD2959[ii][1]);
2021 VNSvOutPortD(iobase + MAC_REG_ITRTMSET, 0x23);
2022 MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0));
2024 priv->abyBBVGA[0] = 0x18;
2025 priv->abyBBVGA[1] = 0x0A;
2026 priv->abyBBVGA[2] = 0x0;
2027 priv->abyBBVGA[3] = 0x0;
2028 priv->ldBmThreshold[0] = -70;
2029 priv->ldBmThreshold[1] = -50;
2030 priv->ldBmThreshold[2] = 0;
2031 priv->ldBmThreshold[3] = 0;
2032 } else if ((byRFType == RF_AIROHA) || (byRFType == RF_AL2230S)) {
2033 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2034 bResult &= BBbWriteEmbedded(priv,
2035 byVT3253B0_AIROHA2230[ii][0],
2036 byVT3253B0_AIROHA2230[ii][1]);
2038 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2039 bResult &= BBbWriteEmbedded(priv,
2040 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2042 priv->abyBBVGA[0] = 0x1C;
2043 priv->abyBBVGA[1] = 0x10;
2044 priv->abyBBVGA[2] = 0x0;
2045 priv->abyBBVGA[3] = 0x0;
2046 priv->ldBmThreshold[0] = -70;
2047 priv->ldBmThreshold[1] = -48;
2048 priv->ldBmThreshold[2] = 0;
2049 priv->ldBmThreshold[3] = 0;
2050 } else if (byRFType == RF_UW2451) {
2051 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
2052 bResult &= BBbWriteEmbedded(priv,
2053 byVT3253B0_UW2451[ii][0],
2054 byVT3253B0_UW2451[ii][1]);
2056 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2057 bResult &= BBbWriteEmbedded(priv,
2058 byVT3253B0_AGC[ii][0],
2059 byVT3253B0_AGC[ii][1]);
2061 VNSvOutPortB(iobase + MAC_REG_ITRTMSET, 0x23);
2062 MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0));
2064 priv->abyBBVGA[0] = 0x14;
2065 priv->abyBBVGA[1] = 0x0A;
2066 priv->abyBBVGA[2] = 0x0;
2067 priv->abyBBVGA[3] = 0x0;
2068 priv->ldBmThreshold[0] = -60;
2069 priv->ldBmThreshold[1] = -50;
2070 priv->ldBmThreshold[2] = 0;
2071 priv->ldBmThreshold[3] = 0;
2072 } else if (byRFType == RF_UW2452) {
2073 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
2074 bResult &= BBbWriteEmbedded(priv,
2075 byVT3253B0_UW2451[ii][0],
2076 byVT3253B0_UW2451[ii][1]);
2078 /* Init ANT B select,
2079 * TX Config CR09 = 0x61->0x45,
2080 * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2083 /*bResult &= BBbWriteEmbedded(iobase,0x09,0x41);*/
2085 /* Init ANT B select,
2086 * RX Config CR10 = 0x28->0x2A,
2087 * 0x2A->0x28(VC1/VC2 define,
2088 * make the ANT_A, ANT_B inverted)
2091 /*bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/
2092 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2093 bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06);
2095 /* {{RobertYu:20050125, request by Jack */
2096 bResult &= BBbWriteEmbedded(priv, 0x90, 0x20);
2097 bResult &= BBbWriteEmbedded(priv, 0x97, 0xeb);
2100 /* {{RobertYu:20050221, request by Jack */
2101 bResult &= BBbWriteEmbedded(priv, 0xa6, 0x00);
2102 bResult &= BBbWriteEmbedded(priv, 0xa8, 0x30);
2104 bResult &= BBbWriteEmbedded(priv, 0xb0, 0x58);
2106 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2107 bResult &= BBbWriteEmbedded(priv,
2108 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2110 priv->abyBBVGA[0] = 0x14;
2111 priv->abyBBVGA[1] = 0x0A;
2112 priv->abyBBVGA[2] = 0x0;
2113 priv->abyBBVGA[3] = 0x0;
2114 priv->ldBmThreshold[0] = -60;
2115 priv->ldBmThreshold[1] = -50;
2116 priv->ldBmThreshold[2] = 0;
2117 priv->ldBmThreshold[3] = 0;
2120 } else if (byRFType == RF_VT3226) {
2121 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2122 bResult &= BBbWriteEmbedded(priv,
2123 byVT3253B0_AIROHA2230[ii][0],
2124 byVT3253B0_AIROHA2230[ii][1]);
2126 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2127 bResult &= BBbWriteEmbedded(priv,
2128 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2130 priv->abyBBVGA[0] = 0x1C;
2131 priv->abyBBVGA[1] = 0x10;
2132 priv->abyBBVGA[2] = 0x0;
2133 priv->abyBBVGA[3] = 0x0;
2134 priv->ldBmThreshold[0] = -70;
2135 priv->ldBmThreshold[1] = -48;
2136 priv->ldBmThreshold[2] = 0;
2137 priv->ldBmThreshold[3] = 0;
2138 /* Fix VT3226 DFC system timing issue */
2139 MACvSetRFLE_LatchBase(iobase);
2140 /* {{ RobertYu: 20050104 */
2141 } else if (byRFType == RF_AIROHA7230) {
2142 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2143 bResult &= BBbWriteEmbedded(priv,
2144 byVT3253B0_AIROHA2230[ii][0],
2145 byVT3253B0_AIROHA2230[ii][1]);
2147 /* {{ RobertYu:20050223, request by JerryChung */
2148 /* Init ANT B select,TX Config CR09 = 0x61->0x45,
2149 * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2151 /*bResult &= BBbWriteEmbedded(iobase,0x09,0x41);*/
2152 /* Init ANT B select,RX Config CR10 = 0x28->0x2A,
2153 * 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2155 /*bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/
2156 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2157 bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06);
2160 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2161 bResult &= BBbWriteEmbedded(priv,
2162 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2164 priv->abyBBVGA[0] = 0x1C;
2165 priv->abyBBVGA[1] = 0x10;
2166 priv->abyBBVGA[2] = 0x0;
2167 priv->abyBBVGA[3] = 0x0;
2168 priv->ldBmThreshold[0] = -70;
2169 priv->ldBmThreshold[1] = -48;
2170 priv->ldBmThreshold[2] = 0;
2171 priv->ldBmThreshold[3] = 0;
2174 /* No VGA Table now */
2175 priv->bUpdateBBVGA = false;
2176 priv->abyBBVGA[0] = 0x1C;
2179 if (byLocalID > REV_ID_VT3253_A1) {
2180 BBbWriteEmbedded(priv, 0x04, 0x7F);
2181 BBbWriteEmbedded(priv, 0x0D, 0x01);
2188 * Description: Set ShortSlotTime mode
2192 * priv - Device Structure
2196 * Return Value: none
2200 BBvSetShortSlotTime(struct vnt_private *priv)
2202 unsigned char byBBRxConf = 0;
2203 unsigned char byBBVGA = 0;
2205 BBbReadEmbedded(priv, 0x0A, &byBBRxConf); /* CR10 */
2207 if (priv->bShortSlotTime)
2208 byBBRxConf &= 0xDF; /* 1101 1111 */
2210 byBBRxConf |= 0x20; /* 0010 0000 */
2212 /* patch for 3253B0 Baseband with Cardbus module */
2213 BBbReadEmbedded(priv, 0xE7, &byBBVGA);
2214 if (byBBVGA == priv->abyBBVGA[0])
2215 byBBRxConf |= 0x20; /* 0010 0000 */
2217 BBbWriteEmbedded(priv, 0x0A, byBBRxConf); /* CR10 */
2220 void BBvSetVGAGainOffset(struct vnt_private *priv, unsigned char byData)
2222 unsigned char byBBRxConf = 0;
2224 BBbWriteEmbedded(priv, 0xE7, byData);
2226 BBbReadEmbedded(priv, 0x0A, &byBBRxConf); /* CR10 */
2227 /* patch for 3253B0 Baseband with Cardbus module */
2228 if (byData == priv->abyBBVGA[0])
2229 byBBRxConf |= 0x20; /* 0010 0000 */
2230 else if (priv->bShortSlotTime)
2231 byBBRxConf &= 0xDF; /* 1101 1111 */
2233 byBBRxConf |= 0x20; /* 0010 0000 */
2234 priv->byBBVGACurrent = byData;
2235 BBbWriteEmbedded(priv, 0x0A, byBBRxConf); /* CR10 */
2239 * Description: Baseband SoftwareReset
2243 * iobase - I/O base address
2247 * Return Value: none
2251 BBvSoftwareReset(struct vnt_private *priv)
2253 BBbWriteEmbedded(priv, 0x50, 0x40);
2254 BBbWriteEmbedded(priv, 0x50, 0);
2255 BBbWriteEmbedded(priv, 0x9C, 0x01);
2256 BBbWriteEmbedded(priv, 0x9C, 0);
2260 * Description: Baseband Power Save Mode ON
2264 * iobase - I/O base address
2268 * Return Value: none
2272 BBvPowerSaveModeON(struct vnt_private *priv)
2274 unsigned char byOrgData;
2276 BBbReadEmbedded(priv, 0x0D, &byOrgData);
2277 byOrgData |= BIT(0);
2278 BBbWriteEmbedded(priv, 0x0D, byOrgData);
2282 * Description: Baseband Power Save Mode OFF
2286 * iobase - I/O base address
2290 * Return Value: none
2294 BBvPowerSaveModeOFF(struct vnt_private *priv)
2296 unsigned char byOrgData;
2298 BBbReadEmbedded(priv, 0x0D, &byOrgData);
2299 byOrgData &= ~(BIT(0));
2300 BBbWriteEmbedded(priv, 0x0D, byOrgData);
2304 * Description: Set Tx Antenna mode
2308 * priv - Device Structure
2309 * byAntennaMode - Antenna Mode
2313 * Return Value: none
2318 BBvSetTxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode)
2320 unsigned char byBBTxConf;
2322 BBbReadEmbedded(priv, 0x09, &byBBTxConf); /* CR09 */
2323 if (byAntennaMode == ANT_DIVERSITY) {
2324 /* bit 1 is diversity */
2326 } else if (byAntennaMode == ANT_A) {
2327 /* bit 2 is ANTSEL */
2328 byBBTxConf &= 0xF9; /* 1111 1001 */
2329 } else if (byAntennaMode == ANT_B) {
2330 byBBTxConf &= 0xFD; /* 1111 1101 */
2333 BBbWriteEmbedded(priv, 0x09, byBBTxConf); /* CR09 */
2337 * Description: Set Rx Antenna mode
2341 * priv - Device Structure
2342 * byAntennaMode - Antenna Mode
2346 * Return Value: none
2351 BBvSetRxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode)
2353 unsigned char byBBRxConf;
2355 BBbReadEmbedded(priv, 0x0A, &byBBRxConf); /* CR10 */
2356 if (byAntennaMode == ANT_DIVERSITY) {
2359 } else if (byAntennaMode == ANT_A) {
2360 byBBRxConf &= 0xFC; /* 1111 1100 */
2361 } else if (byAntennaMode == ANT_B) {
2362 byBBRxConf &= 0xFE; /* 1111 1110 */
2365 BBbWriteEmbedded(priv, 0x0A, byBBRxConf); /* CR10 */
2369 * Description: BBvSetDeepSleep
2373 * priv - Device Structure
2377 * Return Value: none
2381 BBvSetDeepSleep(struct vnt_private *priv, unsigned char byLocalID)
2383 BBbWriteEmbedded(priv, 0x0C, 0x17); /* CR12 */
2384 BBbWriteEmbedded(priv, 0x0D, 0xB9); /* CR13 */
2388 BBvExitDeepSleep(struct vnt_private *priv, unsigned char byLocalID)
2390 BBbWriteEmbedded(priv, 0x0C, 0x00); /* CR12 */
2391 BBbWriteEmbedded(priv, 0x0D, 0x01); /* CR13 */