1 #include <linux/module.h>
2 #include <linux/kernel.h>
3 #include <linux/errno.h>
4 #include <linux/string.h>
6 #include <linux/slab.h>
7 #include <linux/delay.h>
9 #include <linux/ioport.h>
10 #include <linux/init.h>
11 #include <linux/pci.h>
12 #include <linux/vmalloc.h>
13 #include <linux/pagemap.h>
14 #include <linux/console.h>
18 #include <linux/platform_device.h>
19 #include <linux/screen_info.h>
20 #include <linux/sizes.h>
24 #include "sm750_accel.h"
26 int hw_sm750_map(struct sm750_dev *sm750_dev, struct pci_dev *pdev)
32 sm750_dev->vidreg_start = pci_resource_start(pdev, 1);
33 sm750_dev->vidreg_size = SZ_2M;
35 pr_info("mmio phyAddr = %lx\n", sm750_dev->vidreg_start);
37 /* reserve the vidreg space of smi adaptor
38 * if you do this, you need to add release region code
39 * in lynxfb_remove, or memory will not be mapped again
42 ret = pci_request_region(pdev, 1, "sm750fb");
44 pr_err("Can not request PCI regions.\n");
48 /* now map mmio and vidmem */
49 sm750_dev->pvReg = ioremap_nocache(sm750_dev->vidreg_start,
50 sm750_dev->vidreg_size);
51 if (!sm750_dev->pvReg) {
52 pr_err("mmio failed\n");
56 pr_info("mmio virtual addr = %p\n", sm750_dev->pvReg);
59 sm750_dev->accel.dprBase = sm750_dev->pvReg + DE_BASE_ADDR_TYPE1;
60 sm750_dev->accel.dpPortBase = sm750_dev->pvReg + DE_PORT_ADDR_TYPE1;
62 ddk750_set_mmio(sm750_dev->pvReg, sm750_dev->devid, sm750_dev->revid);
64 sm750_dev->vidmem_start = pci_resource_start(pdev, 0);
65 /* don't use pdev_resource[x].end - resource[x].start to
66 * calculate the resource size, it's only the maximum available
67 * size but not the actual size, using
68 * @ddk750_getVMSize function can be safe.
70 sm750_dev->vidmem_size = ddk750_getVMSize();
71 pr_info("video memory phyAddr = %lx, size = %u bytes\n",
72 sm750_dev->vidmem_start, sm750_dev->vidmem_size);
74 /* reserve the vidmem space of smi adaptor */
75 sm750_dev->pvMem = ioremap_wc(sm750_dev->vidmem_start,
76 sm750_dev->vidmem_size);
77 if (!sm750_dev->pvMem) {
78 pr_err("Map video memory failed\n");
82 pr_info("video memory vaddr = %p\n", sm750_dev->pvMem);
88 int hw_sm750_inithw(struct sm750_dev *sm750_dev, struct pci_dev *pdev)
90 struct init_status *parm;
92 parm = &sm750_dev->initParm;
93 if (parm->chip_clk == 0)
94 parm->chip_clk = (sm750_get_chip_type() == SM750LE) ?
95 DEFAULT_SM750LE_CHIP_CLOCK :
96 DEFAULT_SM750_CHIP_CLOCK;
98 if (parm->mem_clk == 0)
99 parm->mem_clk = parm->chip_clk;
100 if (parm->master_clk == 0)
101 parm->master_clk = parm->chip_clk / 3;
103 ddk750_initHw((initchip_param_t *)&sm750_dev->initParm);
104 /* for sm718, open pci burst */
105 if (sm750_dev->devid == 0x718) {
107 PEEK32(SYSTEM_CTRL) | SYSTEM_CTRL_PCI_BURST);
110 if (sm750_get_chip_type() != SM750LE) {
112 /* does user need CRT? */
113 if (sm750_dev->nocrt) {
115 PEEK32(MISC_CTRL) | MISC_CTRL_DAC_POWER_OFF);
117 val = PEEK32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK;
118 val |= SYSTEM_CTRL_DPMS_VPHN;
119 POKE32(SYSTEM_CTRL, val);
122 PEEK32(MISC_CTRL) & ~MISC_CTRL_DAC_POWER_OFF);
124 val = PEEK32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK;
125 val |= SYSTEM_CTRL_DPMS_VPHP;
126 POKE32(SYSTEM_CTRL, val);
129 val = PEEK32(PANEL_DISPLAY_CTRL) &
130 ~(PANEL_DISPLAY_CTRL_DUAL_DISPLAY |
131 PANEL_DISPLAY_CTRL_DOUBLE_PIXEL);
132 switch (sm750_dev->pnltype) {
135 case sm750_doubleTFT:
136 val |= PANEL_DISPLAY_CTRL_DOUBLE_PIXEL;
139 val |= PANEL_DISPLAY_CTRL_DUAL_DISPLAY;
142 POKE32(PANEL_DISPLAY_CTRL, val);
144 /* for 750LE, no DVI chip initialization
145 * makes Monitor no signal
147 * Set up GPIO for software I2C to program DVI chip in the
148 * Xilinx SP605 board, in order to have video signal.
150 sm750_sw_i2c_init(0, 1);
152 /* Customer may NOT use CH7301 DVI chip, which has to be
153 * initialized differently.
155 if (sm750_sw_i2c_read_reg(0xec, 0x4a) == 0x95) {
156 /* The following register values for CH7301 are from
157 * Chrontel app note and our experiment.
159 pr_info("yes,CH7301 DVI chip found\n");
160 sm750_sw_i2c_write_reg(0xec, 0x1d, 0x16);
161 sm750_sw_i2c_write_reg(0xec, 0x21, 0x9);
162 sm750_sw_i2c_write_reg(0xec, 0x49, 0xC0);
163 pr_info("okay,CH7301 DVI chip setup done\n");
168 if (!sm750_dev->accel_off)
169 hw_sm750_initAccel(sm750_dev);
174 int hw_sm750_output_setMode(struct lynxfb_output *output,
175 struct fb_var_screeninfo *var,
176 struct fb_fix_screeninfo *fix)
179 disp_output_t dispSet;
184 channel = *output->channel;
186 if (sm750_get_chip_type() != SM750LE) {
187 if (channel == sm750_primary) {
188 pr_info("primary channel\n");
189 if (output->paths & sm750_panel)
190 dispSet |= do_LCD1_PRI;
191 if (output->paths & sm750_crt)
192 dispSet |= do_CRT_PRI;
195 pr_info("secondary channel\n");
196 if (output->paths & sm750_panel)
197 dispSet |= do_LCD1_SEC;
198 if (output->paths & sm750_crt)
199 dispSet |= do_CRT_SEC;
201 ddk750_setLogicalDispOut(dispSet);
203 /* just open DISPLAY_CONTROL_750LE register bit 3:0 */
206 reg = PEEK32(DISPLAY_CONTROL_750LE);
208 POKE32(DISPLAY_CONTROL_750LE, reg);
211 pr_info("ddk setlogicdispout done\n");
215 int hw_sm750_crtc_checkMode(struct lynxfb_crtc *crtc,
216 struct fb_var_screeninfo *var)
218 struct sm750_dev *sm750_dev;
219 struct lynxfb_par *par = container_of(crtc, struct lynxfb_par, crtc);
221 sm750_dev = par->dev;
223 switch (var->bits_per_pixel) {
228 if (sm750_dev->revid == SM750LE_REVISION_ID) {
229 pr_debug("750le do not support 32bpp\n");
240 /* set the controller's mode for @crtc charged with @var and @fix parameters */
241 int hw_sm750_crtc_setMode(struct lynxfb_crtc *crtc,
242 struct fb_var_screeninfo *var,
243 struct fb_fix_screeninfo *fix)
247 mode_parameter_t modparm;
249 struct sm750_dev *sm750_dev;
250 struct lynxfb_par *par;
253 par = container_of(crtc, struct lynxfb_par, crtc);
254 sm750_dev = par->dev;
256 if (!sm750_dev->accel_off) {
257 /* set 2d engine pixel format according to mode bpp */
258 switch (var->bits_per_pixel) {
270 hw_set2dformat(&sm750_dev->accel, fmt);
274 modparm.pixel_clock = ps_to_hz(var->pixclock);
275 modparm.vertical_sync_polarity = (var->sync & FB_SYNC_HOR_HIGH_ACT)
277 modparm.horizontal_sync_polarity = (var->sync & FB_SYNC_VERT_HIGH_ACT)
279 modparm.clock_phase_polarity = (var->sync & FB_SYNC_COMP_HIGH_ACT)
281 modparm.horizontal_display_end = var->xres;
282 modparm.horizontal_sync_width = var->hsync_len;
283 modparm.horizontal_sync_start = var->xres + var->right_margin;
284 modparm.horizontal_total = var->xres + var->left_margin +
285 var->right_margin + var->hsync_len;
286 modparm.vertical_display_end = var->yres;
287 modparm.vertical_sync_height = var->vsync_len;
288 modparm.vertical_sync_start = var->yres + var->lower_margin;
289 modparm.vertical_total = var->yres + var->upper_margin +
290 var->lower_margin + var->vsync_len;
293 if (crtc->channel != sm750_secondary)
296 clock = SECONDARY_PLL;
298 pr_debug("Request pixel clock = %lu\n", modparm.pixel_clock);
299 ret = ddk750_setModeTiming(&modparm, clock);
301 pr_err("Set mode timing failed\n");
305 if (crtc->channel != sm750_secondary) {
306 /* set pitch, offset, width, start address, etc... */
307 POKE32(PANEL_FB_ADDRESS,
308 crtc->oScreen & PANEL_FB_ADDRESS_ADDRESS_MASK);
310 reg = var->xres * (var->bits_per_pixel >> 3);
311 /* crtc->channel is not equal to par->index on numeric,
314 reg = ALIGN(reg, crtc->line_pad);
315 reg = (reg << PANEL_FB_WIDTH_WIDTH_SHIFT) &
316 PANEL_FB_WIDTH_WIDTH_MASK;
317 reg |= (fix->line_length & PANEL_FB_WIDTH_OFFSET_MASK);
318 POKE32(PANEL_FB_WIDTH, reg);
320 reg = ((var->xres - 1) << PANEL_WINDOW_WIDTH_WIDTH_SHIFT) &
321 PANEL_WINDOW_WIDTH_WIDTH_MASK;
322 reg |= (var->xoffset & PANEL_WINDOW_WIDTH_X_MASK);
323 POKE32(PANEL_WINDOW_WIDTH, reg);
325 reg = (var->yres_virtual - 1) <<
326 PANEL_WINDOW_HEIGHT_HEIGHT_SHIFT;
327 reg &= PANEL_WINDOW_HEIGHT_HEIGHT_MASK;
328 reg |= (var->yoffset & PANEL_WINDOW_HEIGHT_Y_MASK);
329 POKE32(PANEL_WINDOW_HEIGHT, reg);
331 POKE32(PANEL_PLANE_TL, 0);
333 reg = ((var->yres - 1) << PANEL_PLANE_BR_BOTTOM_SHIFT) &
334 PANEL_PLANE_BR_BOTTOM_MASK;
335 reg |= ((var->xres - 1) & PANEL_PLANE_BR_RIGHT_MASK);
336 POKE32(PANEL_PLANE_BR, reg);
338 /* set pixel format */
339 reg = PEEK32(PANEL_DISPLAY_CTRL);
340 POKE32(PANEL_DISPLAY_CTRL, reg | (var->bits_per_pixel >> 4));
342 /* not implemented now */
343 POKE32(CRT_FB_ADDRESS, crtc->oScreen);
344 reg = var->xres * (var->bits_per_pixel >> 3);
345 /* crtc->channel is not equal to par->index on numeric,
348 reg = ALIGN(reg, crtc->line_pad) << CRT_FB_WIDTH_WIDTH_SHIFT;
349 reg &= CRT_FB_WIDTH_WIDTH_MASK;
350 reg |= (fix->line_length & CRT_FB_WIDTH_OFFSET_MASK);
351 POKE32(CRT_FB_WIDTH, reg);
353 /* SET PIXEL FORMAT */
354 reg = PEEK32(CRT_DISPLAY_CTRL);
355 reg |= ((var->bits_per_pixel >> 4) &
356 CRT_DISPLAY_CTRL_FORMAT_MASK);
357 POKE32(CRT_DISPLAY_CTRL, reg);
364 int hw_sm750_setColReg(struct lynxfb_crtc *crtc, ushort index,
365 ushort red, ushort green, ushort blue)
367 static unsigned int add[] = {PANEL_PALETTE_RAM, CRT_PALETTE_RAM};
369 POKE32(add[crtc->channel] + index * 4,
370 (red << 16) | (green << 8) | blue);
374 int hw_sm750le_setBLANK(struct lynxfb_output *output, int blank)
379 case FB_BLANK_UNBLANK:
380 dpms = CRT_DISPLAY_CTRL_DPMS_0;
383 case FB_BLANK_NORMAL:
384 dpms = CRT_DISPLAY_CTRL_DPMS_0;
385 crtdb = CRT_DISPLAY_CTRL_BLANK;
387 case FB_BLANK_VSYNC_SUSPEND:
388 dpms = CRT_DISPLAY_CTRL_DPMS_2;
389 crtdb = CRT_DISPLAY_CTRL_BLANK;
391 case FB_BLANK_HSYNC_SUSPEND:
392 dpms = CRT_DISPLAY_CTRL_DPMS_1;
393 crtdb = CRT_DISPLAY_CTRL_BLANK;
395 case FB_BLANK_POWERDOWN:
396 dpms = CRT_DISPLAY_CTRL_DPMS_3;
397 crtdb = CRT_DISPLAY_CTRL_BLANK;
403 if (output->paths & sm750_crt) {
406 val = PEEK32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_DPMS_MASK;
407 POKE32(CRT_DISPLAY_CTRL, val | dpms);
409 val = PEEK32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_BLANK;
410 POKE32(CRT_DISPLAY_CTRL, val | crtdb);
415 int hw_sm750_setBLANK(struct lynxfb_output *output, int blank)
417 unsigned int dpms, pps, crtdb;
424 case FB_BLANK_UNBLANK:
425 pr_debug("flag = FB_BLANK_UNBLANK\n");
426 dpms = SYSTEM_CTRL_DPMS_VPHP;
427 pps = PANEL_DISPLAY_CTRL_DATA;
429 case FB_BLANK_NORMAL:
430 pr_debug("flag = FB_BLANK_NORMAL\n");
431 dpms = SYSTEM_CTRL_DPMS_VPHP;
432 crtdb = CRT_DISPLAY_CTRL_BLANK;
434 case FB_BLANK_VSYNC_SUSPEND:
435 dpms = SYSTEM_CTRL_DPMS_VNHP;
436 crtdb = CRT_DISPLAY_CTRL_BLANK;
438 case FB_BLANK_HSYNC_SUSPEND:
439 dpms = SYSTEM_CTRL_DPMS_VPHN;
440 crtdb = CRT_DISPLAY_CTRL_BLANK;
442 case FB_BLANK_POWERDOWN:
443 dpms = SYSTEM_CTRL_DPMS_VNHN;
444 crtdb = CRT_DISPLAY_CTRL_BLANK;
448 if (output->paths & sm750_crt) {
449 unsigned int val = PEEK32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK;
451 POKE32(SYSTEM_CTRL, val | dpms);
453 val = PEEK32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_BLANK;
454 POKE32(CRT_DISPLAY_CTRL, val | crtdb);
457 if (output->paths & sm750_panel) {
458 unsigned int val = PEEK32(PANEL_DISPLAY_CTRL);
460 val &= ~PANEL_DISPLAY_CTRL_DATA;
462 POKE32(PANEL_DISPLAY_CTRL, val);
468 void hw_sm750_initAccel(struct sm750_dev *sm750_dev)
474 if (sm750_get_chip_type() == SM750LE) {
475 reg = PEEK32(DE_STATE1);
476 reg |= DE_STATE1_DE_ABORT;
477 POKE32(DE_STATE1, reg);
479 reg = PEEK32(DE_STATE1);
480 reg &= ~DE_STATE1_DE_ABORT;
481 POKE32(DE_STATE1, reg);
485 reg = PEEK32(SYSTEM_CTRL);
486 reg |= SYSTEM_CTRL_DE_ABORT;
487 POKE32(SYSTEM_CTRL, reg);
489 reg = PEEK32(SYSTEM_CTRL);
490 reg &= ~SYSTEM_CTRL_DE_ABORT;
491 POKE32(SYSTEM_CTRL, reg);
495 sm750_dev->accel.de_init(&sm750_dev->accel);
498 int hw_sm750le_deWait(void)
501 unsigned int mask = DE_STATE2_DE_STATUS_BUSY | DE_STATE2_DE_FIFO_EMPTY |
502 DE_STATE2_DE_MEM_FIFO_EMPTY;
505 unsigned int val = PEEK32(DE_STATE2);
508 (DE_STATE2_DE_FIFO_EMPTY | DE_STATE2_DE_MEM_FIFO_EMPTY))
515 int hw_sm750_deWait(void)
518 unsigned int mask = SYSTEM_CTRL_DE_STATUS_BUSY |
519 SYSTEM_CTRL_DE_FIFO_EMPTY |
520 SYSTEM_CTRL_DE_MEM_FIFO_EMPTY;
523 unsigned int val = PEEK32(SYSTEM_CTRL);
526 (SYSTEM_CTRL_DE_FIFO_EMPTY | SYSTEM_CTRL_DE_MEM_FIFO_EMPTY))
533 int hw_sm750_pan_display(struct lynxfb_crtc *crtc,
534 const struct fb_var_screeninfo *var,
535 const struct fb_info *info)
539 if ((var->xoffset + var->xres > var->xres_virtual) ||
540 (var->yoffset + var->yres > var->yres_virtual)) {
544 total = var->yoffset * info->fix.line_length +
545 ((var->xoffset * var->bits_per_pixel) >> 3);
546 total += crtc->oScreen;
547 if (crtc->channel == sm750_primary) {
548 POKE32(PANEL_FB_ADDRESS,
549 PEEK32(PANEL_FB_ADDRESS) |
550 (total & PANEL_FB_ADDRESS_ADDRESS_MASK));
552 POKE32(CRT_FB_ADDRESS,
553 PEEK32(CRT_FB_ADDRESS) |
554 (total & CRT_FB_ADDRESS_ADDRESS_MASK));