drivers/staging/rtl8821ae/debug.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL_DEBUG_H__
  31 #define __RTL_DEBUG_H__
  32
  33 /*--------------------------------------------------------------
  34                         Debug level
  35 --------------------------------------------------------------*/
  36 /*
  37  *Fatal bug.
  38  *For example, Tx/Rx/IO locked up,
  39  *memory access violation,
  40  *resource allocation failed,
  41  *unexpected HW behavior, HW BUG
  42  *and so on.
  43  */
  44 #define DBG_EMERG                       0
  45
  46 /*
  47  *Abnormal, rare, or unexpected cases.
  48  *For example, Packet/IO Ctl canceled,
  49  *device suprisely unremoved and so on.
  50  */
  51 #define DBG_WARNING                     2
  52
  53 /*
  54  *Normal case driver developer should
  55  *open, we can see link status like
  56  *assoc/AddBA/DHCP/adapter start and
  57  *so on basic and useful informations.
  58  */
  59 #define DBG_DMESG                       3
  60
  61 /*
  62  *Normal case with useful information
  63  *about current SW or HW state.
  64  *For example, Tx/Rx descriptor to fill,
  65  *Tx/Rx descriptor completed status,
  66  *SW protocol state change, dynamic
  67  *mechanism state change and so on.
  68  */
  69 #define DBG_LOUD                        4
  70
  71 /*
  72  *Normal case with detail execution
  73  *flow or information.
  74  */
  75 #define DBG_TRACE                       5
  76
  77 /*--------------------------------------------------------------
  78                 Define the rt_trace components
  79 --------------------------------------------------------------*/
  80 #define COMP_ERR                        BIT(0)
  81 #define COMP_FW                         BIT(1)
  82 #define COMP_INIT                       BIT(2)  /*For init/deinit */
  83 #define COMP_RECV                       BIT(3)  /*For Rx. */
  84 #define COMP_SEND                       BIT(4)  /*For Tx. */
  85 #define COMP_MLME                       BIT(5)  /*For MLME. */
  86 #define COMP_SCAN                       BIT(6)  /*For Scan. */
  87 #define COMP_INTR                       BIT(7)  /*For interrupt Related. */
  88 #define COMP_LED                        BIT(8)  /*For LED. */
  89 #define COMP_SEC                        BIT(9)  /*For sec. */
  90 #define COMP_BEACON                     BIT(10) /*For beacon. */
  91 #define COMP_RATE                       BIT(11) /*For rate. */
  92 #define COMP_RXDESC                     BIT(12) /*For rx desc. */
  93 #define COMP_DIG                        BIT(13) /*For DIG */
  94 #define COMP_TXAGC                      BIT(14) /*For Tx power */
  95 #define COMP_HIPWR                      BIT(15) /*For High Power Mechanism */
  96 #define COMP_POWER                      BIT(16) /*For lps/ips/aspm. */
  97 #define COMP_POWER_TRACKING     BIT(17) /*For TX POWER TRACKING */
  98 #define COMP_BB_POWERSAVING     BIT(18)
  99 #define COMP_SWAS                       BIT(19) /*For SW Antenna Switch */
 100 #define COMP_RF                         BIT(20) /*For RF. */
 101 #define COMP_TURBO                      BIT(21) /*For EDCA TURBO. */
 102 #define COMP_RATR                       BIT(22)
 103 #define COMP_CMD                        BIT(23)
 104 #define COMP_EFUSE                      BIT(24)
 105 #define COMP_QOS                        BIT(25)
 106 #define COMP_MAC80211           BIT(26)
 107 #define COMP_REGD                       BIT(27)
 108 #define COMP_CHAN                       BIT(28)
 109 #define COMP_EASY_CONCURRENT            BIT(29)
 110 #define COMP_BT_COEXIST                 BIT(30)
 111 #define COMP_IQK                        BIT(31)
 112
 113 /*--------------------------------------------------------------
 114                 Define the rt_print components
 115 --------------------------------------------------------------*/
 116 /* Define EEPROM and EFUSE  check module bit*/
 117 #define EEPROM_W                        BIT(0)
 118 #define EFUSE_PG                        BIT(1)
 119 #define EFUSE_READ_ALL          BIT(2)
 120
 121 /* Define init check for module bit*/
 122 #define INIT_EEPROM                     BIT(0)
 123 #define INIT_TxPower            BIT(1)
 124 #define INIT_IQK                        BIT(2)
 125 #define INIT_RF                         BIT(3)
 126
 127 /* Define PHY-BB/RF/MAC check module bit */
 128 #define PHY_BBR                         BIT(0)
 129 #define PHY_BBW                         BIT(1)
 130 #define PHY_RFR                         BIT(2)
 131 #define PHY_RFW                         BIT(3)
 132 #define PHY_MACR                        BIT(4)
 133 #define PHY_MACW                        BIT(5)
 134 #define PHY_ALLR                        BIT(6)
 135 #define PHY_ALLW                        BIT(7)
 136 #define PHY_TXPWR                       BIT(8)
 137 #define PHY_PWRDIFF                     BIT(9)
 138
 139 /* Define Dynamic Mechanism check module bit --> FDM */
 140 #define WA_IOT                          BIT(0)
 141 #define DM_PWDB                         BIT(1)
 142 #define DM_MONITOR                      BIT(2)
 143 #define DM_DIG                          BIT(3)
 144 #define DM_EDCA_TURBO           BIT(4)
 145
 146 enum dbgp_flag_e {
 147         FQOS = 0,
 148         FTX = 1,
 149         FRX = 2,
 150         FSEC = 3,
 151         FMGNT = 4,
 152         FMLME = 5,
 153         FRESOURCE = 6,
 154         FBEACON = 7,
 155         FISR = 8,
 156         FPHY = 9,
 157         FMP = 10,
 158         FEEPROM = 11,
 159         FPWR = 12,
 160         FDM = 13,
 161         FDBGCtrl = 14,
 162         FC2H = 15,
 163         FBT = 16,
 164         FINIT = 17,
 165         FIOCTL = 18,
 166         DBGP_TYPE_MAX
 167 };
 168
 169 #define RT_ASSERT(_exp,fmt)                             \
 170         do { \
 171                 if(!(_exp))     {                       \
 172                         printk(KERN_DEBUG "%s:%s(): ", KBUILD_MODNAME, \
 173                         __func__);      \
 174                         printk fmt;                     \
 175                 } \
 176         } while(0);
 177
 178 #define RT_DISP(dbgtype, dbgflag, printstr)
 179
 180 #define RT_TRACE(comp, level, fmt)\
 181         do { \
 182                 if(unlikely(((comp) & rtlpriv->dbg.global_debugcomponents) && \
 183                         ((level) <= rtlpriv->dbg.global_debuglevel))) {\
 184                         printk(KERN_DEBUG "%s-%d:%s():<%lx-%x> ", \
 185                         KBUILD_MODNAME, \
 186                         rtlpriv->rtlhal.interfaceindex, __func__, \
 187                         in_interrupt(), in_atomic());   \
 188                         printk fmt;                     \
 189                 }\
 190         } while(0);
 191
 192 #define RTPRINT(rtlpriv, dbgtype, dbgflag, printstr)    \
 193         do {                                            \
 194                 if (unlikely(rtlpriv->dbg.dbgp_type[dbgtype] & dbgflag)) { \
 195                         printk(KERN_DEBUG "%s: ", KBUILD_MODNAME);      \
 196                         printk printstr;                \
 197                 }                                       \
 198         } while(0);
 199
 200 #define RT_PRINT_DATA(rtlpriv, _comp, _level, _titlestring, _hexdata, \
 201                 _hexdatalen) \
 202         do {\
 203                 if(unlikely(((_comp) & rtlpriv->dbg.global_debugcomponents ) &&\
 204                         (_level <= rtlpriv->dbg.global_debuglevel )))   { \
 205                         int __i;                                        \
 206                         u8*     ptr = (u8*)_hexdata;                    \
 207                         printk(KERN_DEBUG "%s: ", KBUILD_MODNAME);      \
 208                         printk(KERN_DEBUG "In process \"%s\" (pid %i):", \
 209                                         current->comm,  \
 210                                         current->pid); \
 211                         printk(_titlestring);           \
 212                         for( __i=0; __i<(int)_hexdatalen; __i++ ) {     \
 213                                 printk("%02X%s", ptr[__i], (((__i + 1) % 4) \
 214                                                         == 0)?"  ":" ");\
 215                                 if (((__i + 1) % 16) == 0)      \
 216                                         printk("\n");   \
 217                         }                               \
 218                         printk(KERN_DEBUG "\n");                        \
 219                 } \
 220         } while(0);
 221
 222 void rtl_dbgp_flag_init(struct ieee80211_hw *hw);
 223 void rtl_proc_add_one(struct ieee80211_hw *hw);
 224 void rtl_proc_remove_one(struct ieee80211_hw *hw);
 225 void rtl_proc_add_topdir(void);
 226 void rtl_proc_remove_topdir(void);
 227 #endif