1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * TI OMAP4 ISS V4L2 Driver - CSI2 module
5 * Copyright (C) 2012 Texas Instruments, Inc.
7 * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com>
10 #ifndef OMAP4_ISS_CSI2_H
11 #define OMAP4_ISS_CSI2_H
13 #include <linux/types.h>
14 #include <linux/videodev2.h>
16 #include "iss_video.h"
20 /* This is not an exhaustive list */
21 enum iss_csi2_pix_formats {
22 CSI2_PIX_FMT_OTHERS = 0,
23 CSI2_PIX_FMT_YUV422_8BIT = 0x1e,
24 CSI2_PIX_FMT_YUV422_8BIT_VP = 0x9e,
25 CSI2_PIX_FMT_YUV422_8BIT_VP16 = 0xde,
26 CSI2_PIX_FMT_RAW10_EXP16 = 0xab,
27 CSI2_PIX_FMT_RAW10_EXP16_VP = 0x12f,
28 CSI2_PIX_FMT_RAW8 = 0x2a,
29 CSI2_PIX_FMT_RAW8_DPCM10_EXP16 = 0x2aa,
30 CSI2_PIX_FMT_RAW8_DPCM10_VP = 0x32a,
31 CSI2_PIX_FMT_RAW8_VP = 0x12a,
32 CSI2_USERDEF_8BIT_DATA1_DPCM10_VP = 0x340,
33 CSI2_USERDEF_8BIT_DATA1_DPCM10 = 0x2c0,
34 CSI2_USERDEF_8BIT_DATA1 = 0x40,
37 enum iss_csi2_irqevents {
39 SHORT_PACKET_IRQ = 0x2000,
40 ECC_CORRECTION_IRQ = 0x1000,
41 ECC_NO_CORRECTION_IRQ = 0x800,
42 COMPLEXIO2_ERR_IRQ = 0x400,
43 COMPLEXIO1_ERR_IRQ = 0x200,
55 enum iss_csi2_ctx_irqevents {
56 CTX_ECC_CORRECTION = 0x100,
57 CTX_LINE_NUMBER = 0x80,
58 CTX_FRAME_NUMBER = 0x40,
66 enum iss_csi2_frame_mode {
67 ISS_CSI2_FRAME_IMMEDIATE,
68 ISS_CSI2_FRAME_AFTERFEC,
71 #define ISS_CSI2_MAX_CTX_NUM 7
73 struct iss_csi2_ctx_cfg {
74 u8 ctxnum; /* context number 0 - 7 */
77 /* Fields in CSI2_CTx_CTRL2 - locked by CSI2_CTx_CTRL1.CTX_EN */
79 u16 format_id; /* as in CSI2_CTx_CTRL2[9:0] */
80 u8 dpcm_predictor; /* 1: simple, 0: advanced */
83 /* Fields in CSI2_CTx_CTRL1/3 - Shadowed */
94 struct iss_csi2_timing_cfg {
95 u8 ionum; /* IO1 or IO2 as in CSI2_TIMING */
96 unsigned force_rx_mode:1;
97 unsigned stop_state_16x:1;
98 unsigned stop_state_4x:1;
99 u16 stop_state_counter;
102 struct iss_csi2_ctrl_cfg {
106 enum iss_csi2_frame_mode frame_mode;
111 #define CSI2_PAD_SINK 0
112 #define CSI2_PAD_SOURCE 1
113 #define CSI2_PADS_NUM 2
115 #define CSI2_OUTPUT_IPIPEIF BIT(0)
116 #define CSI2_OUTPUT_MEMORY BIT(1)
118 struct iss_csi2_device {
119 struct v4l2_subdev subdev;
120 struct media_pad pads[CSI2_PADS_NUM];
121 struct v4l2_mbus_framefmt formats[CSI2_PADS_NUM];
123 struct iss_video video_out;
124 struct iss_device *iss;
126 u8 available; /* Is the IP present on the silicon? */
128 /* memory resources, as defined in enum iss_mem_resources */
131 /* ISP subclock, as defined in enum iss_isp_subclk_resource */
134 u32 output; /* output to IPIPEIF, memory or both? */
135 bool dpcm_decompress;
136 unsigned int frame_skip;
138 struct iss_csiphy *phy;
139 struct iss_csi2_ctx_cfg contexts[ISS_CSI2_MAX_CTX_NUM + 1];
140 struct iss_csi2_timing_cfg timing[2];
141 struct iss_csi2_ctrl_cfg ctrl;
142 enum iss_pipeline_stream_state state;
143 wait_queue_head_t wait;
147 void omap4iss_csi2_isr(struct iss_csi2_device *csi2);
148 int omap4iss_csi2_reset(struct iss_csi2_device *csi2);
149 int omap4iss_csi2_init(struct iss_device *iss);
150 int omap4iss_csi2_create_links(struct iss_device *iss);
151 void omap4iss_csi2_cleanup(struct iss_device *iss);
152 void omap4iss_csi2_unregister_entities(struct iss_csi2_device *csi2);
153 int omap4iss_csi2_register_entities(struct iss_csi2_device *csi2,
154 struct v4l2_device *vdev);
155 #endif /* OMAP4_ISS_CSI2_H */