drivers/staging/media/hantro/hantro_h1_jpeg_enc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Hantro VPU codec driver
   4  *
   5  * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
   6  */
   7
   8 #include <asm/unaligned.h>
   9 #include <media/v4l2-mem2mem.h>
  10 #include "hantro_jpeg.h"
  11 #include "hantro.h"
  12 #include "hantro_v4l2.h"
  13 #include "hantro_hw.h"
  14 #include "hantro_h1_regs.h"
  15
  16 #define H1_JPEG_QUANT_TABLE_COUNT 16
  17
  18 static void hantro_h1_set_src_img_ctrl(struct hantro_dev *vpu,
  19                                        struct hantro_ctx *ctx)
  20 {
  21         struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
  22         u32 reg;
  23
  24         reg = H1_REG_IN_IMG_CTRL_ROW_LEN(pix_fmt->width)
  25                 | H1_REG_IN_IMG_CTRL_OVRFLR_D4(0)
  26                 | H1_REG_IN_IMG_CTRL_OVRFLB_D4(0)
  27                 | H1_REG_IN_IMG_CTRL_FMT(ctx->vpu_src_fmt->enc_fmt);
  28         vepu_write_relaxed(vpu, reg, H1_REG_IN_IMG_CTRL);
  29 }
  30
  31 static void hantro_h1_jpeg_enc_set_buffers(struct hantro_dev *vpu,
  32                                            struct hantro_ctx *ctx,
  33                                            struct vb2_buffer *src_buf)
  34 {
  35         struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
  36         dma_addr_t src[3];
  37
  38         WARN_ON(pix_fmt->num_planes > 3);
  39
  40         vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.dma,
  41                            H1_REG_ADDR_OUTPUT_STREAM);
  42         vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.size,
  43                            H1_REG_STR_BUF_LIMIT);
  44
  45         if (pix_fmt->num_planes == 1) {
  46                 src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  47                 /* single plane formats we supported are all interlaced */
  48                 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0);
  49         } else if (pix_fmt->num_planes == 2) {
  50                 src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  51                 src[1] = vb2_dma_contig_plane_dma_addr(src_buf, 1);
  52                 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0);
  53                 vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1);
  54         } else {
  55                 src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  56                 src[1] = vb2_dma_contig_plane_dma_addr(src_buf, 1);
  57                 src[2] = vb2_dma_contig_plane_dma_addr(src_buf, 2);
  58                 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0);
  59                 vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1);
  60                 vepu_write_relaxed(vpu, src[2], H1_REG_ADDR_IN_PLANE_2);
  61         }
  62 }
  63
  64 static void
  65 hantro_h1_jpeg_enc_set_qtable(struct hantro_dev *vpu,
  66                               unsigned char *luma_qtable,
  67                               unsigned char *chroma_qtable)
  68 {
  69         u32 reg, i;
  70
  71         for (i = 0; i < H1_JPEG_QUANT_TABLE_COUNT; i++) {
  72                 reg = get_unaligned_be32(&luma_qtable[i]);
  73                 vepu_write_relaxed(vpu, reg, H1_REG_JPEG_LUMA_QUAT(i));
  74
  75                 reg = get_unaligned_be32(&chroma_qtable[i]);
  76                 vepu_write_relaxed(vpu, reg, H1_REG_JPEG_CHROMA_QUAT(i));
  77         }
  78 }
  79
  80 void hantro_h1_jpeg_enc_run(struct hantro_ctx *ctx)
  81 {
  82         struct hantro_dev *vpu = ctx->dev;
  83         struct vb2_v4l2_buffer *src_buf, *dst_buf;
  84         struct hantro_jpeg_ctx jpeg_ctx;
  85         u32 reg;
  86
  87         src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  88         dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  89
  90         memset(&jpeg_ctx, 0, sizeof(jpeg_ctx));
  91         jpeg_ctx.buffer = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
  92         jpeg_ctx.width = ctx->dst_fmt.width;
  93         jpeg_ctx.height = ctx->dst_fmt.height;
  94         jpeg_ctx.quality = ctx->jpeg_quality;
  95         hantro_jpeg_header_assemble(&jpeg_ctx);
  96
  97         /* Switch to JPEG encoder mode before writing registers */
  98         vepu_write_relaxed(vpu, H1_REG_ENC_CTRL_ENC_MODE_JPEG,
  99                            H1_REG_ENC_CTRL);
 100
 101         hantro_h1_set_src_img_ctrl(vpu, ctx);
 102         hantro_h1_jpeg_enc_set_buffers(vpu, ctx, &src_buf->vb2_buf);
 103         hantro_h1_jpeg_enc_set_qtable(vpu,
 104                                       hantro_jpeg_get_qtable(&jpeg_ctx, 0),
 105                                       hantro_jpeg_get_qtable(&jpeg_ctx, 1));
 106
 107         reg = H1_REG_AXI_CTRL_OUTPUT_SWAP16
 108                 | H1_REG_AXI_CTRL_INPUT_SWAP16
 109                 | H1_REG_AXI_CTRL_BURST_LEN(16)
 110                 | H1_REG_AXI_CTRL_OUTPUT_SWAP32
 111                 | H1_REG_AXI_CTRL_INPUT_SWAP32
 112                 | H1_REG_AXI_CTRL_OUTPUT_SWAP8
 113                 | H1_REG_AXI_CTRL_INPUT_SWAP8;
 114         /* Make sure that all registers are written at this point. */
 115         vepu_write(vpu, reg, H1_REG_AXI_CTRL);
 116
 117         reg = H1_REG_ENC_CTRL_WIDTH(JPEG_MB_WIDTH(ctx->src_fmt.width))
 118                 | H1_REG_ENC_CTRL_HEIGHT(JPEG_MB_HEIGHT(ctx->src_fmt.height))
 119                 | H1_REG_ENC_CTRL_ENC_MODE_JPEG
 120                 | H1_REG_ENC_PIC_INTRA
 121                 | H1_REG_ENC_CTRL_EN_BIT;
 122         /* Kick the watchdog and start encoding */
 123         schedule_delayed_work(&vpu->watchdog_work, msecs_to_jiffies(2000));
 124         vepu_write(vpu, reg, H1_REG_ENC_CTRL);
 125 }