drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Hantro VPU codec driver
   4  *
   5  * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
   6  */
   7
   8 #include <asm/unaligned.h>
   9 #include <linux/bitfield.h>
  10 #include <media/v4l2-mem2mem.h>
  11 #include "hantro.h"
  12 #include "hantro_hw.h"
  13
  14 #define G1_SWREG(nr)                    ((nr) * 4)
  15
  16 #define G1_REG_RLC_VLC_BASE             G1_SWREG(12)
  17 #define G1_REG_DEC_OUT_BASE             G1_SWREG(13)
  18 #define G1_REG_REFER0_BASE              G1_SWREG(14)
  19 #define G1_REG_REFER1_BASE              G1_SWREG(15)
  20 #define G1_REG_REFER2_BASE              G1_SWREG(16)
  21 #define G1_REG_REFER3_BASE              G1_SWREG(17)
  22 #define G1_REG_QTABLE_BASE              G1_SWREG(40)
  23 #define G1_REG_DEC_E(v)                 ((v) ? BIT(0) : 0)
  24
  25 #define G1_REG_DEC_AXI_RD_ID(v)         (((v) << 24) & GENMASK(31, 24))
  26 #define G1_REG_DEC_TIMEOUT_E(v)         ((v) ? BIT(23) : 0)
  27 #define G1_REG_DEC_STRSWAP32_E(v)       ((v) ? BIT(22) : 0)
  28 #define G1_REG_DEC_STRENDIAN_E(v)       ((v) ? BIT(21) : 0)
  29 #define G1_REG_DEC_INSWAP32_E(v)        ((v) ? BIT(20) : 0)
  30 #define G1_REG_DEC_OUTSWAP32_E(v)       ((v) ? BIT(19) : 0)
  31 #define G1_REG_DEC_DATA_DISC_E(v)       ((v) ? BIT(18) : 0)
  32 #define G1_REG_DEC_LATENCY(v)           (((v) << 11) & GENMASK(16, 11))
  33 #define G1_REG_DEC_CLK_GATE_E(v)        ((v) ? BIT(10) : 0)
  34 #define G1_REG_DEC_IN_ENDIAN(v)         ((v) ? BIT(9) : 0)
  35 #define G1_REG_DEC_OUT_ENDIAN(v)        ((v) ? BIT(8) : 0)
  36 #define G1_REG_DEC_ADV_PRE_DIS(v)       ((v) ? BIT(6) : 0)
  37 #define G1_REG_DEC_SCMD_DIS(v)          ((v) ? BIT(5) : 0)
  38 #define G1_REG_DEC_MAX_BURST(v)         (((v) << 0) & GENMASK(4, 0))
  39
  40 #define G1_REG_DEC_MODE(v)              (((v) << 28) & GENMASK(31, 28))
  41 #define G1_REG_RLC_MODE_E(v)            ((v) ? BIT(27) : 0)
  42 #define G1_REG_PIC_INTERLACE_E(v)       ((v) ? BIT(23) : 0)
  43 #define G1_REG_PIC_FIELDMODE_E(v)       ((v) ? BIT(22) : 0)
  44 #define G1_REG_PIC_B_E(v)               ((v) ? BIT(21) : 0)
  45 #define G1_REG_PIC_INTER_E(v)           ((v) ? BIT(20) : 0)
  46 #define G1_REG_PIC_TOPFIELD_E(v)        ((v) ? BIT(19) : 0)
  47 #define G1_REG_FWD_INTERLACE_E(v)       ((v) ? BIT(18) : 0)
  48 #define G1_REG_FILTERING_DIS(v)         ((v) ? BIT(14) : 0)
  49 #define G1_REG_WRITE_MVS_E(v)           ((v) ? BIT(12) : 0)
  50 #define G1_REG_DEC_AXI_WR_ID(v)         (((v) << 0) & GENMASK(7, 0))
  51
  52 #define G1_REG_PIC_MB_WIDTH(v)          (((v) << 23) & GENMASK(31, 23))
  53 #define G1_REG_PIC_MB_HEIGHT_P(v)       (((v) << 11) & GENMASK(18, 11))
  54 #define G1_REG_ALT_SCAN_E(v)            ((v) ? BIT(6) : 0)
  55 #define G1_REG_TOPFIELDFIRST_E(v)       ((v) ? BIT(5) : 0)
  56
  57 #define G1_REG_STRM_START_BIT(v)        (((v) << 26) & GENMASK(31, 26))
  58 #define G1_REG_QSCALE_TYPE(v)           ((v) ? BIT(24) : 0)
  59 #define G1_REG_CON_MV_E(v)              ((v) ? BIT(4) : 0)
  60 #define G1_REG_INTRA_DC_PREC(v)         (((v) << 2) & GENMASK(3, 2))
  61 #define G1_REG_INTRA_VLC_TAB(v)         ((v) ? BIT(1) : 0)
  62 #define G1_REG_FRAME_PRED_DCT(v)        ((v) ? BIT(0) : 0)
  63
  64 #define G1_REG_INIT_QP(v)               (((v) << 25) & GENMASK(30, 25))
  65 #define G1_REG_STREAM_LEN(v)            (((v) << 0) & GENMASK(23, 0))
  66
  67 #define G1_REG_ALT_SCAN_FLAG_E(v)       ((v) ? BIT(19) : 0)
  68 #define G1_REG_FCODE_FWD_HOR(v)         (((v) << 15) & GENMASK(18, 15))
  69 #define G1_REG_FCODE_FWD_VER(v)         (((v) << 11) & GENMASK(14, 11))
  70 #define G1_REG_FCODE_BWD_HOR(v)         (((v) << 7) & GENMASK(10, 7))
  71 #define G1_REG_FCODE_BWD_VER(v)         (((v) << 3) & GENMASK(6, 3))
  72 #define G1_REG_MV_ACCURACY_FWD(v)       ((v) ? BIT(2) : 0)
  73 #define G1_REG_MV_ACCURACY_BWD(v)       ((v) ? BIT(1) : 0)
  74
  75 #define G1_REG_STARTMB_X(v)             (((v) << 23) & GENMASK(31, 23))
  76 #define G1_REG_STARTMB_Y(v)             (((v) << 15) & GENMASK(22, 15))
  77
  78 #define G1_REG_APF_THRESHOLD(v)         (((v) << 0) & GENMASK(13, 0))
  79
  80 #define PICT_TOP_FIELD     1
  81 #define PICT_BOTTOM_FIELD  2
  82 #define PICT_FRAME         3
  83
  84 static void
  85 hantro_g1_mpeg2_dec_set_quantization(struct hantro_dev *vpu,
  86                                      struct hantro_ctx *ctx)
  87 {
  88         struct v4l2_ctrl_mpeg2_quantization *quantization;
  89
  90         quantization = hantro_get_ctrl(ctx,
  91                                        V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION);
  92         hantro_mpeg2_dec_copy_qtable(ctx->mpeg2_dec.qtable.cpu,
  93                                      quantization);
  94         vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma,
  95                            G1_REG_QTABLE_BASE);
  96 }
  97
  98 static void
  99 hantro_g1_mpeg2_dec_set_buffers(struct hantro_dev *vpu, struct hantro_ctx *ctx,
 100                                 struct vb2_buffer *src_buf,
 101                                 struct vb2_buffer *dst_buf,
 102                                 const struct v4l2_mpeg2_sequence *sequence,
 103                                 const struct v4l2_mpeg2_picture *picture,
 104                                 const struct v4l2_ctrl_mpeg2_slice_params *slice_params)
 105 {
 106         dma_addr_t forward_addr = 0, backward_addr = 0;
 107         dma_addr_t current_addr, addr;
 108         struct vb2_queue *vq;
 109
 110         vq = v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx);
 111
 112         switch (picture->picture_coding_type) {
 113         case V4L2_MPEG2_PICTURE_CODING_TYPE_B:
 114                 backward_addr = hantro_get_ref(vq,
 115                                                slice_params->backward_ref_ts);
 116                 /* fall-through */
 117         case V4L2_MPEG2_PICTURE_CODING_TYPE_P:
 118                 forward_addr = hantro_get_ref(vq,
 119                                               slice_params->forward_ref_ts);
 120         }
 121
 122         /* Source bitstream buffer */
 123         addr = vb2_dma_contig_plane_dma_addr(src_buf, 0);
 124         vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE);
 125
 126         /* Destination frame buffer */
 127         addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
 128         current_addr = addr;
 129
 130         if (picture->picture_structure == PICT_BOTTOM_FIELD)
 131                 addr += ALIGN(ctx->dst_fmt.width, 16);
 132         vdpu_write_relaxed(vpu, addr, G1_REG_DEC_OUT_BASE);
 133
 134         if (!forward_addr)
 135                 forward_addr = current_addr;
 136         if (!backward_addr)
 137                 backward_addr = current_addr;
 138
 139         /* Set forward ref frame (top/bottom field) */
 140         if (picture->picture_structure == PICT_FRAME ||
 141             picture->picture_coding_type == V4L2_MPEG2_PICTURE_CODING_TYPE_B ||
 142             (picture->picture_structure == PICT_TOP_FIELD &&
 143              picture->top_field_first) ||
 144             (picture->picture_structure == PICT_BOTTOM_FIELD &&
 145              !picture->top_field_first)) {
 146                 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE);
 147                 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE);
 148         } else if (picture->picture_structure == PICT_TOP_FIELD) {
 149                 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE);
 150                 vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER1_BASE);
 151         } else if (picture->picture_structure == PICT_BOTTOM_FIELD) {
 152                 vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER0_BASE);
 153                 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE);
 154         }
 155
 156         /* Set backward ref frame (top/bottom field) */
 157         vdpu_write_relaxed(vpu, backward_addr, G1_REG_REFER2_BASE);
 158         vdpu_write_relaxed(vpu, backward_addr, G1_REG_REFER3_BASE);
 159 }
 160
 161 void hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx)
 162 {
 163         struct hantro_dev *vpu = ctx->dev;
 164         struct vb2_v4l2_buffer *src_buf, *dst_buf;
 165         const struct v4l2_ctrl_mpeg2_slice_params *slice_params;
 166         const struct v4l2_mpeg2_sequence *sequence;
 167         const struct v4l2_mpeg2_picture *picture;
 168         u32 reg;
 169
 170         src_buf = hantro_get_src_buf(ctx);
 171         dst_buf = hantro_get_dst_buf(ctx);
 172
 173         /* Apply request controls if any */
 174         hantro_prepare_run(ctx);
 175
 176         slice_params = hantro_get_ctrl(ctx,
 177                                        V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS);
 178         sequence = &slice_params->sequence;
 179         picture = &slice_params->picture;
 180
 181         reg = G1_REG_DEC_AXI_RD_ID(0) |
 182               G1_REG_DEC_TIMEOUT_E(1) |
 183               G1_REG_DEC_STRSWAP32_E(1) |
 184               G1_REG_DEC_STRENDIAN_E(1) |
 185               G1_REG_DEC_INSWAP32_E(1) |
 186               G1_REG_DEC_OUTSWAP32_E(1) |
 187               G1_REG_DEC_DATA_DISC_E(0) |
 188               G1_REG_DEC_LATENCY(0) |
 189               G1_REG_DEC_CLK_GATE_E(1) |
 190               G1_REG_DEC_IN_ENDIAN(1) |
 191               G1_REG_DEC_OUT_ENDIAN(1) |
 192               G1_REG_DEC_ADV_PRE_DIS(0) |
 193               G1_REG_DEC_SCMD_DIS(0) |
 194               G1_REG_DEC_MAX_BURST(16);
 195         vdpu_write_relaxed(vpu, reg, G1_SWREG(2));
 196
 197         reg = G1_REG_DEC_MODE(5) |
 198               G1_REG_RLC_MODE_E(0) |
 199               G1_REG_PIC_INTERLACE_E(!sequence->progressive_sequence) |
 200               G1_REG_PIC_FIELDMODE_E(picture->picture_structure != PICT_FRAME) |
 201               G1_REG_PIC_B_E(picture->picture_coding_type == V4L2_MPEG2_PICTURE_CODING_TYPE_B) |
 202               G1_REG_PIC_INTER_E(picture->picture_coding_type != V4L2_MPEG2_PICTURE_CODING_TYPE_I) |
 203               G1_REG_PIC_TOPFIELD_E(picture->picture_structure == PICT_TOP_FIELD) |
 204               G1_REG_FWD_INTERLACE_E(0) |
 205               G1_REG_FILTERING_DIS(1) |
 206               G1_REG_WRITE_MVS_E(0) |
 207               G1_REG_DEC_AXI_WR_ID(0);
 208         vdpu_write_relaxed(vpu, reg, G1_SWREG(3));
 209
 210         reg = G1_REG_PIC_MB_WIDTH(MPEG2_MB_WIDTH(ctx->dst_fmt.width)) |
 211               G1_REG_PIC_MB_HEIGHT_P(MPEG2_MB_HEIGHT(ctx->dst_fmt.height)) |
 212               G1_REG_ALT_SCAN_E(picture->alternate_scan) |
 213               G1_REG_TOPFIELDFIRST_E(picture->top_field_first);
 214         vdpu_write_relaxed(vpu, reg, G1_SWREG(4));
 215
 216         reg = G1_REG_STRM_START_BIT(slice_params->data_bit_offset) |
 217               G1_REG_QSCALE_TYPE(picture->q_scale_type) |
 218               G1_REG_CON_MV_E(picture->concealment_motion_vectors) |
 219               G1_REG_INTRA_DC_PREC(picture->intra_dc_precision) |
 220               G1_REG_INTRA_VLC_TAB(picture->intra_vlc_format) |
 221               G1_REG_FRAME_PRED_DCT(picture->frame_pred_frame_dct);
 222         vdpu_write_relaxed(vpu, reg, G1_SWREG(5));
 223
 224         reg = G1_REG_INIT_QP(1) |
 225               G1_REG_STREAM_LEN(slice_params->bit_size >> 3);
 226         vdpu_write_relaxed(vpu, reg, G1_SWREG(6));
 227
 228         reg = G1_REG_ALT_SCAN_FLAG_E(picture->alternate_scan) |
 229               G1_REG_FCODE_FWD_HOR(picture->f_code[0][0]) |
 230               G1_REG_FCODE_FWD_VER(picture->f_code[0][1]) |
 231               G1_REG_FCODE_BWD_HOR(picture->f_code[1][0]) |
 232               G1_REG_FCODE_BWD_VER(picture->f_code[1][1]) |
 233               G1_REG_MV_ACCURACY_FWD(1) |
 234               G1_REG_MV_ACCURACY_BWD(1);
 235         vdpu_write_relaxed(vpu, reg, G1_SWREG(18));
 236
 237         reg = G1_REG_STARTMB_X(0) |
 238               G1_REG_STARTMB_Y(0);
 239         vdpu_write_relaxed(vpu, reg, G1_SWREG(48));
 240
 241         reg = G1_REG_APF_THRESHOLD(8);
 242         vdpu_write_relaxed(vpu, reg, G1_SWREG(55));
 243
 244         hantro_g1_mpeg2_dec_set_quantization(vpu, ctx);
 245
 246         hantro_g1_mpeg2_dec_set_buffers(vpu, ctx, &src_buf->vb2_buf,
 247                                         &dst_buf->vb2_buf,
 248                                         sequence, picture, slice_params);
 249
 250         hantro_finish_run(ctx);
 251
 252         reg = G1_REG_DEC_E(1);
 253         vdpu_write(vpu, reg, G1_SWREG(1));
 254 }