1 // SPDX-License-Identifier: GPL-2.0
3 * AD7190 AD7192 AD7193 AD7195 SPI ADC driver
5 * Copyright 2011-2015 Analog Devices Inc.
8 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/trigger.h>
24 #include <linux/iio/trigger_consumer.h>
25 #include <linux/iio/triggered_buffer.h>
26 #include <linux/iio/adc/ad_sigma_delta.h>
31 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
32 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
33 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
34 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
35 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
36 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
37 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
38 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
39 /* (AD7792)/24-bit (AD7192)) */
40 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
41 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
43 /* Communications Register Bit Designations (AD7192_REG_COMM) */
44 #define AD7192_COMM_WEN BIT(7) /* Write Enable */
45 #define AD7192_COMM_WRITE 0 /* Write Operation */
46 #define AD7192_COMM_READ BIT(6) /* Read Operation */
47 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
48 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
50 /* Status Register Bit Designations (AD7192_REG_STAT) */
51 #define AD7192_STAT_RDY BIT(7) /* Ready */
52 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
53 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
54 #define AD7192_STAT_PARITY BIT(4) /* Parity */
55 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
56 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
57 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
59 /* Mode Register Bit Designations (AD7192_REG_MODE) */
60 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
61 #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
62 #define AD7192_MODE_DAT_STA BIT(20) /* Status Register transmission */
63 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
64 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
65 #define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/
66 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
67 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
68 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
69 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
70 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
72 /* Mode Register: AD7192_MODE_SEL options */
73 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
74 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
75 #define AD7192_MODE_IDLE 2 /* Idle Mode */
76 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
77 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
78 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
79 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
80 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
82 /* Mode Register: AD7192_MODE_CLKSRC options */
83 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/
84 /* from MCLK1 to MCLK2 */
85 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
86 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */
87 /* available at the MCLK2 pin */
88 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/
89 /* at the MCLK2 pin */
91 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
93 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
94 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
95 #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */
96 #define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */
97 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
98 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
99 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
100 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
101 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
103 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
104 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
105 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */
106 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
107 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
108 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
109 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
110 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
112 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */
113 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */
114 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */
115 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */
116 #define AD7193_CH_TEMP 0x100 /* Temp senseor */
117 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
118 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
119 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
120 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
121 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
122 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
123 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
124 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
125 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
126 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
128 /* ID Register Bit Designations (AD7192_REG_ID) */
129 #define ID_AD7190 0x4
130 #define ID_AD7192 0x0
131 #define ID_AD7193 0x2
132 #define ID_AD7195 0x6
133 #define AD7192_ID_MASK 0x0F
135 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
136 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
137 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
138 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
139 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
140 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
141 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
142 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
144 #define AD7192_EXT_FREQ_MHZ_MIN 2457600
145 #define AD7192_EXT_FREQ_MHZ_MAX 5120000
146 #define AD7192_INT_FREQ_MHZ 4915200
149 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
150 * In order to avoid contentions on the SPI bus, it's therefore necessary
151 * to use spi bus locking.
153 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
156 struct ad7192_state {
157 struct regulator *avdd;
158 struct regulator *dvdd;
165 u32 scale_avail[8][2];
169 struct mutex lock; /* protect sensor state */
171 struct ad_sigma_delta sd;
174 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
176 return container_of(sd, struct ad7192_state, sd);
179 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
181 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
183 st->conf &= ~AD7192_CONF_CHAN_MASK;
184 st->conf |= AD7192_CONF_CHAN(channel);
186 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
189 static int ad7192_set_mode(struct ad_sigma_delta *sd,
190 enum ad_sigma_delta_mode mode)
192 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
194 st->mode &= ~AD7192_MODE_SEL_MASK;
195 st->mode |= AD7192_MODE_SEL(mode);
197 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
200 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
201 .set_channel = ad7192_set_channel,
202 .set_mode = ad7192_set_mode,
203 .has_registers = true,
208 static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
209 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
210 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
211 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
212 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
213 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
214 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
215 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
216 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
219 static int ad7192_calibrate_all(struct ad7192_state *st)
221 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
222 ARRAY_SIZE(ad7192_calib_arr));
225 static inline bool ad7192_valid_external_frequency(u32 freq)
227 return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
228 freq <= AD7192_EXT_FREQ_MHZ_MAX);
231 static int ad7192_of_clock_select(struct ad7192_state *st)
233 struct device_node *np = st->sd.spi->dev.of_node;
234 unsigned int clock_sel;
236 clock_sel = AD7192_CLK_INT;
238 /* use internal clock */
239 if (PTR_ERR(st->mclk) == -ENOENT) {
240 if (of_property_read_bool(np, "adi,int-clock-output-enable"))
241 clock_sel = AD7192_CLK_INT_CO;
243 if (of_property_read_bool(np, "adi,clock-xtal"))
244 clock_sel = AD7192_CLK_EXT_MCLK1_2;
246 clock_sel = AD7192_CLK_EXT_MCLK2;
252 static int ad7192_setup(struct ad7192_state *st, struct device_node *np)
254 struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);
255 bool rej60_en, sinc3_en, refin2_en, chop_en;
256 bool buf_en, bipolar, burnout_curr_en;
257 unsigned long long scale_uv;
260 /* reset the serial interface */
261 ret = ad_sd_reset(&st->sd, 48);
264 usleep_range(500, 1000); /* Wait for at least 500us */
266 /* write/read test for device presence */
267 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
271 id &= AD7192_ID_MASK;
274 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n",
277 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
278 AD7192_MODE_CLKSRC(st->clock_sel) |
279 AD7192_MODE_RATE(480);
281 st->conf = AD7192_CONF_GAIN(0);
283 rej60_en = of_property_read_bool(np, "adi,rejection-60-Hz-enable");
285 st->mode |= AD7192_MODE_REJ60;
287 sinc3_en = of_property_read_bool(np, "adi,sinc3-filter-enable");
289 st->mode |= AD7192_MODE_SINC3;
291 refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable");
292 if (refin2_en && st->devid != ID_AD7195)
293 st->conf |= AD7192_CONF_REFSEL;
295 chop_en = of_property_read_bool(np, "adi,chop-enable");
297 st->conf |= AD7192_CONF_CHOP;
299 st->f_order = 3; /* SINC 3rd order */
301 st->f_order = 4; /* SINC 4th order */
306 buf_en = of_property_read_bool(np, "adi,buffer-enable");
308 st->conf |= AD7192_CONF_BUF;
310 bipolar = of_property_read_bool(np, "bipolar");
312 st->conf |= AD7192_CONF_UNIPOLAR;
314 burnout_curr_en = of_property_read_bool(np,
315 "adi,burnout-currents-enable");
316 if (burnout_curr_en && buf_en && !chop_en) {
317 st->conf |= AD7192_CONF_BURN;
318 } else if (burnout_curr_en) {
319 dev_warn(&st->sd.spi->dev,
320 "Can't enable burnout currents: see CHOP or buffer\n");
323 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
327 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
331 ret = ad7192_calibrate_all(st);
335 /* Populate available ADC input ranges */
336 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
337 scale_uv = ((u64)st->int_vref_mv * 100000000)
338 >> (indio_dev->channels[0].scan_type.realbits -
339 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
342 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
343 st->scale_avail[i][0] = scale_uv;
349 static ssize_t ad7192_show_ac_excitation(struct device *dev,
350 struct device_attribute *attr,
353 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
354 struct ad7192_state *st = iio_priv(indio_dev);
356 return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
359 static ssize_t ad7192_show_bridge_switch(struct device *dev,
360 struct device_attribute *attr,
363 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
364 struct ad7192_state *st = iio_priv(indio_dev);
366 return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
369 static ssize_t ad7192_set(struct device *dev,
370 struct device_attribute *attr,
374 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
375 struct ad7192_state *st = iio_priv(indio_dev);
376 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
380 ret = strtobool(buf, &val);
384 ret = iio_device_claim_direct_mode(indio_dev);
388 switch ((u32)this_attr->address) {
389 case AD7192_REG_GPOCON:
391 st->gpocon |= AD7192_GPOCON_BPDSW;
393 st->gpocon &= ~AD7192_GPOCON_BPDSW;
395 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
397 case AD7192_REG_MODE:
399 st->mode |= AD7192_MODE_ACX;
401 st->mode &= ~AD7192_MODE_ACX;
403 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
409 iio_device_release_direct_mode(indio_dev);
411 return ret ? ret : len;
414 static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
415 ad7192_show_bridge_switch, ad7192_set,
418 static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
419 ad7192_show_ac_excitation, ad7192_set,
422 static struct attribute *ad7192_attributes[] = {
423 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
424 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
428 static const struct attribute_group ad7192_attribute_group = {
429 .attrs = ad7192_attributes,
432 static struct attribute *ad7195_attributes[] = {
433 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
437 static const struct attribute_group ad7195_attribute_group = {
438 .attrs = ad7195_attributes,
441 static unsigned int ad7192_get_temp_scale(bool unipolar)
443 return unipolar ? 2815 * 2 : 2815;
446 static int ad7192_read_raw(struct iio_dev *indio_dev,
447 struct iio_chan_spec const *chan,
452 struct ad7192_state *st = iio_priv(indio_dev);
453 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
456 case IIO_CHAN_INFO_RAW:
457 return ad_sigma_delta_single_conversion(indio_dev, chan, val);
458 case IIO_CHAN_INFO_SCALE:
459 switch (chan->type) {
461 mutex_lock(&st->lock);
462 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
463 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
464 mutex_unlock(&st->lock);
465 return IIO_VAL_INT_PLUS_NANO;
468 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
469 return IIO_VAL_INT_PLUS_NANO;
473 case IIO_CHAN_INFO_OFFSET:
475 *val = -(1 << (chan->scan_type.realbits - 1));
478 /* Kelvin to Celsius */
479 if (chan->type == IIO_TEMP)
480 *val -= 273 * ad7192_get_temp_scale(unipolar);
482 case IIO_CHAN_INFO_SAMP_FREQ:
484 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode));
491 static int ad7192_write_raw(struct iio_dev *indio_dev,
492 struct iio_chan_spec const *chan,
497 struct ad7192_state *st = iio_priv(indio_dev);
501 ret = iio_device_claim_direct_mode(indio_dev);
506 case IIO_CHAN_INFO_SCALE:
508 mutex_lock(&st->lock);
509 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
510 if (val2 == st->scale_avail[i][1]) {
513 st->conf &= ~AD7192_CONF_GAIN(-1);
514 st->conf |= AD7192_CONF_GAIN(i);
517 ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
519 ad7192_calibrate_all(st);
522 mutex_unlock(&st->lock);
524 case IIO_CHAN_INFO_SAMP_FREQ:
530 div = st->fclk / (val * st->f_order * 1024);
531 if (div < 1 || div > 1023) {
536 st->mode &= ~AD7192_MODE_RATE(-1);
537 st->mode |= AD7192_MODE_RATE(div);
538 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
544 iio_device_release_direct_mode(indio_dev);
549 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
550 struct iio_chan_spec const *chan,
554 case IIO_CHAN_INFO_SCALE:
555 return IIO_VAL_INT_PLUS_NANO;
556 case IIO_CHAN_INFO_SAMP_FREQ:
563 static int ad7192_read_avail(struct iio_dev *indio_dev,
564 struct iio_chan_spec const *chan,
565 const int **vals, int *type, int *length,
568 struct ad7192_state *st = iio_priv(indio_dev);
571 case IIO_CHAN_INFO_SCALE:
572 *vals = (int *)st->scale_avail;
573 *type = IIO_VAL_INT_PLUS_NANO;
574 /* Values are stored in a 2D matrix */
575 *length = ARRAY_SIZE(st->scale_avail) * 2;
577 return IIO_AVAIL_LIST;
583 static const struct iio_info ad7192_info = {
584 .read_raw = ad7192_read_raw,
585 .write_raw = ad7192_write_raw,
586 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
587 .read_avail = ad7192_read_avail,
588 .attrs = &ad7192_attribute_group,
589 .validate_trigger = ad_sd_validate_trigger,
592 static const struct iio_info ad7195_info = {
593 .read_raw = ad7192_read_raw,
594 .write_raw = ad7192_write_raw,
595 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
596 .read_avail = ad7192_read_avail,
597 .attrs = &ad7195_attribute_group,
598 .validate_trigger = ad_sd_validate_trigger,
601 static const struct iio_chan_spec ad7192_channels[] = {
602 AD_SD_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M, 24, 32, 0),
603 AD_SD_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M, 24, 32, 0),
604 AD_SD_TEMP_CHANNEL(2, AD7192_CH_TEMP, 24, 32, 0),
605 AD_SD_SHORTED_CHANNEL(3, 2, AD7192_CH_AIN2P_AIN2M, 24, 32, 0),
606 AD_SD_CHANNEL(4, 1, AD7192_CH_AIN1, 24, 32, 0),
607 AD_SD_CHANNEL(5, 2, AD7192_CH_AIN2, 24, 32, 0),
608 AD_SD_CHANNEL(6, 3, AD7192_CH_AIN3, 24, 32, 0),
609 AD_SD_CHANNEL(7, 4, AD7192_CH_AIN4, 24, 32, 0),
610 IIO_CHAN_SOFT_TIMESTAMP(8),
613 static const struct iio_chan_spec ad7193_channels[] = {
614 AD_SD_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M, 24, 32, 0),
615 AD_SD_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M, 24, 32, 0),
616 AD_SD_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M, 24, 32, 0),
617 AD_SD_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M, 24, 32, 0),
618 AD_SD_TEMP_CHANNEL(4, AD7193_CH_TEMP, 24, 32, 0),
619 AD_SD_SHORTED_CHANNEL(5, 2, AD7193_CH_AIN2P_AIN2M, 24, 32, 0),
620 AD_SD_CHANNEL(6, 1, AD7193_CH_AIN1, 24, 32, 0),
621 AD_SD_CHANNEL(7, 2, AD7193_CH_AIN2, 24, 32, 0),
622 AD_SD_CHANNEL(8, 3, AD7193_CH_AIN3, 24, 32, 0),
623 AD_SD_CHANNEL(9, 4, AD7193_CH_AIN4, 24, 32, 0),
624 AD_SD_CHANNEL(10, 5, AD7193_CH_AIN5, 24, 32, 0),
625 AD_SD_CHANNEL(11, 6, AD7193_CH_AIN6, 24, 32, 0),
626 AD_SD_CHANNEL(12, 7, AD7193_CH_AIN7, 24, 32, 0),
627 AD_SD_CHANNEL(13, 8, AD7193_CH_AIN8, 24, 32, 0),
628 IIO_CHAN_SOFT_TIMESTAMP(14),
631 static int ad7192_channels_config(struct iio_dev *indio_dev)
633 struct ad7192_state *st = iio_priv(indio_dev);
634 const struct iio_chan_spec *channels;
635 struct iio_chan_spec *chan;
640 channels = ad7193_channels;
641 indio_dev->num_channels = ARRAY_SIZE(ad7193_channels);
644 channels = ad7192_channels;
645 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
649 chan = devm_kcalloc(indio_dev->dev.parent, indio_dev->num_channels,
650 sizeof(*chan), GFP_KERNEL);
654 indio_dev->channels = chan;
656 for (i = 0; i < indio_dev->num_channels; i++) {
658 if (chan->type != IIO_TEMP)
659 chan->info_mask_shared_by_type_available |=
660 BIT(IIO_CHAN_INFO_SCALE);
667 static int ad7192_probe(struct spi_device *spi)
669 const struct ad7192_platform_data *pdata = dev_get_platdata(&spi->dev);
670 struct ad7192_state *st;
671 struct iio_dev *indio_dev;
672 int ret, voltage_uv = 0;
675 dev_err(&spi->dev, "no platform data?\n");
680 dev_err(&spi->dev, "no IRQ?\n");
684 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
688 st = iio_priv(indio_dev);
690 mutex_init(&st->lock);
692 st->avdd = devm_regulator_get(&spi->dev, "avdd");
693 if (IS_ERR(st->avdd))
694 return PTR_ERR(st->avdd);
696 ret = regulator_enable(st->avdd);
698 dev_err(&spi->dev, "Failed to enable specified AVdd supply\n");
702 st->dvdd = devm_regulator_get(&spi->dev, "dvdd");
703 if (IS_ERR(st->dvdd)) {
704 ret = PTR_ERR(st->dvdd);
705 goto error_disable_avdd;
708 ret = regulator_enable(st->dvdd);
710 dev_err(&spi->dev, "Failed to enable specified DVdd supply\n");
711 goto error_disable_avdd;
714 voltage_uv = regulator_get_voltage(st->avdd);
717 st->int_vref_mv = pdata->vref_mv;
719 st->int_vref_mv = voltage_uv / 1000;
721 dev_warn(&spi->dev, "reference voltage undefined\n");
723 spi_set_drvdata(spi, indio_dev);
724 st->devid = spi_get_device_id(spi)->driver_data;
725 indio_dev->dev.parent = &spi->dev;
726 indio_dev->name = spi_get_device_id(spi)->name;
727 indio_dev->modes = INDIO_DIRECT_MODE;
729 ret = ad7192_channels_config(indio_dev);
731 goto error_disable_dvdd;
733 if (st->devid == ID_AD7195)
734 indio_dev->info = &ad7195_info;
736 indio_dev->info = &ad7192_info;
738 ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);
740 ret = ad_sd_setup_buffer_and_trigger(indio_dev);
742 goto error_disable_dvdd;
744 st->fclk = AD7192_INT_FREQ_MHZ;
746 st->mclk = devm_clk_get(&st->sd.spi->dev, "mclk");
747 if (IS_ERR(st->mclk) && PTR_ERR(st->mclk) != -ENOENT) {
748 ret = PTR_ERR(st->mclk);
749 goto error_remove_trigger;
752 st->clock_sel = ad7192_of_clock_select(st);
754 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
755 st->clock_sel == AD7192_CLK_EXT_MCLK2) {
756 ret = clk_prepare_enable(st->mclk);
758 goto error_remove_trigger;
760 st->fclk = clk_get_rate(st->mclk);
761 if (!ad7192_valid_external_frequency(st->fclk)) {
764 "External clock frequency out of bounds\n");
765 goto error_disable_clk;
769 ret = ad7192_setup(st, spi->dev.of_node);
771 goto error_disable_clk;
773 ret = iio_device_register(indio_dev);
775 goto error_disable_clk;
779 clk_disable_unprepare(st->mclk);
780 error_remove_trigger:
781 ad_sd_cleanup_buffer_and_trigger(indio_dev);
783 regulator_disable(st->dvdd);
785 regulator_disable(st->avdd);
790 static int ad7192_remove(struct spi_device *spi)
792 struct iio_dev *indio_dev = spi_get_drvdata(spi);
793 struct ad7192_state *st = iio_priv(indio_dev);
795 iio_device_unregister(indio_dev);
796 clk_disable_unprepare(st->mclk);
797 ad_sd_cleanup_buffer_and_trigger(indio_dev);
799 regulator_disable(st->dvdd);
800 regulator_disable(st->avdd);
805 static const struct spi_device_id ad7192_id[] = {
806 {"ad7190", ID_AD7190},
807 {"ad7192", ID_AD7192},
808 {"ad7193", ID_AD7193},
809 {"ad7195", ID_AD7195},
812 MODULE_DEVICE_TABLE(spi, ad7192_id);
814 static struct spi_driver ad7192_driver = {
818 .probe = ad7192_probe,
819 .remove = ad7192_remove,
820 .id_table = ad7192_id,
822 module_spi_driver(ad7192_driver);
824 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
825 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC");
826 MODULE_LICENSE("GPL v2");