2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/sched.h> /* For jiffies, task states */
18 #include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */
19 #include <linux/delay.h> /* For udelay */
20 #include <linux/io.h> /* For read[bwl]/write[bwl] */
21 #include <linux/serial.h> /* For struct async_serial */
22 #include <linux/serial_reg.h> /* For the various UART offsets */
23 #include <linux/pci.h>
25 #include "dgnc_driver.h" /* Driver main header file */
29 static inline void cls_set_cts_flow_control(struct channel_t *ch)
31 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
32 unsigned char ier = readb(&ch->ch_cls_uart->ier);
33 unsigned char isr_fcr = 0;
36 * The Enhanced Register Set may only be accessed when
37 * the Line Control Register is set to 0xBFh.
39 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
41 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
43 /* Turn on CTS flow control, turn off IXON flow control */
44 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR);
45 isr_fcr &= ~(UART_EXAR654_EFR_IXON);
47 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
49 /* Write old LCR value back out, which turns enhanced access off */
50 writeb(lcrb, &ch->ch_cls_uart->lcr);
53 * Enable interrupts for CTS flow, turn off interrupts for
56 ier |= (UART_EXAR654_IER_CTSDSR);
57 ier &= ~(UART_EXAR654_IER_XOFF);
58 writeb(ier, &ch->ch_cls_uart->ier);
60 /* Set the usual FIFO values */
61 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
63 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
64 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
65 &ch->ch_cls_uart->isr_fcr);
70 static inline void cls_set_ixon_flow_control(struct channel_t *ch)
72 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
73 unsigned char ier = readb(&ch->ch_cls_uart->ier);
74 unsigned char isr_fcr = 0;
77 * The Enhanced Register Set may only be accessed when
78 * the Line Control Register is set to 0xBFh.
80 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
82 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
84 /* Turn on IXON flow control, turn off CTS flow control */
85 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON);
86 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR);
88 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
90 /* Now set our current start/stop chars while in enhanced mode */
91 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
92 writeb(0, &ch->ch_cls_uart->lsr);
93 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
94 writeb(0, &ch->ch_cls_uart->spr);
96 /* Write old LCR value back out, which turns enhanced access off */
97 writeb(lcrb, &ch->ch_cls_uart->lcr);
100 * Disable interrupts for CTS flow, turn on interrupts for
101 * received XOFF chars
103 ier &= ~(UART_EXAR654_IER_CTSDSR);
104 ier |= (UART_EXAR654_IER_XOFF);
105 writeb(ier, &ch->ch_cls_uart->ier);
107 /* Set the usual FIFO values */
108 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
110 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
111 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
112 &ch->ch_cls_uart->isr_fcr);
115 static inline void cls_set_no_output_flow_control(struct channel_t *ch)
117 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
118 unsigned char ier = readb(&ch->ch_cls_uart->ier);
119 unsigned char isr_fcr = 0;
122 * The Enhanced Register Set may only be accessed when
123 * the Line Control Register is set to 0xBFh.
125 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
127 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
129 /* Turn off IXON flow control, turn off CTS flow control */
130 isr_fcr |= (UART_EXAR654_EFR_ECB);
131 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON);
133 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
135 /* Write old LCR value back out, which turns enhanced access off */
136 writeb(lcrb, &ch->ch_cls_uart->lcr);
139 * Disable interrupts for CTS flow, turn off interrupts for
140 * received XOFF chars
142 ier &= ~(UART_EXAR654_IER_CTSDSR);
143 ier &= ~(UART_EXAR654_IER_XOFF);
144 writeb(ier, &ch->ch_cls_uart->ier);
146 /* Set the usual FIFO values */
147 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
149 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
150 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
151 &ch->ch_cls_uart->isr_fcr);
153 ch->ch_r_watermark = 0;
154 ch->ch_t_tlevel = 16;
155 ch->ch_r_tlevel = 16;
158 static inline void cls_set_rts_flow_control(struct channel_t *ch)
160 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
161 unsigned char ier = readb(&ch->ch_cls_uart->ier);
162 unsigned char isr_fcr = 0;
165 * The Enhanced Register Set may only be accessed when
166 * the Line Control Register is set to 0xBFh.
168 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
170 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
172 /* Turn on RTS flow control, turn off IXOFF flow control */
173 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR);
174 isr_fcr &= ~(UART_EXAR654_EFR_IXOFF);
176 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
178 /* Write old LCR value back out, which turns enhanced access off */
179 writeb(lcrb, &ch->ch_cls_uart->lcr);
181 /* Enable interrupts for RTS flow */
182 ier |= (UART_EXAR654_IER_RTSDTR);
183 writeb(ier, &ch->ch_cls_uart->ier);
185 /* Set the usual FIFO values */
186 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
188 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
189 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
190 &ch->ch_cls_uart->isr_fcr);
192 ch->ch_r_watermark = 4;
196 static inline void cls_set_ixoff_flow_control(struct channel_t *ch)
198 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
199 unsigned char ier = readb(&ch->ch_cls_uart->ier);
200 unsigned char isr_fcr = 0;
203 * The Enhanced Register Set may only be accessed when
204 * the Line Control Register is set to 0xBFh.
206 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
208 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
210 /* Turn on IXOFF flow control, turn off RTS flow control */
211 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF);
212 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR);
214 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
216 /* Now set our current start/stop chars while in enhanced mode */
217 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
218 writeb(0, &ch->ch_cls_uart->lsr);
219 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
220 writeb(0, &ch->ch_cls_uart->spr);
222 /* Write old LCR value back out, which turns enhanced access off */
223 writeb(lcrb, &ch->ch_cls_uart->lcr);
225 /* Disable interrupts for RTS flow */
226 ier &= ~(UART_EXAR654_IER_RTSDTR);
227 writeb(ier, &ch->ch_cls_uart->ier);
229 /* Set the usual FIFO values */
230 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
232 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
233 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
234 &ch->ch_cls_uart->isr_fcr);
237 static inline void cls_set_no_input_flow_control(struct channel_t *ch)
239 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
240 unsigned char ier = readb(&ch->ch_cls_uart->ier);
241 unsigned char isr_fcr = 0;
244 * The Enhanced Register Set may only be accessed when
245 * the Line Control Register is set to 0xBFh.
247 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
249 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
251 /* Turn off IXOFF flow control, turn off RTS flow control */
252 isr_fcr |= (UART_EXAR654_EFR_ECB);
253 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF);
255 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
257 /* Write old LCR value back out, which turns enhanced access off */
258 writeb(lcrb, &ch->ch_cls_uart->lcr);
260 /* Disable interrupts for RTS flow */
261 ier &= ~(UART_EXAR654_IER_RTSDTR);
262 writeb(ier, &ch->ch_cls_uart->ier);
264 /* Set the usual FIFO values */
265 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
267 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
268 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
269 &ch->ch_cls_uart->isr_fcr);
271 ch->ch_t_tlevel = 16;
272 ch->ch_r_tlevel = 16;
277 * Determines whether its time to shut off break condition.
279 * No locks are assumed to be held when calling this function.
280 * channel lock is held and released in this function.
282 static inline void cls_clear_break(struct channel_t *ch, int force)
286 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
289 spin_lock_irqsave(&ch->ch_lock, flags);
291 /* Bail if we aren't currently sending a break. */
292 if (!ch->ch_stop_sending_break) {
293 spin_unlock_irqrestore(&ch->ch_lock, flags);
297 /* Turn break off, and unset some variables */
298 if (ch->ch_flags & CH_BREAK_SENDING) {
299 if (time_after(jiffies, ch->ch_stop_sending_break) || force) {
300 unsigned char temp = readb(&ch->ch_cls_uart->lcr);
302 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
303 ch->ch_flags &= ~(CH_BREAK_SENDING);
304 ch->ch_stop_sending_break = 0;
307 spin_unlock_irqrestore(&ch->ch_lock, flags);
310 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch)
313 unsigned char linestatus = 0;
314 unsigned char error_mask = 0;
319 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
322 spin_lock_irqsave(&ch->ch_lock, flags);
324 /* cache head and tail of queue */
325 head = ch->ch_r_head;
326 tail = ch->ch_r_tail;
328 /* Store how much space we have left in the queue */
329 qleft = tail - head - 1;
331 qleft += RQUEUEMASK + 1;
334 * Create a mask to determine whether we should
335 * insert the character (if any) into our queue.
337 if (ch->ch_c_iflag & IGNBRK)
338 error_mask |= UART_LSR_BI;
341 linestatus = readb(&ch->ch_cls_uart->lsr);
343 if (!(linestatus & (UART_LSR_DR)))
347 * Discard character if we are ignoring the error mask.
349 if (linestatus & error_mask) {
351 readb(&ch->ch_cls_uart->txrx);
356 * If our queue is full, we have no choice but to drop some
357 * data. The assumption is that HWFLOW or SWFLOW should have
358 * stopped things way way before we got to this point.
360 * I decided that I wanted to ditch the oldest data first,
361 * I hope thats okay with everyone? Yes? Good.
364 tail = (tail + 1) & RQUEUEMASK;
365 ch->ch_r_tail = tail;
366 ch->ch_err_overrun++;
370 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
372 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
376 if (ch->ch_equeue[head] & UART_LSR_PE)
378 if (ch->ch_equeue[head] & UART_LSR_BI)
380 if (ch->ch_equeue[head] & UART_LSR_FE)
383 /* Add to, and flip head if needed */
384 head = (head + 1) & RQUEUEMASK;
388 /* Write new final heads to channel structure. */
390 ch->ch_r_head = head & RQUEUEMASK;
391 ch->ch_e_head = head & EQUEUEMASK;
393 spin_unlock_irqrestore(&ch->ch_lock, flags);
396 /* Make the UART raise any of the output signals we want up */
397 static void cls_assert_modem_signals(struct channel_t *ch)
401 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
406 if (ch->ch_flags & CH_LOOPBACK)
407 out |= UART_MCR_LOOP;
409 writeb(out, &ch->ch_cls_uart->mcr);
411 /* Give time for the UART to actually drop the signals */
415 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch)
421 uint len_written = 0;
424 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
427 spin_lock_irqsave(&ch->ch_lock, flags);
429 /* No data to write to the UART */
430 if (ch->ch_w_tail == ch->ch_w_head)
433 /* If port is "stopped", don't send any data to the UART */
434 if ((ch->ch_flags & CH_FORCED_STOP) ||
435 (ch->ch_flags & CH_BREAK_SENDING))
438 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
443 /* cache head and tail of queue */
444 head = ch->ch_w_head & WQUEUEMASK;
445 tail = ch->ch_w_tail & WQUEUEMASK;
446 qlen = (head - tail) & WQUEUEMASK;
448 /* Find minimum of the FIFO space, versus queue length */
453 * If RTS Toggle mode is on, turn on RTS now if not already set,
454 * and make sure we get an event when the data transfer has
457 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
458 if (!(ch->ch_mostat & UART_MCR_RTS)) {
459 ch->ch_mostat |= (UART_MCR_RTS);
460 cls_assert_modem_signals(ch);
462 ch->ch_tun.un_flags |= (UN_EMPTY);
466 * If DTR Toggle mode is on, turn on DTR now if not already set,
467 * and make sure we get an event when the data transfer has
470 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
471 if (!(ch->ch_mostat & UART_MCR_DTR)) {
472 ch->ch_mostat |= (UART_MCR_DTR);
473 cls_assert_modem_signals(ch);
475 ch->ch_tun.un_flags |= (UN_EMPTY);
477 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_cls_uart->txrx);
479 ch->ch_w_tail &= WQUEUEMASK;
486 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
489 spin_unlock_irqrestore(&ch->ch_lock, flags);
492 static void cls_parse_modem(struct channel_t *ch, unsigned char signals)
494 unsigned char msignals = signals;
497 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
501 * Do altpin switching. Altpin switches DCD and DSR.
502 * This prolly breaks DSRPACE, so we should be more clever here.
504 spin_lock_irqsave(&ch->ch_lock, flags);
505 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
506 unsigned char mswap = signals;
508 if (mswap & UART_MSR_DDCD) {
509 msignals &= ~UART_MSR_DDCD;
510 msignals |= UART_MSR_DDSR;
512 if (mswap & UART_MSR_DDSR) {
513 msignals &= ~UART_MSR_DDSR;
514 msignals |= UART_MSR_DDCD;
516 if (mswap & UART_MSR_DCD) {
517 msignals &= ~UART_MSR_DCD;
518 msignals |= UART_MSR_DSR;
520 if (mswap & UART_MSR_DSR) {
521 msignals &= ~UART_MSR_DSR;
522 msignals |= UART_MSR_DCD;
525 spin_unlock_irqrestore(&ch->ch_lock, flags);
528 * Scrub off lower bits. They signify delta's, which I don't
533 spin_lock_irqsave(&ch->ch_lock, flags);
534 if (msignals & UART_MSR_DCD)
535 ch->ch_mistat |= UART_MSR_DCD;
537 ch->ch_mistat &= ~UART_MSR_DCD;
539 if (msignals & UART_MSR_DSR)
540 ch->ch_mistat |= UART_MSR_DSR;
542 ch->ch_mistat &= ~UART_MSR_DSR;
544 if (msignals & UART_MSR_RI)
545 ch->ch_mistat |= UART_MSR_RI;
547 ch->ch_mistat &= ~UART_MSR_RI;
549 if (msignals & UART_MSR_CTS)
550 ch->ch_mistat |= UART_MSR_CTS;
552 ch->ch_mistat &= ~UART_MSR_CTS;
553 spin_unlock_irqrestore(&ch->ch_lock, flags);
556 /* Parse the ISR register for the specific port */
557 static inline void cls_parse_isr(struct dgnc_board *brd, uint port)
559 struct channel_t *ch;
560 unsigned char isr = 0;
564 * No need to verify board pointer, it was already
565 * verified in the interrupt routine.
568 if (port >= brd->nasync)
571 ch = brd->channels[port];
572 if (ch->magic != DGNC_CHANNEL_MAGIC)
575 /* Here we try to figure out what caused the interrupt to happen */
577 isr = readb(&ch->ch_cls_uart->isr_fcr);
579 /* Bail if no pending interrupt on port */
580 if (isr & UART_IIR_NO_INT)
583 /* Receive Interrupt pending */
584 if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) {
585 /* Read data from uart -> queue */
586 cls_copy_data_from_uart_to_queue(ch);
587 dgnc_check_queue_flow_control(ch);
590 /* Transmit Hold register empty pending */
591 if (isr & UART_IIR_THRI) {
592 /* Transfer data (if any) from Write Queue -> UART. */
593 spin_lock_irqsave(&ch->ch_lock, flags);
594 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
595 spin_unlock_irqrestore(&ch->ch_lock, flags);
596 cls_copy_data_from_queue_to_uart(ch);
599 /* Parse any modem signal changes */
600 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
604 /* Channel lock MUST be held before calling this function! */
605 static void cls_flush_uart_write(struct channel_t *ch)
607 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
610 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
611 &ch->ch_cls_uart->isr_fcr);
612 usleep_range(10, 20);
614 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
617 /* Channel lock MUST be held before calling this function! */
618 static void cls_flush_uart_read(struct channel_t *ch)
620 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
624 * For complete POSIX compatibility, we should be purging the
625 * read FIFO in the UART here.
627 * However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also
628 * incorrectly flushes write data as well as just basically trashing the
631 * Presumably, this is a bug in this UART.
639 * Send any/all changes to the line to the UART.
641 static void cls_param(struct tty_struct *tty)
643 unsigned char lcr = 0;
644 unsigned char uart_lcr = 0;
645 unsigned char ier = 0;
646 unsigned char uart_ier = 0;
649 struct dgnc_board *bd;
650 struct channel_t *ch;
653 if (!tty || tty->magic != TTY_MAGIC)
656 un = (struct un_t *)tty->driver_data;
657 if (!un || un->magic != DGNC_UNIT_MAGIC)
661 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
665 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
668 /* If baud rate is zero, flush queues, and set mval to drop DTR. */
670 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
678 cls_flush_uart_write(ch);
679 cls_flush_uart_read(ch);
681 /* The baudrate is B0 so all modem lines are to be dropped. */
682 ch->ch_flags |= (CH_BAUD0);
683 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
684 cls_assert_modem_signals(ch);
687 } else if (ch->ch_custom_speed) {
688 baud = ch->ch_custom_speed;
689 /* Handle transition from B0 */
690 if (ch->ch_flags & CH_BAUD0) {
691 ch->ch_flags &= ~(CH_BAUD0);
694 * Bring back up RTS and DTR...
695 * Also handle RTS or DTR toggle if set.
697 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
698 ch->ch_mostat |= (UART_MCR_RTS);
699 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
700 ch->ch_mostat |= (UART_MCR_DTR);
707 ulong bauds[4][16] = {
711 600, 1200, 1800, 2400,
712 4800, 9600, 19200, 38400 },
713 { /* slowbaud & CBAUDEX */
714 0, 57600, 115200, 230400,
715 460800, 150, 200, 921600,
716 600, 1200, 1800, 2400,
717 4800, 9600, 19200, 38400 },
719 0, 57600, 76800, 115200,
720 131657, 153600, 230400, 460800,
721 921600, 1200, 1800, 2400,
722 4800, 9600, 19200, 38400 },
723 { /* fastbaud & CBAUDEX */
724 0, 57600, 115200, 230400,
725 460800, 150, 200, 921600,
726 600, 1200, 1800, 2400,
727 4800, 9600, 19200, 38400 }
731 * Only use the TXPrint baud rate if the terminal
734 if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
735 (un->un_type == DGNC_PRINT))
736 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
738 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
740 if (ch->ch_c_cflag & CBAUDEX)
743 if (ch->ch_digi.digi_flags & DIGI_FAST)
748 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) &&
750 baud = bauds[iindex][jindex];
758 /* Handle transition from B0 */
759 if (ch->ch_flags & CH_BAUD0) {
760 ch->ch_flags &= ~(CH_BAUD0);
763 * Bring back up RTS and DTR...
764 * Also handle RTS or DTR toggle if set.
766 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
767 ch->ch_mostat |= (UART_MCR_RTS);
768 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
769 ch->ch_mostat |= (UART_MCR_DTR);
773 if (ch->ch_c_cflag & PARENB)
774 lcr |= UART_LCR_PARITY;
776 if (!(ch->ch_c_cflag & PARODD))
777 lcr |= UART_LCR_EPAR;
780 * Not all platforms support mark/space parity,
781 * so this will hide behind an ifdef.
784 if (ch->ch_c_cflag & CMSPAR)
785 lcr |= UART_LCR_SPAR;
788 if (ch->ch_c_cflag & CSTOPB)
789 lcr |= UART_LCR_STOP;
791 switch (ch->ch_c_cflag & CSIZE) {
793 lcr |= UART_LCR_WLEN5;
796 lcr |= UART_LCR_WLEN6;
799 lcr |= UART_LCR_WLEN7;
803 lcr |= UART_LCR_WLEN8;
807 uart_ier = readb(&ch->ch_cls_uart->ier);
809 uart_lcr = readb(&ch->ch_cls_uart->lcr);
814 quot = ch->ch_bd->bd_dividend / baud;
816 if (quot != 0 && ch->ch_old_baud != baud) {
817 ch->ch_old_baud = baud;
818 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);
819 writeb((quot & 0xff), &ch->ch_cls_uart->txrx);
820 writeb((quot >> 8), &ch->ch_cls_uart->ier);
821 writeb(lcr, &ch->ch_cls_uart->lcr);
825 writeb(lcr, &ch->ch_cls_uart->lcr);
827 if (ch->ch_c_cflag & CREAD)
828 ier |= (UART_IER_RDI | UART_IER_RLSI);
830 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
833 * Have the UART interrupt on modem signal changes ONLY when
834 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
836 if ((ch->ch_digi.digi_flags & CTSPACE) ||
837 (ch->ch_digi.digi_flags & RTSPACE) ||
838 (ch->ch_c_cflag & CRTSCTS) ||
839 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
840 !(ch->ch_c_cflag & CLOCAL))
843 ier &= ~UART_IER_MSI;
845 ier |= UART_IER_THRI;
848 writeb(ier, &ch->ch_cls_uart->ier);
850 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
851 cls_set_cts_flow_control(ch);
852 } else if (ch->ch_c_iflag & IXON) {
854 * If start/stop is set to disable, then we should
855 * disable flow control
857 if ((ch->ch_startc == _POSIX_VDISABLE) ||
858 (ch->ch_stopc == _POSIX_VDISABLE))
859 cls_set_no_output_flow_control(ch);
861 cls_set_ixon_flow_control(ch);
863 cls_set_no_output_flow_control(ch);
866 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
867 cls_set_rts_flow_control(ch);
868 } else if (ch->ch_c_iflag & IXOFF) {
870 * If start/stop is set to disable, then we should disable
873 if ((ch->ch_startc == _POSIX_VDISABLE) ||
874 (ch->ch_stopc == _POSIX_VDISABLE))
875 cls_set_no_input_flow_control(ch);
877 cls_set_ixoff_flow_control(ch);
879 cls_set_no_input_flow_control(ch);
882 cls_assert_modem_signals(ch);
884 /* Get current status of the modem signals now */
885 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
888 /* Our board poller function. */
890 static void cls_tasklet(unsigned long data)
892 struct dgnc_board *bd = (struct dgnc_board *)data;
893 struct channel_t *ch;
899 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
902 /* Cache a couple board values */
903 spin_lock_irqsave(&bd->bd_lock, flags);
906 spin_unlock_irqrestore(&bd->bd_lock, flags);
909 * Do NOT allow the interrupt routine to read the intr registers
910 * Until we release this lock.
912 spin_lock_irqsave(&bd->bd_intr_lock, flags);
914 /* If board is ready, parse deeper to see if there is anything to do. */
916 if ((state == BOARD_READY) && (ports > 0)) {
917 /* Loop on each port */
918 for (i = 0; i < ports; i++) {
919 ch = bd->channels[i];
922 * NOTE: Remember you CANNOT hold any channel
923 * locks when calling input.
924 * During input processing, its possible we
925 * will call ld, which might do callbacks back
931 * Channel lock is grabbed and then released
932 * inside this routine.
934 cls_copy_data_from_queue_to_uart(ch);
935 dgnc_wakeup_writes(ch);
937 /* Check carrier function. */
942 * The timing check of turning off the break is done
943 * inside clear_break()
945 if (ch->ch_stop_sending_break)
946 cls_clear_break(ch, 0);
950 spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
956 * Classic specific interrupt handler.
958 static irqreturn_t cls_intr(int irq, void *voidbrd)
960 struct dgnc_board *brd = voidbrd;
962 unsigned char poll_reg;
966 * Check to make sure it didn't receive interrupt with a null board
967 * associated or a board pointer that wasn't ours.
969 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
972 spin_lock_irqsave(&brd->bd_intr_lock, flags);
975 * Check the board's global interrupt offset to see if we
976 * we actually do have an interrupt pending for us.
978 poll_reg = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET);
980 /* If 0, no interrupts pending */
982 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
986 /* Parse each port to find out what caused the interrupt */
987 for (i = 0; i < brd->nasync; i++)
988 cls_parse_isr(brd, i);
990 /* Schedule tasklet to more in-depth servicing at a better time. */
992 tasklet_schedule(&brd->helper_tasklet);
994 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
999 static void cls_disable_receiver(struct channel_t *ch)
1001 unsigned char tmp = readb(&ch->ch_cls_uart->ier);
1003 tmp &= ~(UART_IER_RDI);
1004 writeb(tmp, &ch->ch_cls_uart->ier);
1007 static void cls_enable_receiver(struct channel_t *ch)
1009 unsigned char tmp = readb(&ch->ch_cls_uart->ier);
1011 tmp |= (UART_IER_RDI);
1012 writeb(tmp, &ch->ch_cls_uart->ier);
1016 * This function basically goes to sleep for secs, or until
1017 * it gets signalled that the port has fully drained.
1019 static int cls_drain(struct tty_struct *tty, uint seconds)
1021 unsigned long flags;
1022 struct channel_t *ch;
1025 if (!tty || tty->magic != TTY_MAGIC)
1028 un = (struct un_t *)tty->driver_data;
1029 if (!un || un->magic != DGNC_UNIT_MAGIC)
1033 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1036 spin_lock_irqsave(&ch->ch_lock, flags);
1037 un->un_flags |= UN_EMPTY;
1038 spin_unlock_irqrestore(&ch->ch_lock, flags);
1040 /* NOTE: Do something with time passed in. */
1042 /* If ret is non-zero, user ctrl-c'ed us */
1044 return wait_event_interruptible(un->un_flags_wait,
1045 ((un->un_flags & UN_EMPTY) == 0));
1048 static void cls_send_start_character(struct channel_t *ch)
1050 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1053 if (ch->ch_startc != _POSIX_VDISABLE) {
1055 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);
1059 static void cls_send_stop_character(struct channel_t *ch)
1061 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1064 if (ch->ch_stopc != _POSIX_VDISABLE) {
1065 ch->ch_xoff_sends++;
1066 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);
1071 static void cls_uart_init(struct channel_t *ch)
1073 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
1074 unsigned char isr_fcr = 0;
1076 writeb(0, &ch->ch_cls_uart->ier);
1079 * The Enhanced Register Set may only be accessed when
1080 * the Line Control Register is set to 0xBFh.
1082 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
1084 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
1086 /* Turn on Enhanced/Extended controls */
1087 isr_fcr |= (UART_EXAR654_EFR_ECB);
1089 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
1091 /* Write old LCR value back out, which turns enhanced access off */
1092 writeb(lcrb, &ch->ch_cls_uart->lcr);
1094 /* Clear out UART and FIFO */
1095 readb(&ch->ch_cls_uart->txrx);
1097 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1098 &ch->ch_cls_uart->isr_fcr);
1101 ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1103 readb(&ch->ch_cls_uart->lsr);
1104 readb(&ch->ch_cls_uart->msr);
1107 /* Turns off UART. */
1109 static void cls_uart_off(struct channel_t *ch)
1111 writeb(0, &ch->ch_cls_uart->ier);
1115 * cls_get_uarts_bytes_left.
1116 * Returns 0 is nothing left in the FIFO, returns 1 otherwise.
1118 * The channel lock MUST be held by the calling function.
1120 static uint cls_get_uart_bytes_left(struct channel_t *ch)
1122 unsigned char left = 0;
1123 unsigned char lsr = 0;
1125 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1128 lsr = readb(&ch->ch_cls_uart->lsr);
1130 /* Determine whether the Transmitter is empty or not */
1131 if (!(lsr & UART_LSR_TEMT)) {
1132 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1133 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1136 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1145 * Starts sending a break thru the UART.
1147 * The channel lock MUST be held by the calling function.
1149 static void cls_send_break(struct channel_t *ch, int msecs)
1151 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1154 /* If we receive a time of 0, this means turn off the break. */
1157 /* Turn break off, and unset some variables */
1158 if (ch->ch_flags & CH_BREAK_SENDING) {
1159 unsigned char temp = readb(&ch->ch_cls_uart->lcr);
1161 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1162 ch->ch_flags &= ~(CH_BREAK_SENDING);
1163 ch->ch_stop_sending_break = 0;
1169 * Set the time we should stop sending the break.
1170 * If we are already sending a break, toss away the existing
1171 * time to stop, and use this new value instead.
1173 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1175 /* Tell the UART to start sending the break */
1176 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1177 unsigned char temp = readb(&ch->ch_cls_uart->lcr);
1179 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1180 ch->ch_flags |= (CH_BREAK_SENDING);
1185 * cls_send_immediate_char.
1186 * Sends a specific character as soon as possible to the UART,
1187 * jumping over any bytes that might be in the write queue.
1189 * The channel lock MUST be held by the calling function.
1191 static void cls_send_immediate_char(struct channel_t *ch, unsigned char c)
1193 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1196 writeb(c, &ch->ch_cls_uart->txrx);
1199 static void cls_vpd(struct dgnc_board *brd)
1201 ulong vpdbase; /* Start of io base of the card */
1202 u8 __iomem *re_map_vpdbase;/* Remapped memory of the card */
1205 vpdbase = pci_resource_start(brd->pdev, 3);
1211 re_map_vpdbase = ioremap(vpdbase, 0x400);
1213 if (!re_map_vpdbase)
1216 /* Store the VPD into our buffer */
1217 for (i = 0; i < 0x40; i++) {
1218 brd->vpd[i] = readb(re_map_vpdbase + i);
1219 pr_info("%x ", brd->vpd[i]);
1223 iounmap(re_map_vpdbase);
1226 struct board_ops dgnc_cls_ops = {
1227 .tasklet = cls_tasklet,
1229 .uart_init = cls_uart_init,
1230 .uart_off = cls_uart_off,
1234 .assert_modem_signals = cls_assert_modem_signals,
1235 .flush_uart_write = cls_flush_uart_write,
1236 .flush_uart_read = cls_flush_uart_read,
1237 .disable_receiver = cls_disable_receiver,
1238 .enable_receiver = cls_enable_receiver,
1239 .send_break = cls_send_break,
1240 .send_start_character = cls_send_start_character,
1241 .send_stop_character = cls_send_stop_character,
1242 .copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart,
1243 .get_uart_bytes_left = cls_get_uart_bytes_left,
1244 .send_immediate_char = cls_send_immediate_char