drivers/staging/comedi/drivers/ni_pcidio.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Comedi driver for National Instruments PCI-DIO-32HS
   4  *
   5  * COMEDI - Linux Control and Measurement Device Interface
   6  * Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org>
   7  */
   8
   9 /*
  10  * Driver: ni_pcidio
  11  * Description: National Instruments PCI-DIO32HS, PCI-6533
  12  * Author: ds
  13  * Status: works
  14  * Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio)
  15  *   [National Instruments] PXI-6533, PCI-6533 (pxi-6533)
  16  *   [National Instruments] PCI-6534 (pci-6534)
  17  * Updated: Mon, 09 Jan 2012 14:27:23 +0000
  18  *
  19  * The DIO32HS board appears as one subdevice, with 32 channels. Each
  20  * channel is individually I/O configurable. The channel order is 0=A0,
  21  * 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only supports simple
  22  * digital I/O; no handshaking is supported.
  23  *
  24  * DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
  25  *
  26  * The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
  27  * scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
  28  * scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
  29  * trailing edge.
  30  *
  31  * This driver could be easily modified to support AT-MIO32HS and AT-MIO96.
  32  *
  33  * The PCI-6534 requires a firmware upload after power-up to work, the
  34  * firmware data and instructions for loading it with comedi_config
  35  * it are contained in the comedi_nonfree_firmware tarball available from
  36  * http://www.comedi.org
  37  */
  38
  39 #define USE_DMA
  40
  41 #include <linux/module.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/sched.h>
  45
  46 #include "../comedi_pci.h"
  47
  48 #include "mite.h"
  49
  50 /* defines for the PCI-DIO-32HS */
  51
  52 #define WINDOW_ADDRESS                  4       /* W */
  53 #define INTERRUPT_AND_WINDOW_STATUS     4       /* R */
  54 #define INT_STATUS_1                            BIT(0)
  55 #define INT_STATUS_2                            BIT(1)
  56 #define WINDOW_ADDRESS_STATUS_MASK              0x7c
  57
  58 #define MASTER_DMA_AND_INTERRUPT_CONTROL 5      /* W */
  59 #define INTERRUPT_LINE(x)                       ((x) & 3)
  60 #define OPEN_INT                                BIT(2)
  61 #define GROUP_STATUS                    5       /* R */
  62 #define DATA_LEFT                               BIT(0)
  63 #define REQ                                     BIT(2)
  64 #define STOP_TRIG                               BIT(3)
  65
  66 #define GROUP_1_FLAGS                   6       /* R */
  67 #define GROUP_2_FLAGS                   7       /* R */
  68 #define TRANSFER_READY                          BIT(0)
  69 #define COUNT_EXPIRED                           BIT(1)
  70 #define WAITED                                  BIT(5)
  71 #define PRIMARY_TC                              BIT(6)
  72 #define SECONDARY_TC                            BIT(7)
  73   /* #define SerialRose */
  74   /* #define ReqRose */
  75   /* #define Paused */
  76
  77 #define GROUP_1_FIRST_CLEAR             6       /* W */
  78 #define GROUP_2_FIRST_CLEAR             7       /* W */
  79 #define CLEAR_WAITED                            BIT(3)
  80 #define CLEAR_PRIMARY_TC                        BIT(4)
  81 #define CLEAR_SECONDARY_TC                      BIT(5)
  82 #define DMA_RESET                               BIT(6)
  83 #define FIFO_RESET                              BIT(7)
  84 #define CLEAR_ALL                               0xf8
  85
  86 #define GROUP_1_FIFO                    8       /* W */
  87 #define GROUP_2_FIFO                    12      /* W */
  88
  89 #define TRANSFER_COUNT                  20
  90 #define CHIP_ID_D                       24
  91 #define CHIP_ID_I                       25
  92 #define CHIP_ID_O                       26
  93 #define CHIP_VERSION                    27
  94 #define PORT_IO(x)                      (28 + (x))
  95 #define PORT_PIN_DIRECTIONS(x)          (32 + (x))
  96 #define PORT_PIN_MASK(x)                (36 + (x))
  97 #define PORT_PIN_POLARITIES(x)          (40 + (x))
  98
  99 #define MASTER_CLOCK_ROUTING            45
 100 #define RTSI_CLOCKING(x)                        (((x) & 3) << 4)
 101
 102 #define GROUP_1_SECOND_CLEAR            46      /* W */
 103 #define GROUP_2_SECOND_CLEAR            47      /* W */
 104 #define CLEAR_EXPIRED                           BIT(0)
 105
 106 #define PORT_PATTERN(x)                 (48 + (x))
 107
 108 #define DATA_PATH                       64
 109 #define FIFO_ENABLE_A           BIT(0)
 110 #define FIFO_ENABLE_B           BIT(1)
 111 #define FIFO_ENABLE_C           BIT(2)
 112 #define FIFO_ENABLE_D           BIT(3)
 113 #define FUNNELING(x)            (((x) & 3) << 4)
 114 #define GROUP_DIRECTION         BIT(7)
 115
 116 #define PROTOCOL_REGISTER_1             65
 117 #define OP_MODE                 PROTOCOL_REGISTER_1
 118 #define RUN_MODE(x)             ((x) & 7)
 119 #define NUMBERED                BIT(3)
 120
 121 #define PROTOCOL_REGISTER_2             66
 122 #define CLOCK_REG                       PROTOCOL_REGISTER_2
 123 #define CLOCK_LINE(x)           (((x) & 3) << 5)
 124 #define INVERT_STOP_TRIG                BIT(7)
 125 #define DATA_LATCHING(x)       (((x) & 3) << 5)
 126
 127 #define PROTOCOL_REGISTER_3             67
 128 #define SEQUENCE                        PROTOCOL_REGISTER_3
 129
 130 #define PROTOCOL_REGISTER_14            68      /* 16 bit */
 131 #define CLOCK_SPEED                     PROTOCOL_REGISTER_14
 132
 133 #define PROTOCOL_REGISTER_4             70
 134 #define REQ_REG                 PROTOCOL_REGISTER_4
 135 #define REQ_CONDITIONING(x)     (((x) & 7) << 3)
 136
 137 #define PROTOCOL_REGISTER_5             71
 138 #define BLOCK_MODE                      PROTOCOL_REGISTER_5
 139
 140 #define FIFO_Control                    72
 141 #define READY_LEVEL(x)          ((x) & 7)
 142
 143 #define PROTOCOL_REGISTER_6             73
 144 #define LINE_POLARITIES         PROTOCOL_REGISTER_6
 145 #define INVERT_ACK              BIT(0)
 146 #define INVERT_REQ              BIT(1)
 147 #define INVERT_CLOCK            BIT(2)
 148 #define INVERT_SERIAL           BIT(3)
 149 #define OPEN_ACK                BIT(4)
 150 #define OPEN_CLOCK              BIT(5)
 151
 152 #define PROTOCOL_REGISTER_7             74
 153 #define ACK_SER                 PROTOCOL_REGISTER_7
 154 #define ACK_LINE(x)             (((x) & 3) << 2)
 155 #define EXCHANGE_PINS           BIT(7)
 156
 157 #define INTERRUPT_CONTROL               75
 158 /* bits same as flags */
 159
 160 #define DMA_LINE_CONTROL_GROUP1         76
 161 #define DMA_LINE_CONTROL_GROUP2         108
 162
 163 /* channel zero is none */
 164 static inline unsigned int primary_DMAChannel_bits(unsigned int channel)
 165 {
 166         return channel & 0x3;
 167 }
 168
 169 static inline unsigned int secondary_DMAChannel_bits(unsigned int channel)
 170 {
 171         return (channel << 2) & 0xc;
 172 }
 173
 174 #define TRANSFER_SIZE_CONTROL           77
 175 #define TRANSFER_WIDTH(x)       ((x) & 3)
 176 #define TRANSFER_LENGTH(x)      (((x) & 3) << 3)
 177 #define REQUIRE_R_LEVEL        BIT(5)
 178
 179 #define PROTOCOL_REGISTER_15            79
 180 #define DAQ_OPTIONS                     PROTOCOL_REGISTER_15
 181 #define START_SOURCE(x)                 ((x) & 0x3)
 182 #define INVERT_START                            BIT(2)
 183 #define STOP_SOURCE(x)                          (((x) & 0x3) << 3)
 184 #define REQ_START                               BIT(6)
 185 #define PRE_START                               BIT(7)
 186
 187 #define PATTERN_DETECTION               81
 188 #define DETECTION_METHOD                        BIT(0)
 189 #define INVERT_MATCH                            BIT(1)
 190 #define IE_PATTERN_DETECTION                    BIT(2)
 191
 192 #define PROTOCOL_REGISTER_9             82
 193 #define REQ_DELAY                       PROTOCOL_REGISTER_9
 194
 195 #define PROTOCOL_REGISTER_10            83
 196 #define REQ_NOT_DELAY                   PROTOCOL_REGISTER_10
 197
 198 #define PROTOCOL_REGISTER_11            84
 199 #define ACK_DELAY                       PROTOCOL_REGISTER_11
 200
 201 #define PROTOCOL_REGISTER_12            85
 202 #define ACK_NOT_DELAY                   PROTOCOL_REGISTER_12
 203
 204 #define PROTOCOL_REGISTER_13            86
 205 #define DATA_1_DELAY                    PROTOCOL_REGISTER_13
 206
 207 #define PROTOCOL_REGISTER_8             88      /* 32 bit */
 208 #define START_DELAY                     PROTOCOL_REGISTER_8
 209
 210 /* Firmware files for PCI-6524 */
 211 #define FW_PCI_6534_MAIN                "/*(DEBLOBBED)*/"
 212 #define FW_PCI_6534_SCARAB_DI           "/*(DEBLOBBED)*/"
 213 #define FW_PCI_6534_SCARAB_DO           "/*(DEBLOBBED)*/"
 214 /*(DEBLOBBED)*/
 215
 216 enum pci_6534_firmware_registers {      /* 16 bit */
 217         Firmware_Control_Register = 0x100,
 218         Firmware_Status_Register = 0x104,
 219         Firmware_Data_Register = 0x108,
 220         Firmware_Mask_Register = 0x10c,
 221         Firmware_Debug_Register = 0x110,
 222 };
 223
 224 /* main fpga registers (32 bit)*/
 225 enum pci_6534_fpga_registers {
 226         FPGA_Control1_Register = 0x200,
 227         FPGA_Control2_Register = 0x204,
 228         FPGA_Irq_Mask_Register = 0x208,
 229         FPGA_Status_Register = 0x20c,
 230         FPGA_Signature_Register = 0x210,
 231         FPGA_SCALS_Counter_Register = 0x280,    /*write-clear */
 232         FPGA_SCAMS_Counter_Register = 0x284,    /*write-clear */
 233         FPGA_SCBLS_Counter_Register = 0x288,    /*write-clear */
 234         FPGA_SCBMS_Counter_Register = 0x28c,    /*write-clear */
 235         FPGA_Temp_Control_Register = 0x2a0,
 236         FPGA_DAR_Register = 0x2a8,
 237         FPGA_ELC_Read_Register = 0x2b8,
 238         FPGA_ELC_Write_Register = 0x2bc,
 239 };
 240
 241 enum FPGA_Control_Bits {
 242         FPGA_Enable_Bit = 0x8000,
 243 };
 244
 245 #define TIMER_BASE 50           /* nanoseconds */
 246
 247 #ifdef USE_DMA
 248 #define INT_EN (COUNT_EXPIRED | WAITED | PRIMARY_TC | SECONDARY_TC)
 249 #else
 250 #define INT_EN (TRANSFER_READY | COUNT_EXPIRED | WAITED \
 251                 | PRIMARY_TC | SECONDARY_TC)
 252 #endif
 253
 254 enum nidio_boardid {
 255         BOARD_PCIDIO_32HS,
 256         BOARD_PXI6533,
 257         BOARD_PCI6534,
 258 };
 259
 260 struct nidio_board {
 261         const char *name;
 262         unsigned int uses_firmware:1;
 263         unsigned int dio_speed;
 264 };
 265
 266 static const struct nidio_board nidio_boards[] = {
 267         [BOARD_PCIDIO_32HS] = {
 268                 .name           = "pci-dio-32hs",
 269                 .dio_speed      = 50,
 270         },
 271         [BOARD_PXI6533] = {
 272                 .name           = "pxi-6533",
 273                 .dio_speed      = 50,
 274         },
 275         [BOARD_PCI6534] = {
 276                 .name           = "pci-6534",
 277                 .uses_firmware  = 1,
 278                 .dio_speed      = 50,
 279         },
 280 };
 281
 282 struct nidio96_private {
 283         struct mite *mite;
 284         int boardtype;
 285         int dio;
 286         unsigned short OP_MODEBits;
 287         struct mite_channel *di_mite_chan;
 288         struct mite_ring *di_mite_ring;
 289         spinlock_t mite_channel_lock;
 290 };
 291
 292 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
 293 {
 294         struct nidio96_private *devpriv = dev->private;
 295         unsigned long flags;
 296
 297         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 298         BUG_ON(devpriv->di_mite_chan);
 299         devpriv->di_mite_chan =
 300             mite_request_channel_in_range(devpriv->mite,
 301                                           devpriv->di_mite_ring, 1, 2);
 302         if (!devpriv->di_mite_chan) {
 303                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 304                 dev_err(dev->class_dev, "failed to reserve mite dma channel\n");
 305                 return -EBUSY;
 306         }
 307         devpriv->di_mite_chan->dir = COMEDI_INPUT;
 308         writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
 309                secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
 310                dev->mmio + DMA_LINE_CONTROL_GROUP1);
 311         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 312         return 0;
 313 }
 314
 315 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
 316 {
 317         struct nidio96_private *devpriv = dev->private;
 318         unsigned long flags;
 319
 320         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 321         if (devpriv->di_mite_chan) {
 322                 mite_release_channel(devpriv->di_mite_chan);
 323                 devpriv->di_mite_chan = NULL;
 324                 writeb(primary_DMAChannel_bits(0) |
 325                        secondary_DMAChannel_bits(0),
 326                        dev->mmio + DMA_LINE_CONTROL_GROUP1);
 327         }
 328         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 329 }
 330
 331 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
 332 {
 333         struct nidio96_private *devpriv = dev->private;
 334         int retval;
 335         unsigned long flags;
 336
 337         retval = ni_pcidio_request_di_mite_channel(dev);
 338         if (retval)
 339                 return retval;
 340
 341         /* write alloc the entire buffer */
 342         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
 343
 344         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 345         if (devpriv->di_mite_chan) {
 346                 mite_prep_dma(devpriv->di_mite_chan, 32, 32);
 347                 mite_dma_arm(devpriv->di_mite_chan);
 348         } else {
 349                 retval = -EIO;
 350         }
 351         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 352
 353         return retval;
 354 }
 355
 356 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
 357 {
 358         struct nidio96_private *devpriv = dev->private;
 359         unsigned long irq_flags;
 360         int count;
 361
 362         spin_lock_irqsave(&dev->spinlock, irq_flags);
 363         spin_lock(&devpriv->mite_channel_lock);
 364         if (devpriv->di_mite_chan)
 365                 mite_sync_dma(devpriv->di_mite_chan, s);
 366         spin_unlock(&devpriv->mite_channel_lock);
 367         count = comedi_buf_n_bytes_ready(s);
 368         spin_unlock_irqrestore(&dev->spinlock, irq_flags);
 369         return count;
 370 }
 371
 372 static irqreturn_t nidio_interrupt(int irq, void *d)
 373 {
 374         struct comedi_device *dev = d;
 375         struct nidio96_private *devpriv = dev->private;
 376         struct comedi_subdevice *s = dev->read_subdev;
 377         struct comedi_async *async = s->async;
 378         unsigned int auxdata;
 379         int flags;
 380         int status;
 381         int work = 0;
 382
 383         /* interrupcions parasites */
 384         if (!dev->attached) {
 385                 /* assume it's from another card */
 386                 return IRQ_NONE;
 387         }
 388
 389         /* Lock to avoid race with comedi_poll */
 390         spin_lock(&dev->spinlock);
 391
 392         status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS);
 393         flags = readb(dev->mmio + GROUP_1_FLAGS);
 394
 395         spin_lock(&devpriv->mite_channel_lock);
 396         if (devpriv->di_mite_chan) {
 397                 mite_ack_linkc(devpriv->di_mite_chan, s, false);
 398                 /* XXX need to byteswap sync'ed dma */
 399         }
 400         spin_unlock(&devpriv->mite_channel_lock);
 401
 402         while (status & DATA_LEFT) {
 403                 work++;
 404                 if (work > 20) {
 405                         dev_dbg(dev->class_dev, "too much work in interrupt\n");
 406                         writeb(0x00,
 407                                dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
 408                         break;
 409                 }
 410
 411                 flags &= INT_EN;
 412
 413                 if (flags & TRANSFER_READY) {
 414                         while (flags & TRANSFER_READY) {
 415                                 work++;
 416                                 if (work > 100) {
 417                                         dev_dbg(dev->class_dev,
 418                                                 "too much work in interrupt\n");
 419                                         writeb(0x00, dev->mmio +
 420                                                MASTER_DMA_AND_INTERRUPT_CONTROL
 421                                               );
 422                                         goto out;
 423                                 }
 424                                 auxdata = readl(dev->mmio + GROUP_1_FIFO);
 425                                 comedi_buf_write_samples(s, &auxdata, 1);
 426                                 flags = readb(dev->mmio + GROUP_1_FLAGS);
 427                         }
 428                 }
 429
 430                 if (flags & COUNT_EXPIRED) {
 431                         writeb(CLEAR_EXPIRED, dev->mmio + GROUP_1_SECOND_CLEAR);
 432                         async->events |= COMEDI_CB_EOA;
 433
 434                         writeb(0x00, dev->mmio + OP_MODE);
 435                         break;
 436                 } else if (flags & WAITED) {
 437                         writeb(CLEAR_WAITED, dev->mmio + GROUP_1_FIRST_CLEAR);
 438                         async->events |= COMEDI_CB_ERROR;
 439                         break;
 440                 } else if (flags & PRIMARY_TC) {
 441                         writeb(CLEAR_PRIMARY_TC,
 442                                dev->mmio + GROUP_1_FIRST_CLEAR);
 443                         async->events |= COMEDI_CB_EOA;
 444                 } else if (flags & SECONDARY_TC) {
 445                         writeb(CLEAR_SECONDARY_TC,
 446                                dev->mmio + GROUP_1_FIRST_CLEAR);
 447                         async->events |= COMEDI_CB_EOA;
 448                 }
 449
 450                 flags = readb(dev->mmio + GROUP_1_FLAGS);
 451                 status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS);
 452         }
 453
 454 out:
 455         comedi_handle_events(dev, s);
 456 #if 0
 457         if (!tag)
 458                 writeb(0x03, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
 459 #endif
 460
 461         spin_unlock(&dev->spinlock);
 462         return IRQ_HANDLED;
 463 }
 464
 465 static int ni_pcidio_insn_config(struct comedi_device *dev,
 466                                  struct comedi_subdevice *s,
 467                                  struct comedi_insn *insn,
 468                                  unsigned int *data)
 469 {
 470         int ret;
 471
 472         if (data[0] == INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS) {
 473                 const struct nidio_board *board = dev->board_ptr;
 474
 475                 /* we don't care about actual channels */
 476                 data[1] = board->dio_speed;
 477                 data[2] = 0;
 478                 return 0;
 479         }
 480
 481         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
 482         if (ret)
 483                 return ret;
 484
 485         writel(s->io_bits, dev->mmio + PORT_PIN_DIRECTIONS(0));
 486
 487         return insn->n;
 488 }
 489
 490 static int ni_pcidio_insn_bits(struct comedi_device *dev,
 491                                struct comedi_subdevice *s,
 492                                struct comedi_insn *insn,
 493                                unsigned int *data)
 494 {
 495         if (comedi_dio_update_state(s, data))
 496                 writel(s->state, dev->mmio + PORT_IO(0));
 497
 498         data[1] = readl(dev->mmio + PORT_IO(0));
 499
 500         return insn->n;
 501 }
 502
 503 static int ni_pcidio_ns_to_timer(int *nanosec, unsigned int flags)
 504 {
 505         int divider, base;
 506
 507         base = TIMER_BASE;
 508
 509         switch (flags & CMDF_ROUND_MASK) {
 510         case CMDF_ROUND_NEAREST:
 511         default:
 512                 divider = DIV_ROUND_CLOSEST(*nanosec, base);
 513                 break;
 514         case CMDF_ROUND_DOWN:
 515                 divider = (*nanosec) / base;
 516                 break;
 517         case CMDF_ROUND_UP:
 518                 divider = DIV_ROUND_UP(*nanosec, base);
 519                 break;
 520         }
 521
 522         *nanosec = base * divider;
 523         return divider;
 524 }
 525
 526 static int ni_pcidio_cmdtest(struct comedi_device *dev,
 527                              struct comedi_subdevice *s, struct comedi_cmd *cmd)
 528 {
 529         int err = 0;
 530         unsigned int arg;
 531
 532         /* Step 1 : check if triggers are trivially valid */
 533
 534         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
 535         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
 536                                         TRIG_TIMER | TRIG_EXT);
 537         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
 538         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 539         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
 540
 541         if (err)
 542                 return 1;
 543
 544         /* Step 2a : make sure trigger sources are unique */
 545
 546         err |= comedi_check_trigger_is_unique(cmd->start_src);
 547         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
 548         err |= comedi_check_trigger_is_unique(cmd->stop_src);
 549
 550         /* Step 2b : and mutually compatible */
 551
 552         if (err)
 553                 return 2;
 554
 555         /* Step 3: check if arguments are trivially valid */
 556
 557         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
 558
 559 #define MAX_SPEED       (TIMER_BASE)    /* in nanoseconds */
 560
 561         if (cmd->scan_begin_src == TRIG_TIMER) {
 562                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
 563                                                     MAX_SPEED);
 564                 /* no minimum speed */
 565         } else {
 566                 /* TRIG_EXT */
 567                 /* should be level/edge, hi/lo specification here */
 568                 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
 569                         cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
 570                         err |= -EINVAL;
 571                 }
 572         }
 573
 574         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
 575         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
 576                                            cmd->chanlist_len);
 577
 578         if (cmd->stop_src == TRIG_COUNT)
 579                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
 580         else    /* TRIG_NONE */
 581                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
 582
 583         if (err)
 584                 return 3;
 585
 586         /* step 4: fix up any arguments */
 587
 588         if (cmd->scan_begin_src == TRIG_TIMER) {
 589                 arg = cmd->scan_begin_arg;
 590                 ni_pcidio_ns_to_timer(&arg, cmd->flags);
 591                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
 592         }
 593
 594         if (err)
 595                 return 4;
 596
 597         return 0;
 598 }
 599
 600 static int ni_pcidio_inttrig(struct comedi_device *dev,
 601                              struct comedi_subdevice *s,
 602                              unsigned int trig_num)
 603 {
 604         struct nidio96_private *devpriv = dev->private;
 605         struct comedi_cmd *cmd = &s->async->cmd;
 606
 607         if (trig_num != cmd->start_arg)
 608                 return -EINVAL;
 609
 610         writeb(devpriv->OP_MODEBits, dev->mmio + OP_MODE);
 611         s->async->inttrig = NULL;
 612
 613         return 1;
 614 }
 615
 616 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 617 {
 618         struct nidio96_private *devpriv = dev->private;
 619         struct comedi_cmd *cmd = &s->async->cmd;
 620
 621         /* XXX configure ports for input */
 622         writel(0x0000, dev->mmio + PORT_PIN_DIRECTIONS(0));
 623
 624         if (1) {
 625                 /* enable fifos A B C D */
 626                 writeb(0x0f, dev->mmio + DATA_PATH);
 627
 628                 /* set transfer width a 32 bits */
 629                 writeb(TRANSFER_WIDTH(0) | TRANSFER_LENGTH(0),
 630                        dev->mmio + TRANSFER_SIZE_CONTROL);
 631         } else {
 632                 writeb(0x03, dev->mmio + DATA_PATH);
 633                 writeb(TRANSFER_WIDTH(3) | TRANSFER_LENGTH(0),
 634                        dev->mmio + TRANSFER_SIZE_CONTROL);
 635         }
 636
 637         /* protocol configuration */
 638         if (cmd->scan_begin_src == TRIG_TIMER) {
 639                 /* page 4-5, "input with internal REQs" */
 640                 writeb(0, dev->mmio + OP_MODE);
 641                 writeb(0x00, dev->mmio + CLOCK_REG);
 642                 writeb(1, dev->mmio + SEQUENCE);
 643                 writeb(0x04, dev->mmio + REQ_REG);
 644                 writeb(4, dev->mmio + BLOCK_MODE);
 645                 writeb(3, dev->mmio + LINE_POLARITIES);
 646                 writeb(0xc0, dev->mmio + ACK_SER);
 647                 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
 648                                              CMDF_ROUND_NEAREST),
 649                        dev->mmio + START_DELAY);
 650                 writeb(1, dev->mmio + REQ_DELAY);
 651                 writeb(1, dev->mmio + REQ_NOT_DELAY);
 652                 writeb(1, dev->mmio + ACK_DELAY);
 653                 writeb(0x0b, dev->mmio + ACK_NOT_DELAY);
 654                 writeb(0x01, dev->mmio + DATA_1_DELAY);
 655                 /*
 656                  * manual, page 4-5:
 657                  * CLOCK_SPEED comment is incorrectly listed on DAQ_OPTIONS
 658                  */
 659                 writew(0, dev->mmio + CLOCK_SPEED);
 660                 writeb(0, dev->mmio + DAQ_OPTIONS);
 661         } else {
 662                 /* TRIG_EXT */
 663                 /* page 4-5, "input with external REQs" */
 664                 writeb(0, dev->mmio + OP_MODE);
 665                 writeb(0x00, dev->mmio + CLOCK_REG);
 666                 writeb(0, dev->mmio + SEQUENCE);
 667                 writeb(0x00, dev->mmio + REQ_REG);
 668                 writeb(4, dev->mmio + BLOCK_MODE);
 669                 if (!(cmd->scan_begin_arg & CR_INVERT)) /* Leading Edge */
 670                         writeb(0, dev->mmio + LINE_POLARITIES);
 671                 else                                    /* Trailing Edge */
 672                         writeb(2, dev->mmio + LINE_POLARITIES);
 673                 writeb(0x00, dev->mmio + ACK_SER);
 674                 writel(1, dev->mmio + START_DELAY);
 675                 writeb(1, dev->mmio + REQ_DELAY);
 676                 writeb(1, dev->mmio + REQ_NOT_DELAY);
 677                 writeb(1, dev->mmio + ACK_DELAY);
 678                 writeb(0x0C, dev->mmio + ACK_NOT_DELAY);
 679                 writeb(0x10, dev->mmio + DATA_1_DELAY);
 680                 writew(0, dev->mmio + CLOCK_SPEED);
 681                 writeb(0x60, dev->mmio + DAQ_OPTIONS);
 682         }
 683
 684         if (cmd->stop_src == TRIG_COUNT) {
 685                 writel(cmd->stop_arg,
 686                        dev->mmio + TRANSFER_COUNT);
 687         } else {
 688                 /* XXX */
 689         }
 690
 691 #ifdef USE_DMA
 692         writeb(CLEAR_PRIMARY_TC | CLEAR_SECONDARY_TC,
 693                dev->mmio + GROUP_1_FIRST_CLEAR);
 694
 695         {
 696                 int retval = setup_mite_dma(dev, s);
 697
 698                 if (retval)
 699                         return retval;
 700         }
 701 #else
 702         writeb(0x00, dev->mmio + DMA_LINE_CONTROL_GROUP1);
 703 #endif
 704         writeb(0x00, dev->mmio + DMA_LINE_CONTROL_GROUP2);
 705
 706         /* clear and enable interrupts */
 707         writeb(0xff, dev->mmio + GROUP_1_FIRST_CLEAR);
 708         /* writeb(CLEAR_EXPIRED, dev->mmio+GROUP_1_SECOND_CLEAR); */
 709
 710         writeb(INT_EN, dev->mmio + INTERRUPT_CONTROL);
 711         writeb(0x03, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
 712
 713         if (cmd->stop_src == TRIG_NONE) {
 714                 devpriv->OP_MODEBits = DATA_LATCHING(0) | RUN_MODE(7);
 715         } else {                /* TRIG_TIMER */
 716                 devpriv->OP_MODEBits = NUMBERED | RUN_MODE(7);
 717         }
 718         if (cmd->start_src == TRIG_NOW) {
 719                 /* start */
 720                 writeb(devpriv->OP_MODEBits, dev->mmio + OP_MODE);
 721                 s->async->inttrig = NULL;
 722         } else {
 723                 /* TRIG_INT */
 724                 s->async->inttrig = ni_pcidio_inttrig;
 725         }
 726
 727         return 0;
 728 }
 729
 730 static int ni_pcidio_cancel(struct comedi_device *dev,
 731                             struct comedi_subdevice *s)
 732 {
 733         writeb(0x00, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
 734         ni_pcidio_release_di_mite_channel(dev);
 735
 736         return 0;
 737 }
 738
 739 static int ni_pcidio_change(struct comedi_device *dev,
 740                             struct comedi_subdevice *s)
 741 {
 742         struct nidio96_private *devpriv = dev->private;
 743         int ret;
 744
 745         ret = mite_buf_change(devpriv->di_mite_ring, s);
 746         if (ret < 0)
 747                 return ret;
 748
 749         memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
 750
 751         return 0;
 752 }
 753
 754 static int pci_6534_load_fpga(struct comedi_device *dev,
 755                               const u8 *data, size_t data_len,
 756                               unsigned long context)
 757 {
 758         static const int timeout = 1000;
 759         int fpga_index = context;
 760         int i;
 761         size_t j;
 762
 763         writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
 764         writew(0xc0 | fpga_index, dev->mmio + Firmware_Control_Register);
 765         for (i = 0;
 766              (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0 &&
 767              i < timeout; ++i) {
 768                 udelay(1);
 769         }
 770         if (i == timeout) {
 771                 dev_warn(dev->class_dev,
 772                          "ni_pcidio: failed to load fpga %i, waiting for status 0x2\n",
 773                          fpga_index);
 774                 return -EIO;
 775         }
 776         writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
 777         for (i = 0;
 778              readw(dev->mmio + Firmware_Status_Register) != 0x3 &&
 779              i < timeout; ++i) {
 780                 udelay(1);
 781         }
 782         if (i == timeout) {
 783                 dev_warn(dev->class_dev,
 784                          "ni_pcidio: failed to load fpga %i, waiting for status 0x3\n",
 785                          fpga_index);
 786                 return -EIO;
 787         }
 788         for (j = 0; j + 1 < data_len;) {
 789                 unsigned int value = data[j++];
 790
 791                 value |= data[j++] << 8;
 792                 writew(value, dev->mmio + Firmware_Data_Register);
 793                 for (i = 0;
 794                      (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0
 795                      && i < timeout; ++i) {
 796                         udelay(1);
 797                 }
 798                 if (i == timeout) {
 799                         dev_warn(dev->class_dev,
 800                                  "ni_pcidio: failed to load word into fpga %i\n",
 801                                  fpga_index);
 802                         return -EIO;
 803                 }
 804                 if (need_resched())
 805                         schedule();
 806         }
 807         writew(0x0, dev->mmio + Firmware_Control_Register);
 808         return 0;
 809 }
 810
 811 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
 812 {
 813         return pci_6534_load_fpga(dev, NULL, 0, fpga_index);
 814 }
 815
 816 static int pci_6534_reset_fpgas(struct comedi_device *dev)
 817 {
 818         int ret;
 819         int i;
 820
 821         writew(0x0, dev->mmio + Firmware_Control_Register);
 822         for (i = 0; i < 3; ++i) {
 823                 ret = pci_6534_reset_fpga(dev, i);
 824                 if (ret < 0)
 825                         break;
 826         }
 827         writew(0x0, dev->mmio + Firmware_Mask_Register);
 828         return ret;
 829 }
 830
 831 static void pci_6534_init_main_fpga(struct comedi_device *dev)
 832 {
 833         writel(0, dev->mmio + FPGA_Control1_Register);
 834         writel(0, dev->mmio + FPGA_Control2_Register);
 835         writel(0, dev->mmio + FPGA_SCALS_Counter_Register);
 836         writel(0, dev->mmio + FPGA_SCAMS_Counter_Register);
 837         writel(0, dev->mmio + FPGA_SCBLS_Counter_Register);
 838         writel(0, dev->mmio + FPGA_SCBMS_Counter_Register);
 839 }
 840
 841 static int pci_6534_upload_firmware(struct comedi_device *dev)
 842 {
 843         struct nidio96_private *devpriv = dev->private;
 844         static const char *const fw_file[3] = {
 845                 FW_PCI_6534_SCARAB_DI,  /* loaded into scarab A for DI */
 846                 FW_PCI_6534_SCARAB_DO,  /* loaded into scarab B for DO */
 847                 FW_PCI_6534_MAIN,       /* loaded into main FPGA */
 848         };
 849         int ret;
 850         int n;
 851
 852         ret = pci_6534_reset_fpgas(dev);
 853         if (ret < 0)
 854                 return ret;
 855         /* load main FPGA first, then the two scarabs */
 856         for (n = 2; n >= 0; n--) {
 857                 ret = comedi_load_firmware(dev, &devpriv->mite->pcidev->dev,
 858                                            fw_file[n],
 859                                            pci_6534_load_fpga, n);
 860                 if (ret == 0 && n == 2)
 861                         pci_6534_init_main_fpga(dev);
 862                 if (ret < 0)
 863                         break;
 864         }
 865         return ret;
 866 }
 867
 868 static void nidio_reset_board(struct comedi_device *dev)
 869 {
 870         writel(0, dev->mmio + PORT_IO(0));
 871         writel(0, dev->mmio + PORT_PIN_DIRECTIONS(0));
 872         writel(0, dev->mmio + PORT_PIN_MASK(0));
 873
 874         /* disable interrupts on board */
 875         writeb(0, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
 876 }
 877
 878 static int nidio_auto_attach(struct comedi_device *dev,
 879                              unsigned long context)
 880 {
 881         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 882         const struct nidio_board *board = NULL;
 883         struct nidio96_private *devpriv;
 884         struct comedi_subdevice *s;
 885         int ret;
 886         unsigned int irq;
 887
 888         if (context < ARRAY_SIZE(nidio_boards))
 889                 board = &nidio_boards[context];
 890         if (!board)
 891                 return -ENODEV;
 892         dev->board_ptr = board;
 893         dev->board_name = board->name;
 894
 895         ret = comedi_pci_enable(dev);
 896         if (ret)
 897                 return ret;
 898
 899         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
 900         if (!devpriv)
 901                 return -ENOMEM;
 902
 903         spin_lock_init(&devpriv->mite_channel_lock);
 904
 905         devpriv->mite = mite_attach(dev, false);        /* use win0 */
 906         if (!devpriv->mite)
 907                 return -ENOMEM;
 908
 909         devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
 910         if (!devpriv->di_mite_ring)
 911                 return -ENOMEM;
 912
 913         if (board->uses_firmware) {
 914                 ret = pci_6534_upload_firmware(dev);
 915                 if (ret < 0)
 916                         return ret;
 917         }
 918
 919         nidio_reset_board(dev);
 920
 921         ret = comedi_alloc_subdevices(dev, 1);
 922         if (ret)
 923                 return ret;
 924
 925         dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
 926                  readb(dev->mmio + CHIP_VERSION));
 927
 928         s = &dev->subdevices[0];
 929
 930         dev->read_subdev = s;
 931         s->type = COMEDI_SUBD_DIO;
 932         s->subdev_flags =
 933                 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
 934                 SDF_CMD_READ;
 935         s->n_chan = 32;
 936         s->range_table = &range_digital;
 937         s->maxdata = 1;
 938         s->insn_config = &ni_pcidio_insn_config;
 939         s->insn_bits = &ni_pcidio_insn_bits;
 940         s->do_cmd = &ni_pcidio_cmd;
 941         s->do_cmdtest = &ni_pcidio_cmdtest;
 942         s->cancel = &ni_pcidio_cancel;
 943         s->len_chanlist = 32;   /* XXX */
 944         s->buf_change = &ni_pcidio_change;
 945         s->async_dma_dir = DMA_BIDIRECTIONAL;
 946         s->poll = &ni_pcidio_poll;
 947
 948         irq = pcidev->irq;
 949         if (irq) {
 950                 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
 951                                   dev->board_name, dev);
 952                 if (ret == 0)
 953                         dev->irq = irq;
 954         }
 955
 956         return 0;
 957 }
 958
 959 static void nidio_detach(struct comedi_device *dev)
 960 {
 961         struct nidio96_private *devpriv = dev->private;
 962
 963         if (dev->irq)
 964                 free_irq(dev->irq, dev);
 965         if (devpriv) {
 966                 if (devpriv->di_mite_ring) {
 967                         mite_free_ring(devpriv->di_mite_ring);
 968                         devpriv->di_mite_ring = NULL;
 969                 }
 970                 mite_detach(devpriv->mite);
 971         }
 972         if (dev->mmio)
 973                 iounmap(dev->mmio);
 974         comedi_pci_disable(dev);
 975 }
 976
 977 static struct comedi_driver ni_pcidio_driver = {
 978         .driver_name    = "ni_pcidio",
 979         .module         = THIS_MODULE,
 980         .auto_attach    = nidio_auto_attach,
 981         .detach         = nidio_detach,
 982 };
 983
 984 static int ni_pcidio_pci_probe(struct pci_dev *dev,
 985                                const struct pci_device_id *id)
 986 {
 987         return comedi_pci_auto_config(dev, &ni_pcidio_driver, id->driver_data);
 988 }
 989
 990 static const struct pci_device_id ni_pcidio_pci_table[] = {
 991         { PCI_VDEVICE(NI, 0x1150), BOARD_PCIDIO_32HS },
 992         { PCI_VDEVICE(NI, 0x12b0), BOARD_PCI6534 },
 993         { PCI_VDEVICE(NI, 0x1320), BOARD_PXI6533 },
 994         { 0 }
 995 };
 996 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
 997
 998 static struct pci_driver ni_pcidio_pci_driver = {
 999         .name           = "ni_pcidio",
1000         .id_table       = ni_pcidio_pci_table,
1001         .probe          = ni_pcidio_pci_probe,
1002         .remove         = comedi_pci_auto_unconfig,
1003 };
1004 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
1005
1006 MODULE_AUTHOR("Comedi http://www.comedi.org");
1007 MODULE_DESCRIPTION("Comedi low-level driver");
1008 MODULE_LICENSE("GPL");