1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
9 * Tel: +19(0)7223/9493-0
10 * Fax: +49(0)7223/9493-92
11 * http://www.addi-data.com
16 * Driver: addi_apci_1564
17 * Description: ADDI-DATA APCI-1564 Digital I/O board
18 * Devices: [ADDI-DATA] APCI-1564 (addi_apci_1564)
19 * Author: H Hartley Sweeten <hsweeten@visionengravers.com>
20 * Updated: Thu, 02 Jun 2016 13:12:46 -0700
23 * Configuration Options: not applicable, uses comedi PCI auto config
25 * This board has the following features:
26 * - 32 optically isolated digital inputs (24V), 16 of which can
27 * generate change-of-state (COS) interrupts (channels 4 to 19)
28 * - 32 optically isolated digital outputs (10V to 36V)
29 * - 1 8-bit watchdog for resetting the outputs
32 * - 2 diagnostic inputs
34 * The COS, timer, and counter subdevices all use the dev->read_subdev to
35 * return the interrupt status. The sample data is updated and returned when
36 * any of these subdevices generate an interrupt. The sample data format is:
39 * ----- ------------------------------------------
42 * 29 counter 2 interrupt
43 * 28 counter 1 interrupt
44 * 27 counter 0 interrupt
46 * 19:4 COS digital input state (channels 19 to 4)
49 * The COS interrupts must be configured using an INSN_CONFIG_DIGITAL_TRIG
50 * instruction before they can be enabled by an async command. The COS
51 * interrupts will stay active until canceled.
53 * The timer subdevice does not use an async command. All control is handled
54 * by the (*insn_config).
56 * FIXME: The format of the ADDI_TCW_TIMEBASE_REG is not descibed in the
57 * datasheet I have. The INSN_CONFIG_SET_CLOCK_SRC currently just writes
58 * the raw data[1] to this register along with the raw data[2] value to the
59 * ADDI_TCW_RELOAD_REG. If anyone tests this and can determine the actual
60 * timebase/reload operation please let me know.
62 * The counter subdevice also does not use an async command. All control is
63 * handled by the (*insn_config).
65 * FIXME: The operation of the counters is not really described in the
66 * datasheet I have. The (*insn_config) needs more work.
69 #include <linux/module.h>
70 #include <linux/interrupt.h>
72 #include "../comedi_pci.h"
74 #include "addi_watchdog.h"
79 * PLD Revision 1.0 I/O Mapping
81 * 0x04 - 0x18 Timer 12-Bit
83 * PLD Revision 2.x I/O Mapping
85 * 0x04 - 0x14 Digital Input
86 * 0x18 - 0x25 Digital Output
87 * 0x28 - 0x44 Watchdog 8-Bit
88 * 0x48 - 0x64 Timer 12-Bit
90 #define APCI1564_EEPROM_REG 0x00
91 #define APCI1564_EEPROM_VCC_STATUS BIT(8)
92 #define APCI1564_EEPROM_TO_REV(x) (((x) >> 4) & 0xf)
93 #define APCI1564_EEPROM_DI BIT(3)
94 #define APCI1564_EEPROM_DO BIT(2)
95 #define APCI1564_EEPROM_CS BIT(1)
96 #define APCI1564_EEPROM_CLK BIT(0)
97 #define APCI1564_REV1_TIMER_IOBASE 0x04
98 #define APCI1564_REV2_MAIN_IOBASE 0x04
99 #define APCI1564_REV2_TIMER_IOBASE 0x48
104 * PLD Revision 1.0 I/O Mapping
105 * 0x00 - 0x10 Digital Input
106 * 0x14 - 0x20 Digital Output
107 * 0x24 - 0x3c Watchdog 8-Bit
109 * PLD Revision 2.x I/O Mapping
114 #define APCI1564_REV1_MAIN_IOBASE 0x00
117 * dev->iobase Register Map
118 * PLD Revision 1.0 - PCI BAR 1 + 0x00
119 * PLD Revision 2.x - PCI BAR 0 + 0x04
121 #define APCI1564_DI_REG 0x00
122 #define APCI1564_DI_INT_MODE1_REG 0x04
123 #define APCI1564_DI_INT_MODE2_REG 0x08
124 #define APCI1564_DI_INT_MODE_MASK 0x000ffff0 /* chans [19:4] */
125 #define APCI1564_DI_INT_STATUS_REG 0x0c
126 #define APCI1564_DI_IRQ_REG 0x10
127 #define APCI1564_DI_IRQ_ENA BIT(2)
128 #define APCI1564_DI_IRQ_MODE BIT(1) /* 1=AND, 0=OR */
129 #define APCI1564_DO_REG 0x14
130 #define APCI1564_DO_INT_CTRL_REG 0x18
131 #define APCI1564_DO_INT_CTRL_CC_INT_ENA BIT(1)
132 #define APCI1564_DO_INT_CTRL_VCC_INT_ENA BIT(0)
133 #define APCI1564_DO_INT_STATUS_REG 0x1c
134 #define APCI1564_DO_INT_STATUS_CC BIT(1)
135 #define APCI1564_DO_INT_STATUS_VCC BIT(0)
136 #define APCI1564_DO_IRQ_REG 0x20
137 #define APCI1564_DO_IRQ_INTR BIT(0)
138 #define APCI1564_WDOG_IOBASE 0x24
141 * devpriv->timer Register Map (see addi_tcw.h for register/bit defines)
142 * PLD Revision 1.0 - PCI BAR 0 + 0x04
143 * PLD Revision 2.x - PCI BAR 0 + 0x48
147 * devpriv->counters Register Map (see addi_tcw.h for register/bit defines)
148 * PLD Revision 2.x - PCI BAR 1 + 0x00
150 #define APCI1564_COUNTER(x) ((x) * 0x20)
153 * The dev->read_subdev is used to return the interrupt events along with
154 * the state of the interrupt capable inputs.
156 #define APCI1564_EVENT_COS BIT(31)
157 #define APCI1564_EVENT_TIMER BIT(30)
158 #define APCI1564_EVENT_COUNTER(x) BIT(27 + (x)) /* counter 0-2 */
159 #define APCI1564_EVENT_MASK 0xfff0000f /* all but [19:4] */
161 struct apci1564_private {
162 unsigned long eeprom; /* base address of EEPROM register */
163 unsigned long timer; /* base address of 12-bit timer */
164 unsigned long counters; /* base address of 32-bit counters */
165 unsigned int mode1; /* rising-edge/high level channels */
166 unsigned int mode2; /* falling-edge/low level channels */
167 unsigned int ctrl; /* interrupt mode OR (edge) . AND (level) */
170 static int apci1564_reset(struct comedi_device *dev)
172 struct apci1564_private *devpriv = dev->private;
174 /* Disable the input interrupts and reset status register */
175 outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
176 inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
177 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
178 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
180 /* Reset the output channels and disable interrupts */
181 outl(0x0, dev->iobase + APCI1564_DO_REG);
182 outl(0x0, dev->iobase + APCI1564_DO_INT_CTRL_REG);
184 /* Reset the watchdog registers */
185 addi_watchdog_reset(dev->iobase + APCI1564_WDOG_IOBASE);
187 /* Reset the timer registers */
188 outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
189 outl(0x0, devpriv->timer + ADDI_TCW_RELOAD_REG);
191 if (devpriv->counters) {
192 unsigned long iobase = devpriv->counters + ADDI_TCW_CTRL_REG;
194 /* Reset the counter registers */
195 outl(0x0, iobase + APCI1564_COUNTER(0));
196 outl(0x0, iobase + APCI1564_COUNTER(1));
197 outl(0x0, iobase + APCI1564_COUNTER(2));
203 static irqreturn_t apci1564_interrupt(int irq, void *d)
205 struct comedi_device *dev = d;
206 struct apci1564_private *devpriv = dev->private;
207 struct comedi_subdevice *s = dev->read_subdev;
212 s->state &= ~APCI1564_EVENT_MASK;
214 status = inl(dev->iobase + APCI1564_DI_IRQ_REG);
215 if (status & APCI1564_DI_IRQ_ENA) {
216 /* get the COS interrupt state and set the event flag */
217 s->state = inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
218 s->state &= APCI1564_DI_INT_MODE_MASK;
219 s->state |= APCI1564_EVENT_COS;
221 /* clear the interrupt */
222 outl(status & ~APCI1564_DI_IRQ_ENA,
223 dev->iobase + APCI1564_DI_IRQ_REG);
224 outl(status, dev->iobase + APCI1564_DI_IRQ_REG);
227 status = inl(devpriv->timer + ADDI_TCW_IRQ_REG);
228 if (status & ADDI_TCW_IRQ) {
229 s->state |= APCI1564_EVENT_TIMER;
231 /* clear the interrupt */
232 ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG);
233 outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
234 outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG);
237 if (devpriv->counters) {
238 for (chan = 0; chan < 3; chan++) {
239 unsigned long iobase;
241 iobase = devpriv->counters + APCI1564_COUNTER(chan);
243 status = inl(iobase + ADDI_TCW_IRQ_REG);
244 if (status & ADDI_TCW_IRQ) {
245 s->state |= APCI1564_EVENT_COUNTER(chan);
247 /* clear the interrupt */
248 ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
249 outl(0x0, iobase + ADDI_TCW_CTRL_REG);
250 outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
255 if (s->state & APCI1564_EVENT_MASK) {
256 comedi_buf_write_samples(s, &s->state, 1);
257 comedi_handle_events(dev, s);
263 static int apci1564_di_insn_bits(struct comedi_device *dev,
264 struct comedi_subdevice *s,
265 struct comedi_insn *insn,
268 data[1] = inl(dev->iobase + APCI1564_DI_REG);
273 static int apci1564_do_insn_bits(struct comedi_device *dev,
274 struct comedi_subdevice *s,
275 struct comedi_insn *insn,
278 s->state = inl(dev->iobase + APCI1564_DO_REG);
280 if (comedi_dio_update_state(s, data))
281 outl(s->state, dev->iobase + APCI1564_DO_REG);
288 static int apci1564_diag_insn_bits(struct comedi_device *dev,
289 struct comedi_subdevice *s,
290 struct comedi_insn *insn,
293 data[1] = inl(dev->iobase + APCI1564_DO_INT_STATUS_REG) & 3;
299 * Change-Of-State (COS) interrupt configuration
301 * Channels 4 to 19 are interruptible. These channels can be configured
302 * to generate interrupts based on AND/OR logic for the desired channels.
305 * - reacts to rising or falling edges
306 * - interrupt is generated when any enabled channel
307 * meet the desired interrupt condition
310 * - reacts to changes in level of the selected inputs
311 * - interrupt is generated when all enabled channels
312 * meet the desired interrupt condition
313 * - after an interrupt, a change in level must occur on
314 * the selected inputs to release the IRQ logic
316 * The COS interrupt must be configured before it can be enabled.
318 * data[0] : INSN_CONFIG_DIGITAL_TRIG
319 * data[1] : trigger number (= 0)
320 * data[2] : configuration operation:
321 * COMEDI_DIGITAL_TRIG_DISABLE = no interrupts
322 * COMEDI_DIGITAL_TRIG_ENABLE_EDGES = OR (edge) interrupts
323 * COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = AND (level) interrupts
324 * data[3] : left-shift for data[4] and data[5]
325 * data[4] : rising-edge/high level channels
326 * data[5] : falling-edge/low level channels
328 static int apci1564_cos_insn_config(struct comedi_device *dev,
329 struct comedi_subdevice *s,
330 struct comedi_insn *insn,
333 struct apci1564_private *devpriv = dev->private;
334 unsigned int shift, oldmask;
337 case INSN_CONFIG_DIGITAL_TRIG:
341 oldmask = (1U << shift) - 1;
343 case COMEDI_DIGITAL_TRIG_DISABLE:
347 outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
348 inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
349 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
350 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
352 case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
353 if (devpriv->ctrl != APCI1564_DI_IRQ_ENA) {
354 /* switching to 'OR' mode */
355 devpriv->ctrl = APCI1564_DI_IRQ_ENA;
356 /* wipe old channels */
360 /* preserve unspecified channels */
361 devpriv->mode1 &= oldmask;
362 devpriv->mode2 &= oldmask;
364 /* configure specified channels */
365 devpriv->mode1 |= data[4] << shift;
366 devpriv->mode2 |= data[5] << shift;
368 case COMEDI_DIGITAL_TRIG_ENABLE_LEVELS:
369 if (devpriv->ctrl != (APCI1564_DI_IRQ_ENA |
370 APCI1564_DI_IRQ_MODE)) {
371 /* switching to 'AND' mode */
372 devpriv->ctrl = APCI1564_DI_IRQ_ENA |
373 APCI1564_DI_IRQ_MODE;
374 /* wipe old channels */
378 /* preserve unspecified channels */
379 devpriv->mode1 &= oldmask;
380 devpriv->mode2 &= oldmask;
382 /* configure specified channels */
383 devpriv->mode1 |= data[4] << shift;
384 devpriv->mode2 |= data[5] << shift;
390 /* ensure the mode bits are in-range for channels [19:4] */
391 devpriv->mode1 &= APCI1564_DI_INT_MODE_MASK;
392 devpriv->mode2 &= APCI1564_DI_INT_MODE_MASK;
400 static int apci1564_cos_insn_bits(struct comedi_device *dev,
401 struct comedi_subdevice *s,
402 struct comedi_insn *insn,
410 static int apci1564_cos_cmdtest(struct comedi_device *dev,
411 struct comedi_subdevice *s,
412 struct comedi_cmd *cmd)
416 /* Step 1 : check if triggers are trivially valid */
418 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
419 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
420 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
421 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
422 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
427 /* Step 2a : make sure trigger sources are unique */
428 /* Step 2b : and mutually compatible */
430 /* Step 3: check if arguments are trivially valid */
432 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
433 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
434 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
435 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
437 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
442 /* Step 4: fix up any arguments */
444 /* Step 5: check channel list if it exists */
450 * Change-Of-State (COS) 'do_cmd' operation
452 * Enable the COS interrupt as configured by apci1564_cos_insn_config().
454 static int apci1564_cos_cmd(struct comedi_device *dev,
455 struct comedi_subdevice *s)
457 struct apci1564_private *devpriv = dev->private;
459 if (!devpriv->ctrl && !(devpriv->mode1 || devpriv->mode2)) {
460 dev_warn(dev->class_dev,
461 "Interrupts disabled due to mode configuration!\n");
465 outl(devpriv->mode1, dev->iobase + APCI1564_DI_INT_MODE1_REG);
466 outl(devpriv->mode2, dev->iobase + APCI1564_DI_INT_MODE2_REG);
467 outl(devpriv->ctrl, dev->iobase + APCI1564_DI_IRQ_REG);
472 static int apci1564_cos_cancel(struct comedi_device *dev,
473 struct comedi_subdevice *s)
475 outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
476 inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
477 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
478 outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
483 static int apci1564_timer_insn_config(struct comedi_device *dev,
484 struct comedi_subdevice *s,
485 struct comedi_insn *insn,
488 struct apci1564_private *devpriv = dev->private;
492 case INSN_CONFIG_ARM:
493 if (data[1] > s->maxdata)
495 outl(data[1], devpriv->timer + ADDI_TCW_RELOAD_REG);
496 outl(ADDI_TCW_CTRL_IRQ_ENA | ADDI_TCW_CTRL_TIMER_ENA,
497 devpriv->timer + ADDI_TCW_CTRL_REG);
499 case INSN_CONFIG_DISARM:
500 outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
502 case INSN_CONFIG_GET_COUNTER_STATUS:
504 val = inl(devpriv->timer + ADDI_TCW_CTRL_REG);
505 if (val & ADDI_TCW_CTRL_IRQ_ENA)
506 data[1] |= COMEDI_COUNTER_ARMED;
507 if (val & ADDI_TCW_CTRL_TIMER_ENA)
508 data[1] |= COMEDI_COUNTER_COUNTING;
509 val = inl(devpriv->timer + ADDI_TCW_STATUS_REG);
510 if (val & ADDI_TCW_STATUS_OVERFLOW)
511 data[1] |= COMEDI_COUNTER_TERMINAL_COUNT;
512 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING |
513 COMEDI_COUNTER_TERMINAL_COUNT;
515 case INSN_CONFIG_SET_CLOCK_SRC:
516 if (data[2] > s->maxdata)
518 outl(data[1], devpriv->timer + ADDI_TCW_TIMEBASE_REG);
519 outl(data[2], devpriv->timer + ADDI_TCW_RELOAD_REG);
521 case INSN_CONFIG_GET_CLOCK_SRC:
522 data[1] = inl(devpriv->timer + ADDI_TCW_TIMEBASE_REG);
523 data[2] = inl(devpriv->timer + ADDI_TCW_RELOAD_REG);
532 static int apci1564_timer_insn_write(struct comedi_device *dev,
533 struct comedi_subdevice *s,
534 struct comedi_insn *insn,
537 struct apci1564_private *devpriv = dev->private;
539 /* just write the last last to the reload register */
541 unsigned int val = data[insn->n - 1];
543 outl(val, devpriv->timer + ADDI_TCW_RELOAD_REG);
549 static int apci1564_timer_insn_read(struct comedi_device *dev,
550 struct comedi_subdevice *s,
551 struct comedi_insn *insn,
554 struct apci1564_private *devpriv = dev->private;
557 /* return the actual value of the timer */
558 for (i = 0; i < insn->n; i++)
559 data[i] = inl(devpriv->timer + ADDI_TCW_VAL_REG);
564 static int apci1564_counter_insn_config(struct comedi_device *dev,
565 struct comedi_subdevice *s,
566 struct comedi_insn *insn,
569 struct apci1564_private *devpriv = dev->private;
570 unsigned int chan = CR_CHAN(insn->chanspec);
571 unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
575 case INSN_CONFIG_ARM:
576 val = inl(iobase + ADDI_TCW_CTRL_REG);
577 val |= ADDI_TCW_CTRL_IRQ_ENA | ADDI_TCW_CTRL_CNTR_ENA;
578 outl(data[1], iobase + ADDI_TCW_RELOAD_REG);
579 outl(val, iobase + ADDI_TCW_CTRL_REG);
581 case INSN_CONFIG_DISARM:
582 val = inl(iobase + ADDI_TCW_CTRL_REG);
583 val &= ~(ADDI_TCW_CTRL_IRQ_ENA | ADDI_TCW_CTRL_CNTR_ENA);
584 outl(val, iobase + ADDI_TCW_CTRL_REG);
586 case INSN_CONFIG_SET_COUNTER_MODE:
588 * FIXME: The counter operation is not described in the
589 * datasheet. For now just write the raw data[1] value to
590 * the control register.
592 outl(data[1], iobase + ADDI_TCW_CTRL_REG);
594 case INSN_CONFIG_GET_COUNTER_STATUS:
596 val = inl(iobase + ADDI_TCW_CTRL_REG);
597 if (val & ADDI_TCW_CTRL_IRQ_ENA)
598 data[1] |= COMEDI_COUNTER_ARMED;
599 if (val & ADDI_TCW_CTRL_CNTR_ENA)
600 data[1] |= COMEDI_COUNTER_COUNTING;
601 val = inl(iobase + ADDI_TCW_STATUS_REG);
602 if (val & ADDI_TCW_STATUS_OVERFLOW)
603 data[1] |= COMEDI_COUNTER_TERMINAL_COUNT;
604 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING |
605 COMEDI_COUNTER_TERMINAL_COUNT;
614 static int apci1564_counter_insn_write(struct comedi_device *dev,
615 struct comedi_subdevice *s,
616 struct comedi_insn *insn,
619 struct apci1564_private *devpriv = dev->private;
620 unsigned int chan = CR_CHAN(insn->chanspec);
621 unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
623 /* just write the last last to the reload register */
625 unsigned int val = data[insn->n - 1];
627 outl(val, iobase + ADDI_TCW_RELOAD_REG);
633 static int apci1564_counter_insn_read(struct comedi_device *dev,
634 struct comedi_subdevice *s,
635 struct comedi_insn *insn,
638 struct apci1564_private *devpriv = dev->private;
639 unsigned int chan = CR_CHAN(insn->chanspec);
640 unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
643 /* return the actual value of the counter */
644 for (i = 0; i < insn->n; i++)
645 data[i] = inl(iobase + ADDI_TCW_VAL_REG);
650 static int apci1564_auto_attach(struct comedi_device *dev,
651 unsigned long context_unused)
653 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
654 struct apci1564_private *devpriv;
655 struct comedi_subdevice *s;
659 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
663 ret = comedi_pci_enable(dev);
667 /* read the EEPROM register and check the I/O map revision */
668 devpriv->eeprom = pci_resource_start(pcidev, 0);
669 val = inl(devpriv->eeprom + APCI1564_EEPROM_REG);
670 if (APCI1564_EEPROM_TO_REV(val) == 0) {
671 /* PLD Revision 1.0 I/O Mapping */
672 dev->iobase = pci_resource_start(pcidev, 1) +
673 APCI1564_REV1_MAIN_IOBASE;
674 devpriv->timer = devpriv->eeprom + APCI1564_REV1_TIMER_IOBASE;
676 /* PLD Revision 2.x I/O Mapping */
677 dev->iobase = devpriv->eeprom + APCI1564_REV2_MAIN_IOBASE;
678 devpriv->timer = devpriv->eeprom + APCI1564_REV2_TIMER_IOBASE;
679 devpriv->counters = pci_resource_start(pcidev, 1);
684 if (pcidev->irq > 0) {
685 ret = request_irq(pcidev->irq, apci1564_interrupt, IRQF_SHARED,
686 dev->board_name, dev);
688 dev->irq = pcidev->irq;
691 ret = comedi_alloc_subdevices(dev, 7);
695 /* Allocate and Initialise DI Subdevice Structures */
696 s = &dev->subdevices[0];
697 s->type = COMEDI_SUBD_DI;
698 s->subdev_flags = SDF_READABLE;
701 s->range_table = &range_digital;
702 s->insn_bits = apci1564_di_insn_bits;
704 /* Allocate and Initialise DO Subdevice Structures */
705 s = &dev->subdevices[1];
706 s->type = COMEDI_SUBD_DO;
707 s->subdev_flags = SDF_WRITABLE;
710 s->range_table = &range_digital;
711 s->insn_bits = apci1564_do_insn_bits;
713 /* Change-Of-State (COS) interrupt subdevice */
714 s = &dev->subdevices[2];
716 dev->read_subdev = s;
717 s->type = COMEDI_SUBD_DI;
718 s->subdev_flags = SDF_READABLE | SDF_CMD_READ | SDF_LSAMPL;
721 s->range_table = &range_digital;
723 s->insn_config = apci1564_cos_insn_config;
724 s->insn_bits = apci1564_cos_insn_bits;
725 s->do_cmdtest = apci1564_cos_cmdtest;
726 s->do_cmd = apci1564_cos_cmd;
727 s->cancel = apci1564_cos_cancel;
729 s->type = COMEDI_SUBD_UNUSED;
732 /* Timer subdevice */
733 s = &dev->subdevices[3];
734 s->type = COMEDI_SUBD_TIMER;
735 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
738 s->range_table = &range_digital;
739 s->insn_config = apci1564_timer_insn_config;
740 s->insn_write = apci1564_timer_insn_write;
741 s->insn_read = apci1564_timer_insn_read;
743 /* Counter subdevice */
744 s = &dev->subdevices[4];
745 if (devpriv->counters) {
746 s->type = COMEDI_SUBD_COUNTER;
747 s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
749 s->maxdata = 0xffffffff;
750 s->range_table = &range_digital;
751 s->insn_config = apci1564_counter_insn_config;
752 s->insn_write = apci1564_counter_insn_write;
753 s->insn_read = apci1564_counter_insn_read;
755 s->type = COMEDI_SUBD_UNUSED;
758 /* Initialize the watchdog subdevice */
759 s = &dev->subdevices[5];
760 ret = addi_watchdog_init(s, dev->iobase + APCI1564_WDOG_IOBASE);
764 /* Initialize the diagnostic status subdevice */
765 s = &dev->subdevices[6];
766 s->type = COMEDI_SUBD_DI;
767 s->subdev_flags = SDF_READABLE;
770 s->range_table = &range_digital;
771 s->insn_bits = apci1564_diag_insn_bits;
776 static void apci1564_detach(struct comedi_device *dev)
780 comedi_pci_detach(dev);
783 static struct comedi_driver apci1564_driver = {
784 .driver_name = "addi_apci_1564",
785 .module = THIS_MODULE,
786 .auto_attach = apci1564_auto_attach,
787 .detach = apci1564_detach,
790 static int apci1564_pci_probe(struct pci_dev *dev,
791 const struct pci_device_id *id)
793 return comedi_pci_auto_config(dev, &apci1564_driver, id->driver_data);
796 static const struct pci_device_id apci1564_pci_table[] = {
797 { PCI_DEVICE(PCI_VENDOR_ID_ADDIDATA, 0x1006) },
800 MODULE_DEVICE_TABLE(pci, apci1564_pci_table);
802 static struct pci_driver apci1564_pci_driver = {
803 .name = "addi_apci_1564",
804 .id_table = apci1564_pci_table,
805 .probe = apci1564_pci_probe,
806 .remove = comedi_pci_auto_unconfig,
808 module_comedi_pci_driver(apci1564_driver, apci1564_pci_driver);
810 MODULE_AUTHOR("Comedi http://www.comedi.org");
811 MODULE_DESCRIPTION("ADDI-DATA APCI-1564, 32 channel DI / 32 channel DO boards");
812 MODULE_LICENSE("GPL");