1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2018 Xilinx
5 * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
10 #include <asm/arch/sys_proto.h>
17 #include <ubi_uboot.h>
19 #include <dm/device_compat.h>
20 #include <linux/err.h>
22 #define GQSPI_GFIFO_STRT_MODE_MASK BIT(29)
23 #define GQSPI_CONFIG_MODE_EN_MASK (3 << 30)
24 #define GQSPI_CONFIG_DMA_MODE (2 << 30)
25 #define GQSPI_CONFIG_CPHA_MASK BIT(2)
26 #define GQSPI_CONFIG_CPOL_MASK BIT(1)
29 * QSPI Interrupt Registers bit Masks
31 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
34 #define GQSPI_IXR_TXNFULL_MASK 0x00000004 /* QSPI TX FIFO Overflow */
35 #define GQSPI_IXR_TXFULL_MASK 0x00000008 /* QSPI TX FIFO is full */
36 #define GQSPI_IXR_RXNEMTY_MASK 0x00000010 /* QSPI RX FIFO Not Empty */
37 #define GQSPI_IXR_GFEMTY_MASK 0x00000080 /* QSPI Generic FIFO Empty */
38 #define GQSPI_IXR_ALL_MASK (GQSPI_IXR_TXNFULL_MASK | \
39 GQSPI_IXR_RXNEMTY_MASK)
42 * QSPI Enable Register bit Masks
44 * This register is used to enable or disable the QSPI controller
46 #define GQSPI_ENABLE_ENABLE_MASK 0x00000001 /* QSPI Enable Bit Mask */
48 #define GQSPI_GFIFO_LOW_BUS BIT(14)
49 #define GQSPI_GFIFO_CS_LOWER BIT(12)
50 #define GQSPI_GFIFO_UP_BUS BIT(15)
51 #define GQSPI_GFIFO_CS_UPPER BIT(13)
52 #define GQSPI_SPI_MODE_QSPI (3 << 10)
53 #define GQSPI_SPI_MODE_SPI BIT(10)
54 #define GQSPI_SPI_MODE_DUAL_SPI (2 << 10)
55 #define GQSPI_IMD_DATA_CS_ASSERT 5
56 #define GQSPI_IMD_DATA_CS_DEASSERT 5
57 #define GQSPI_GFIFO_TX BIT(16)
58 #define GQSPI_GFIFO_RX BIT(17)
59 #define GQSPI_GFIFO_STRIPE_MASK BIT(18)
60 #define GQSPI_GFIFO_IMD_MASK 0xFF
61 #define GQSPI_GFIFO_EXP_MASK BIT(9)
62 #define GQSPI_GFIFO_DATA_XFR_MASK BIT(8)
63 #define GQSPI_STRT_GEN_FIFO BIT(28)
64 #define GQSPI_GEN_FIFO_STRT_MOD BIT(29)
65 #define GQSPI_GFIFO_WP_HOLD BIT(19)
66 #define GQSPI_BAUD_DIV_MASK (7 << 3)
67 #define GQSPI_DFLT_BAUD_RATE_DIV BIT(3)
68 #define GQSPI_GFIFO_ALL_INT_MASK 0xFBE
69 #define GQSPI_DMA_DST_I_STS_DONE BIT(1)
70 #define GQSPI_DMA_DST_I_STS_MASK 0xFE
73 #define GQSPI_GFIFO_SELECT BIT(0)
74 #define GQSPI_FIFO_THRESHOLD 1
76 #define SPI_XFER_ON_BOTH 0
77 #define SPI_XFER_ON_LOWER 1
78 #define SPI_XFER_ON_UPPER 2
80 #define GQSPI_DMA_ALIGN 0x4
81 #define GQSPI_MAX_BAUD_RATE_VAL 7
82 #define GQSPI_DFLT_BAUD_RATE_VAL 2
84 #define GQSPI_TIMEOUT 100000000
86 #define GQSPI_BAUD_DIV_SHIFT 2
87 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5
88 #define GQSPI_LPBK_DLY_ADJ_DLY_1 0x2
89 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 3
90 #define GQSPI_LPBK_DLY_ADJ_DLY_0 0x3
91 #define GQSPI_USE_DATA_DLY 0x1
92 #define GQSPI_USE_DATA_DLY_SHIFT 31
93 #define GQSPI_DATA_DLY_ADJ_VALUE 0x2
94 #define GQSPI_DATA_DLY_ADJ_SHIFT 28
95 #define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1
96 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2
97 #define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8
98 #define IOU_TAPDLY_BYPASS_OFST 0xFF180390
99 #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x00000020
100 #define GQSPI_FREQ_40MHZ 40000000
101 #define GQSPI_FREQ_100MHZ 100000000
102 #define GQSPI_FREQ_150MHZ 150000000
103 #define IOU_TAPDLY_BYPASS_MASK 0x7
105 #define GQSPI_REG_OFFSET 0x100
106 #define GQSPI_DMA_REG_OFFSET 0x800
108 /* QSPI register offsets */
109 struct zynqmp_qspi_regs {
110 u32 confr; /* 0x00 */
113 u32 idisr; /* 0x0C */
114 u32 imaskr; /* 0x10 */
117 u32 txd0r; /* 0x1C */
120 u32 txftr; /* 0x28 */
121 u32 rxftr; /* 0x2C */
122 u32 gpior; /* 0x30 */
123 u32 reserved0; /* 0x34 */
124 u32 lpbkdly; /* 0x38 */
125 u32 reserved1; /* 0x3C */
126 u32 genfifo; /* 0x40 */
127 u32 gqspisel; /* 0x44 */
128 u32 reserved2; /* 0x48 */
129 u32 gqfifoctrl; /* 0x4C */
130 u32 gqfthr; /* 0x50 */
131 u32 gqpollcfg; /* 0x54 */
132 u32 gqpollto; /* 0x58 */
133 u32 gqxfersts; /* 0x5C */
134 u32 gqfifosnap; /* 0x60 */
135 u32 gqrxcpy; /* 0x64 */
136 u32 reserved3[36]; /* 0x68 */
137 u32 gqspidlyadj; /* 0xF8 */
140 struct zynqmp_qspi_dma_regs {
141 u32 dmadst; /* 0x00 */
142 u32 dmasize; /* 0x04 */
143 u32 dmasts; /* 0x08 */
144 u32 dmactrl; /* 0x0C */
145 u32 reserved0; /* 0x10 */
146 u32 dmaisr; /* 0x14 */
147 u32 dmaier; /* 0x18 */
148 u32 dmaidr; /* 0x1C */
149 u32 dmaimr; /* 0x20 */
150 u32 dmactrl2; /* 0x24 */
151 u32 dmadstmsb; /* 0x28 */
154 DECLARE_GLOBAL_DATA_PTR;
156 struct zynqmp_qspi_platdata {
157 struct zynqmp_qspi_regs *regs;
158 struct zynqmp_qspi_dma_regs *dma_regs;
163 struct zynqmp_qspi_priv {
164 struct zynqmp_qspi_regs *regs;
165 struct zynqmp_qspi_dma_regs *dma_regs;
169 int bytes_to_transfer;
170 int bytes_to_receive;
171 unsigned int is_inst;
172 unsigned int cs_change:1;
175 static int zynqmp_qspi_ofdata_to_platdata(struct udevice *bus)
177 struct zynqmp_qspi_platdata *plat = bus->platdata;
179 debug("%s\n", __func__);
181 plat->regs = (struct zynqmp_qspi_regs *)(devfdt_get_addr(bus) +
183 plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
184 (devfdt_get_addr(bus) + GQSPI_DMA_REG_OFFSET);
189 static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
192 struct zynqmp_qspi_regs *regs = priv->regs;
194 writel(GQSPI_GFIFO_SELECT, ®s->gqspisel);
195 writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->idisr);
196 writel(GQSPI_FIFO_THRESHOLD, ®s->txftr);
197 writel(GQSPI_FIFO_THRESHOLD, ®s->rxftr);
198 writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->isr);
200 config_reg = readl(®s->confr);
201 config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
202 GQSPI_CONFIG_MODE_EN_MASK);
203 config_reg |= GQSPI_CONFIG_DMA_MODE |
204 GQSPI_GFIFO_WP_HOLD |
205 GQSPI_DFLT_BAUD_RATE_DIV;
206 writel(config_reg, ®s->confr);
208 writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
211 static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
213 u32 gqspi_fifo_reg = 0;
215 gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
216 GQSPI_GFIFO_CS_LOWER;
218 return gqspi_fifo_reg;
221 static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
224 struct zynqmp_qspi_regs *regs = priv->regs;
227 ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1,
230 printf("%s Timeout\n", __func__);
232 writel(gqspi_fifo_reg, ®s->genfifo);
235 static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
237 u32 gqspi_fifo_reg = 0;
240 gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
241 gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
242 GQSPI_IMD_DATA_CS_ASSERT;
244 gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS;
245 gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
248 debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
250 zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
253 void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
255 struct zynqmp_qspi_platdata *plat = bus->platdata;
256 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
257 struct zynqmp_qspi_regs *regs = priv->regs;
258 u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
261 clk_rate = plat->frequency;
262 reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
264 debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
265 __func__, reqhz, clk_rate, baudrateval);
267 if (reqhz < GQSPI_FREQ_40MHZ) {
268 zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
269 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
270 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
271 } else if (reqhz <= GQSPI_FREQ_100MHZ) {
272 zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
273 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
274 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
275 lpbkdlyadj = readl(®s->lpbkdly);
276 lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_LPBK_MASK);
277 datadlyadj = readl(®s->gqspidlyadj);
278 datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
279 | (GQSPI_DATA_DLY_ADJ_VALUE <<
280 GQSPI_DATA_DLY_ADJ_SHIFT));
281 } else if (reqhz <= GQSPI_FREQ_150MHZ) {
282 lpbkdlyadj = readl(®s->lpbkdly);
283 lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) |
284 GQSPI_LPBK_DLY_ADJ_DLY_0);
287 zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK,
289 writel(lpbkdlyadj, ®s->lpbkdly);
290 writel(datadlyadj, ®s->gqspidlyadj);
293 static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
295 struct zynqmp_qspi_platdata *plat = bus->platdata;
296 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
297 struct zynqmp_qspi_regs *regs = priv->regs;
299 u8 baud_rate_val = 0;
301 debug("%s\n", __func__);
302 if (speed > plat->frequency)
303 speed = plat->frequency;
305 /* Set the clock frequency */
306 confr = readl(®s->confr);
308 /* Set baudrate x8, if the freq is 0 */
309 baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
310 } else if (plat->speed_hz != speed) {
311 while ((baud_rate_val < 8) &&
313 (2 << baud_rate_val)) > speed))
316 if (baud_rate_val > GQSPI_MAX_BAUD_RATE_VAL)
317 baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
319 plat->speed_hz = plat->frequency / (2 << baud_rate_val);
321 confr &= ~GQSPI_BAUD_DIV_MASK;
322 confr |= (baud_rate_val << 3);
323 writel(confr, ®s->confr);
325 zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
326 debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
331 static int zynqmp_qspi_probe(struct udevice *bus)
333 struct zynqmp_qspi_platdata *plat = dev_get_platdata(bus);
334 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
339 debug("%s: bus:%p, priv:%p\n", __func__, bus, priv);
341 priv->regs = plat->regs;
342 priv->dma_regs = plat->dma_regs;
344 ret = clk_get_by_index(bus, 0, &clk);
346 dev_err(dev, "failed to get clock\n");
350 clock = clk_get_rate(&clk);
351 if (IS_ERR_VALUE(clock)) {
352 dev_err(dev, "failed to get rate\n");
355 debug("%s: CLK %ld\n", __func__, clock);
357 ret = clk_enable(&clk);
358 if (ret && ret != -ENOSYS) {
359 dev_err(dev, "failed to enable clock\n");
362 plat->frequency = clock;
363 plat->speed_hz = plat->frequency / 2;
365 /* init the zynq spi hw */
366 zynqmp_qspi_init_hw(priv);
371 static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
373 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
374 struct zynqmp_qspi_regs *regs = priv->regs;
377 debug("%s\n", __func__);
378 /* Set the SPI Clock phase and polarities */
379 confr = readl(®s->confr);
380 confr &= ~(GQSPI_CONFIG_CPHA_MASK |
381 GQSPI_CONFIG_CPOL_MASK);
384 confr |= GQSPI_CONFIG_CPHA_MASK;
386 confr |= GQSPI_CONFIG_CPOL_MASK;
388 writel(confr, ®s->confr);
393 static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
397 struct zynqmp_qspi_regs *regs = priv->regs;
398 u32 *buf = (u32 *)priv->tx_buf;
401 debug("TxFIFO: 0x%x, size: 0x%x\n", readl(®s->isr),
405 ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXNFULL_MASK, 1,
408 printf("%s: Timeout\n", __func__);
413 writel(*buf, ®s->txd0r);
421 data |= GENMASK(31, 8);
424 data = *((u16 *)buf);
426 data |= GENMASK(31, 16);
429 data = *((u16 *)buf);
431 data |= (*((u8 *)buf) << 16);
433 data |= GENMASK(31, 24);
436 writel(data, ®s->txd0r);
445 static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
451 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
452 gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_SPI_MODE_SPI;
453 gen_fifo_cmd |= *(u8 *)priv->tx_buf;
456 priv->tx_buf = (u8 *)priv->tx_buf + 1;
458 debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
460 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
464 static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
471 if (priv->len > 255) {
472 if (priv->len & (1 << expval)) {
473 *gen_fifo_cmd &= ~GQSPI_GFIFO_IMD_MASK;
474 *gen_fifo_cmd |= GQSPI_GFIFO_EXP_MASK;
475 *gen_fifo_cmd |= expval;
476 priv->len -= (1 << expval);
481 *gen_fifo_cmd &= ~(GQSPI_GFIFO_IMD_MASK |
482 GQSPI_GFIFO_EXP_MASK);
483 *gen_fifo_cmd |= (u8)priv->len;
491 static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
497 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
498 gen_fifo_cmd |= GQSPI_GFIFO_TX |
499 GQSPI_GFIFO_DATA_XFR_MASK;
501 gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
504 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
505 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
507 debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
509 if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
510 ret = zynqmp_qspi_fill_tx_fifo(priv,
513 ret = zynqmp_qspi_fill_tx_fifo(priv,
522 static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
523 u32 gen_fifo_cmd, u32 *buf)
527 u32 actuallen = priv->len;
529 struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
531 writel((unsigned long)buf, &dma_regs->dmadst);
532 writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize);
533 writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
534 addr = (unsigned long)buf;
535 size = roundup(priv->len, ARCH_DMA_MINALIGN);
536 flush_dcache_range(addr, addr + size);
539 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
540 if (!(gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) &&
541 (len % ARCH_DMA_MINALIGN)) {
542 gen_fifo_cmd &= ~GENMASK(7, 0);
543 gen_fifo_cmd |= roundup(len, ARCH_DMA_MINALIGN);
545 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
547 debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
550 ret = wait_for_bit_le32(&dma_regs->dmaisr, GQSPI_DMA_DST_I_STS_DONE,
551 1, GQSPI_TIMEOUT, 1);
553 printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
557 writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
559 debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
560 (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
563 if (buf != priv->rx_buf)
564 memcpy(priv->rx_buf, buf, actuallen);
569 static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
573 u32 actuallen = priv->len;
575 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
576 gen_fifo_cmd |= GQSPI_GFIFO_RX |
577 GQSPI_GFIFO_DATA_XFR_MASK;
579 gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
582 * Check if receive buffer is aligned to 4 byte and length
583 * is multiples of four byte as we are using dma to receive.
585 if (!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) &&
586 !(actuallen % GQSPI_DMA_ALIGN)) {
587 buf = (u32 *)priv->rx_buf;
588 return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
591 ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len,
594 return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
597 static int zynqmp_qspi_start_transfer(struct zynqmp_qspi_priv *priv)
603 zynqmp_qspi_genfifo_cmd(priv);
608 ret = zynqmp_qspi_genfifo_fill_tx(priv);
609 else if (priv->rx_buf)
610 ret = zynqmp_qspi_genfifo_fill_rx(priv);
617 static int zynqmp_qspi_transfer(struct zynqmp_qspi_priv *priv)
619 static unsigned int cs_change = 1;
622 debug("%s\n", __func__);
625 /* Select the chip if required */
627 zynqmp_qspi_chipselect(priv, 1);
629 cs_change = priv->cs_change;
631 if (!priv->tx_buf && !priv->rx_buf && priv->len) {
636 /* Request the transfer */
638 status = zynqmp_qspi_start_transfer(priv);
645 /* Deselect the chip */
646 zynqmp_qspi_chipselect(priv, 0);
653 static int zynqmp_qspi_claim_bus(struct udevice *dev)
655 struct udevice *bus = dev->parent;
656 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
657 struct zynqmp_qspi_regs *regs = priv->regs;
659 writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
664 static int zynqmp_qspi_release_bus(struct udevice *dev)
666 struct udevice *bus = dev->parent;
667 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
668 struct zynqmp_qspi_regs *regs = priv->regs;
670 writel(~GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
675 int zynqmp_qspi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout,
676 void *din, unsigned long flags)
678 struct udevice *bus = dev->parent;
679 struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
681 debug("%s: priv: 0x%08lx bitlen: %d dout: 0x%08lx ", __func__,
682 (unsigned long)priv, bitlen, (unsigned long)dout);
683 debug("din: 0x%08lx flags: 0x%lx\n", (unsigned long)din, flags);
687 priv->len = bitlen / 8;
690 * Assume that the beginning of a transfer with bits to
691 * transmit must contain a device command.
693 if (dout && flags & SPI_XFER_BEGIN)
698 if (flags & SPI_XFER_END)
703 zynqmp_qspi_transfer(priv);
708 static const struct dm_spi_ops zynqmp_qspi_ops = {
709 .claim_bus = zynqmp_qspi_claim_bus,
710 .release_bus = zynqmp_qspi_release_bus,
711 .xfer = zynqmp_qspi_xfer,
712 .set_speed = zynqmp_qspi_set_speed,
713 .set_mode = zynqmp_qspi_set_mode,
716 static const struct udevice_id zynqmp_qspi_ids[] = {
717 { .compatible = "xlnx,zynqmp-qspi-1.0" },
718 { .compatible = "xlnx,versal-qspi-1.0" },
722 U_BOOT_DRIVER(zynqmp_qspi) = {
723 .name = "zynqmp_qspi",
725 .of_match = zynqmp_qspi_ids,
726 .ops = &zynqmp_qspi_ops,
727 .ofdata_to_platdata = zynqmp_qspi_ofdata_to_platdata,
728 .platdata_auto_alloc_size = sizeof(struct zynqmp_qspi_platdata),
729 .priv_auto_alloc_size = sizeof(struct zynqmp_qspi_priv),
730 .probe = zynqmp_qspi_probe,