4 * supports 8 bit SPI transfers only, with or w/o FIFO
6 * based on bfin_spi.c, by way of altera_spi.c
7 * Copyright (c) 2005-2008 Analog Devices Inc.
8 * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
9 * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
10 * Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
12 * SPDX-License-Identifier: GPL-2.0+
14 * [0]: http://www.xilinx.com/support/documentation
16 * [S]: [0]/ip_documentation/xps_spi.pdf
17 * [0]/ip_documentation/axi_spi_ds742.pdf
25 * Xilinx SPI Register Definition
27 * [1]: [0]/ip_documentation/xps_spi.pdf
28 * page 8, Register Descriptions
29 * [2]: [0]/ip_documentation/axi_spi_ds742.pdf
30 * page 7, Register Overview Table
32 struct xilinx_spi_reg {
34 u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
35 u32 ipisr; /* IP Interrupt Status Register (IPISR) */
37 u32 ipier; /* IP Interrupt Enable Register (IPIER) */
39 u32 srr; /* Softare Reset Register (SRR) */
41 u32 spicr; /* SPI Control Register (SPICR) */
42 u32 spisr; /* SPI Status Register (SPISR) */
43 u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
44 u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
45 u32 spissr; /* SPI Slave Select Register (SPISSR) */
46 u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */
47 u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
50 /* Device Global Interrupt Enable Register (dgier), [1] p15, [2] p15 */
51 #define DGIER_GIE (1 << 31)
53 /* IP Interrupt Status Register (ipisr), [1] p15, [2] p15 */
54 #define IPISR_DRR_NOT_EMPTY (1 << 8)
55 #define IPISR_SLAVE_SELECT (1 << 7)
56 #define IPISR_TXF_HALF_EMPTY (1 << 6)
57 #define IPISR_DRR_OVERRUN (1 << 5)
58 #define IPISR_DRR_FULL (1 << 4)
59 #define IPISR_DTR_UNDERRUN (1 << 3)
60 #define IPISR_DTR_EMPTY (1 << 2)
61 #define IPISR_SLAVE_MODF (1 << 1)
62 #define IPISR_MODF (1 << 0)
64 /* IP Interrupt Enable Register (ipier), [1] p17, [2] p18 */
65 #define IPIER_DRR_NOT_EMPTY (1 << 8)
66 #define IPIER_SLAVE_SELECT (1 << 7)
67 #define IPIER_TXF_HALF_EMPTY (1 << 6)
68 #define IPIER_DRR_OVERRUN (1 << 5)
69 #define IPIER_DRR_FULL (1 << 4)
70 #define IPIER_DTR_UNDERRUN (1 << 3)
71 #define IPIER_DTR_EMPTY (1 << 2)
72 #define IPIER_SLAVE_MODF (1 << 1)
73 #define IPIER_MODF (1 << 0)
75 /* Softare Reset Register (srr), [1] p9, [2] p8 */
76 #define SRR_RESET_CODE 0x0000000A
78 /* SPI Control Register (spicr), [1] p9, [2] p8 */
79 #define SPICR_LSB_FIRST (1 << 9)
80 #define SPICR_MASTER_INHIBIT (1 << 8)
81 #define SPICR_MANUAL_SS (1 << 7)
82 #define SPICR_RXFIFO_RESEST (1 << 6)
83 #define SPICR_TXFIFO_RESEST (1 << 5)
84 #define SPICR_CPHA (1 << 4)
85 #define SPICR_CPOL (1 << 3)
86 #define SPICR_MASTER_MODE (1 << 2)
87 #define SPICR_SPE (1 << 1)
88 #define SPICR_LOOP (1 << 0)
90 /* SPI Status Register (spisr), [1] p11, [2] p10 */
91 #define SPISR_SLAVE_MODE_SELECT (1 << 5)
92 #define SPISR_MODF (1 << 4)
93 #define SPISR_TX_FULL (1 << 3)
94 #define SPISR_TX_EMPTY (1 << 2)
95 #define SPISR_RX_FULL (1 << 1)
96 #define SPISR_RX_EMPTY (1 << 0)
98 /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
99 #define SPIDTR_8BIT_MASK (0xff << 0)
100 #define SPIDTR_16BIT_MASK (0xffff << 0)
101 #define SPIDTR_32BIT_MASK (0xffffffff << 0)
103 /* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
104 #define SPIDRR_8BIT_MASK (0xff << 0)
105 #define SPIDRR_16BIT_MASK (0xffff << 0)
106 #define SPIDRR_32BIT_MASK (0xffffffff << 0)
108 /* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
109 #define SPISSR_MASK(cs) (1 << (cs))
110 #define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
111 #define SPISSR_OFF ~0UL
113 /* SPI Transmit FIFO Occupancy Register (spitfor), [1] p13, [2] p14 */
114 #define SPITFOR_OCYVAL_POS 0
115 #define SPITFOR_OCYVAL_MASK (0xf << SPITFOR_OCYVAL_POS)
117 /* SPI Receive FIFO Occupancy Register (spirfor), [1] p14, [2] p14 */
118 #define SPIRFOR_OCYVAL_POS 0
119 #define SPIRFOR_OCYVAL_MASK (0xf << SPIRFOR_OCYVAL_POS)
121 /* SPI Software Reset Register (ssr) */
122 #define SPISSR_RESET_VALUE 0x0a
124 struct xilinx_spi_slave {
125 struct spi_slave slave;
126 struct xilinx_spi_reg *regs;
131 static inline struct xilinx_spi_slave *to_xilinx_spi_slave(
132 struct spi_slave *slave)
134 return container_of(slave, struct xilinx_spi_slave, slave);
137 #ifndef CONFIG_SYS_XILINX_SPI_LIST
138 #define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
141 #ifndef CONFIG_XILINX_SPI_IDLE_VAL
142 #define CONFIG_XILINX_SPI_IDLE_VAL 0xff
145 #define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | \
146 SPICR_MASTER_MODE | \
149 #define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | \
152 #define XILSPI_MAX_XFER_BITS 8
154 static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
156 __attribute__((weak))
157 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
159 return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32;
162 __attribute__((weak))
163 void spi_cs_activate(struct spi_slave *slave)
165 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
167 writel(SPISSR_ACT(slave->cs), &xilspi->regs->spissr);
170 __attribute__((weak))
171 void spi_cs_deactivate(struct spi_slave *slave)
173 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
175 writel(SPISSR_OFF, &xilspi->regs->spissr);
183 void spi_set_speed(struct spi_slave *slave, uint hz)
185 /* xilinx spi core does not support programmable speed */
188 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
189 unsigned int max_hz, unsigned int mode)
191 struct xilinx_spi_slave *xilspi;
193 if (!spi_cs_is_valid(bus, cs)) {
194 printf("XILSPI error: %s: unsupported bus %d / cs %d\n",
199 xilspi = spi_alloc_slave(struct xilinx_spi_slave, bus, cs);
201 printf("XILSPI error: %s: malloc of SPI structure failed\n",
205 xilspi->regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus];
206 xilspi->freq = max_hz;
208 debug("%s: bus:%i cs:%i base:%p mode:%x max_hz:%d\n", __func__,
209 bus, cs, xilspi->regs, xilspi->mode, xilspi->freq);
211 writel(SPISSR_RESET_VALUE, &xilspi->regs->srr);
213 return &xilspi->slave;
216 void spi_free_slave(struct spi_slave *slave)
218 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
223 int spi_claim_bus(struct spi_slave *slave)
225 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
228 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
229 writel(SPISSR_OFF, &xilspi->regs->spissr);
231 spicr = XILSPI_SPICR_DFLT_ON;
232 if (xilspi->mode & SPI_LSB_FIRST)
233 spicr |= SPICR_LSB_FIRST;
234 if (xilspi->mode & SPI_CPHA)
236 if (xilspi->mode & SPI_CPOL)
238 if (xilspi->mode & SPI_LOOP)
241 writel(spicr, &xilspi->regs->spicr);
245 void spi_release_bus(struct spi_slave *slave)
247 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
249 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
250 writel(SPISSR_OFF, &xilspi->regs->spissr);
251 writel(XILSPI_SPICR_DFLT_OFF, &xilspi->regs->spicr);
254 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
255 void *din, unsigned long flags)
257 struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
258 /* assume spi core configured to do 8 bit transfers */
259 unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
260 const unsigned char *txp = dout;
261 unsigned char *rxp = din;
262 unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */
263 unsigned global_timeout;
265 debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
266 slave->bus, slave->cs, bitlen, bytes, flags);
270 if (bitlen % XILSPI_MAX_XFER_BITS) {
271 printf("XILSPI warning: %s: Not a multiple of %d bits\n",
272 __func__, XILSPI_MAX_XFER_BITS);
273 flags |= SPI_XFER_END;
277 /* empty read buffer */
278 while (rxecount && !(readl(&xilspi->regs->spisr) & SPISR_RX_EMPTY)) {
279 readl(&xilspi->regs->spidrr);
284 printf("XILSPI error: %s: Rx buffer not empty\n", __func__);
288 if (flags & SPI_XFER_BEGIN)
289 spi_cs_activate(slave);
291 /* at least 1usec or greater, leftover 1 */
292 global_timeout = xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 :
293 (XILSPI_MAX_XFER_BITS * 1000000 / xilspi->freq) + 1;
296 unsigned timeout = global_timeout;
297 /* get Tx element from data out buffer and count up */
298 unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
299 debug("%s: tx:%x ", __func__, d);
301 /* write out and wait for processing (receive data) */
302 writel(d & SPIDTR_8BIT_MASK, &xilspi->regs->spidtr);
303 while (timeout && readl(&xilspi->regs->spisr)
310 printf("XILSPI error: %s: Xfer timeout\n", __func__);
314 /* read Rx element and push into data in buffer */
315 d = readl(&xilspi->regs->spidrr) & SPIDRR_8BIT_MASK;
322 if (flags & SPI_XFER_END)
323 spi_cs_deactivate(slave);