1 // SPDX-License-Identifier: GPL-2.0+
3 * uniphier_spi.c - Socionext UniPhier SPI driver
4 * Copyright 2019 Socionext, Inc.
11 #include <dm/device_compat.h>
12 #include <linux/bitfield.h>
17 DECLARE_GLOBAL_DATA_PTR;
20 #define SSI_CTL_EN BIT(0)
23 #define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
24 #define SSI_CKS_CKPHS BIT(14)
25 #define SSI_CKS_CKINIT BIT(13)
26 #define SSI_CKS_CKDLY BIT(12)
28 #define SSI_TXWDS 0x08
29 #define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
30 #define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
31 #define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
33 #define SSI_RXWDS 0x0c
34 #define SSI_RXWDS_RDTF_MASK GENMASK(7, 6)
35 #define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
38 #define SSI_FPS_FSPOL BIT(15)
39 #define SSI_FPS_FSTRT BIT(14)
42 #define SSI_SR_BUSY BIT(7)
43 #define SSI_SR_TNF BIT(5)
44 #define SSI_SR_RNE BIT(0)
49 #define SSI_IC_TCIC BIT(4)
50 #define SSI_IC_RCIC BIT(3)
51 #define SSI_IC_RORIC BIT(0)
54 #define SSI_FC_TXFFL BIT(12)
55 #define SSI_FC_TXFTH_MASK GENMASK(11, 8)
56 #define SSI_FC_RXFFL BIT(4)
57 #define SSI_FC_RXFTH_MASK GENMASK(3, 0)
59 #define SSI_XDR 0x24 /* TXDR for write, RXDR for read */
61 #define SSI_FIFO_DEPTH 8U
63 #define SSI_REG_TIMEOUT (CONFIG_SYS_HZ / 100) /* 10 ms */
64 #define SSI_XFER_TIMEOUT (CONFIG_SYS_HZ) /* 1 sec */
66 #define SSI_CLK 50000000 /* internal I/O clock: 50MHz */
68 struct uniphier_spi_platdata {
70 u32 frequency; /* input frequency */
72 uint deactivate_delay_us; /* Delay to wait after deactivate */
73 uint activate_delay_us; /* Delay to wait after activate */
76 struct uniphier_spi_priv {
81 ulong last_transaction_us; /* Time of last transaction end */
84 static void uniphier_spi_enable(struct uniphier_spi_priv *priv, int enable)
88 val = readl(priv->base + SSI_CTL);
93 writel(val, priv->base + SSI_CTL);
96 static void uniphier_spi_regdump(struct uniphier_spi_priv *priv)
98 pr_debug("CTL %08x\n", readl(priv->base + SSI_CTL));
99 pr_debug("CKS %08x\n", readl(priv->base + SSI_CKS));
100 pr_debug("TXWDS %08x\n", readl(priv->base + SSI_TXWDS));
101 pr_debug("RXWDS %08x\n", readl(priv->base + SSI_RXWDS));
102 pr_debug("FPS %08x\n", readl(priv->base + SSI_FPS));
103 pr_debug("SR %08x\n", readl(priv->base + SSI_SR));
104 pr_debug("IE %08x\n", readl(priv->base + SSI_IE));
105 pr_debug("IC %08x\n", readl(priv->base + SSI_IC));
106 pr_debug("FC %08x\n", readl(priv->base + SSI_FC));
107 pr_debug("XDR %08x\n", readl(priv->base + SSI_XDR));
110 static void spi_cs_activate(struct udevice *dev)
112 struct udevice *bus = dev->parent;
113 struct uniphier_spi_platdata *plat = bus->platdata;
114 struct uniphier_spi_priv *priv = dev_get_priv(bus);
115 ulong delay_us; /* The delay completed so far */
118 /* If it's too soon to do another transaction, wait */
119 if (plat->deactivate_delay_us && priv->last_transaction_us) {
120 delay_us = timer_get_us() - priv->last_transaction_us;
121 if (delay_us < plat->deactivate_delay_us)
122 udelay(plat->deactivate_delay_us - delay_us);
125 val = readl(priv->base + SSI_FPS);
126 if (priv->mode & SPI_CS_HIGH)
127 val |= SSI_FPS_FSPOL;
129 val &= ~SSI_FPS_FSPOL;
130 writel(val, priv->base + SSI_FPS);
132 if (plat->activate_delay_us)
133 udelay(plat->activate_delay_us);
136 static void spi_cs_deactivate(struct udevice *dev)
138 struct udevice *bus = dev->parent;
139 struct uniphier_spi_platdata *plat = bus->platdata;
140 struct uniphier_spi_priv *priv = dev_get_priv(bus);
143 val = readl(priv->base + SSI_FPS);
144 if (priv->mode & SPI_CS_HIGH)
145 val &= ~SSI_FPS_FSPOL;
147 val |= SSI_FPS_FSPOL;
148 writel(val, priv->base + SSI_FPS);
150 /* Remember time of this transaction so we can honour the bus delay */
151 if (plat->deactivate_delay_us)
152 priv->last_transaction_us = timer_get_us();
155 static int uniphier_spi_claim_bus(struct udevice *dev)
157 struct udevice *bus = dev->parent;
158 struct uniphier_spi_priv *priv = dev_get_priv(bus);
161 uniphier_spi_enable(priv, false);
163 /* disable interrupts */
164 writel(0, priv->base + SSI_IE);
167 size = priv->bits_per_word;
168 val = readl(priv->base + SSI_TXWDS);
169 val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
170 val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
171 val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
172 writel(val, priv->base + SSI_TXWDS);
174 val = readl(priv->base + SSI_RXWDS);
175 val &= ~SSI_RXWDS_DTLEN_MASK;
176 val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
177 writel(val, priv->base + SSI_RXWDS);
180 val = SSI_FC_TXFFL | SSI_FC_RXFFL;
181 writel(val, priv->base + SSI_FC);
184 val = readl(priv->base + SSI_FC);
185 val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
186 val |= FIELD_PREP(SSI_FC_TXFTH_MASK, priv->fifo_depth);
187 val |= FIELD_PREP(SSI_FC_RXFTH_MASK, priv->fifo_depth);
188 writel(val, priv->base + SSI_FC);
190 /* clear interrupts */
191 writel(SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC,
192 priv->base + SSI_IC);
194 uniphier_spi_enable(priv, true);
199 static int uniphier_spi_release_bus(struct udevice *dev)
201 struct udevice *bus = dev->parent;
202 struct uniphier_spi_priv *priv = dev_get_priv(bus);
204 uniphier_spi_enable(priv, false);
209 static int uniphier_spi_xfer(struct udevice *dev, unsigned int bitlen,
210 const void *dout, void *din, unsigned long flags)
212 struct udevice *bus = dev->parent;
213 struct uniphier_spi_priv *priv = dev_get_priv(bus);
214 const u8 *tx_buf = dout;
215 u8 *rx_buf = din, buf;
216 u32 len = bitlen / 8;
222 dev_err(dev, "Non byte aligned SPI transfer\n");
226 if (flags & SPI_XFER_BEGIN)
227 spi_cs_activate(dev);
229 uniphier_spi_enable(priv, true);
235 uniphier_spi_regdump(priv);
237 while (tx_len || rx_len) {
238 ret = wait_for_bit_le32(priv->base + SSI_SR, SSI_SR_BUSY, false,
239 SSI_REG_TIMEOUT * 1000, false);
241 if (ret == -ETIMEDOUT)
242 dev_err(dev, "access timeout\n");
246 status = readl(priv->base + SSI_SR);
247 /* write the data into TX */
248 if (tx_len && (status & SSI_SR_TNF)) {
249 buf = tx_buf ? *tx_buf++ : 0;
250 writel(buf, priv->base + SSI_XDR);
254 /* read the data from RX */
255 if (rx_len && (status & SSI_SR_RNE)) {
256 buf = readl(priv->base + SSI_XDR);
262 if (get_timer(ts) >= SSI_XFER_TIMEOUT) {
263 dev_err(dev, "transfer timeout\n");
269 if (flags & SPI_XFER_END)
270 spi_cs_deactivate(dev);
272 uniphier_spi_enable(priv, false);
277 static int uniphier_spi_set_speed(struct udevice *bus, uint speed)
279 struct uniphier_spi_platdata *plat = bus->platdata;
280 struct uniphier_spi_priv *priv = dev_get_priv(bus);
283 if (speed > plat->frequency)
284 speed = plat->frequency;
287 ckdiv = DIV_ROUND_UP(SSI_CLK, speed);
288 ckdiv = round_up(ckdiv, 2);
290 val = readl(priv->base + SSI_CKS);
291 val &= ~SSI_CKS_CKRAT_MASK;
292 val |= ckdiv & SSI_CKS_CKRAT_MASK;
293 writel(val, priv->base + SSI_CKS);
298 static int uniphier_spi_set_mode(struct udevice *bus, uint mode)
300 struct uniphier_spi_priv *priv = dev_get_priv(bus);
305 * CKPHS capture timing. 0:rising edge, 1:falling edge
306 * CKINIT clock initial level. 0:low, 1:high
307 * CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT
308 * (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
311 * FSPOL frame signal porarity. 0: low, 1: high
312 * FSTRT start frame timing
313 * 0: rising edge of clock, 1: falling edge of clock
315 val1 = readl(priv->base + SSI_CKS);
316 val2 = readl(priv->base + SSI_FPS);
318 switch (mode & (SPI_CPOL | SPI_CPHA)) {
320 /* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
321 val1 |= SSI_CKS_CKPHS | SSI_CKS_CKDLY;
322 val1 &= ~SSI_CKS_CKINIT;
323 val2 &= ~SSI_FPS_FSTRT;
326 /* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
327 val1 &= ~(SSI_CKS_CKPHS | SSI_CKS_CKINIT | SSI_CKS_CKDLY);
328 val2 |= SSI_FPS_FSTRT;
331 /* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
332 val1 |= SSI_CKS_CKINIT | SSI_CKS_CKDLY;
333 val1 &= ~SSI_CKS_CKPHS;
334 val2 |= SSI_FPS_FSTRT;
337 /* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
338 val1 |= SSI_CKS_CKPHS | SSI_CKS_CKINIT;
339 val1 &= ~SSI_CKS_CKDLY;
340 val2 &= ~SSI_FPS_FSTRT;
344 writel(val1, priv->base + SSI_CKS);
345 writel(val2, priv->base + SSI_FPS);
348 val1 = readl(priv->base + SSI_TXWDS);
349 val2 = readl(priv->base + SSI_RXWDS);
350 if (mode & SPI_LSB_FIRST) {
351 val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
352 val2 |= FIELD_PREP(SSI_RXWDS_RDTF_MASK, 1);
354 writel(val1, priv->base + SSI_TXWDS);
355 writel(val2, priv->base + SSI_RXWDS);
362 static int uniphier_spi_ofdata_to_platdata(struct udevice *bus)
364 struct uniphier_spi_platdata *plat = bus->platdata;
365 const void *blob = gd->fdt_blob;
366 int node = dev_of_offset(bus);
368 plat->base = devfdt_get_addr_ptr(bus);
371 fdtdec_get_int(blob, node, "spi-max-frequency", 12500000);
372 plat->deactivate_delay_us =
373 fdtdec_get_int(blob, node, "spi-deactivate-delay", 0);
374 plat->activate_delay_us =
375 fdtdec_get_int(blob, node, "spi-activate-delay", 0);
376 plat->speed_hz = plat->frequency / 2;
381 static int uniphier_spi_probe(struct udevice *bus)
383 struct uniphier_spi_platdata *plat = dev_get_platdata(bus);
384 struct uniphier_spi_priv *priv = dev_get_priv(bus);
386 priv->base = plat->base;
387 priv->fifo_depth = SSI_FIFO_DEPTH;
388 priv->bits_per_word = 8;
393 static const struct dm_spi_ops uniphier_spi_ops = {
394 .claim_bus = uniphier_spi_claim_bus,
395 .release_bus = uniphier_spi_release_bus,
396 .xfer = uniphier_spi_xfer,
397 .set_speed = uniphier_spi_set_speed,
398 .set_mode = uniphier_spi_set_mode,
401 static const struct udevice_id uniphier_spi_ids[] = {
402 { .compatible = "socionext,uniphier-scssi" },
406 U_BOOT_DRIVER(uniphier_spi) = {
407 .name = "uniphier_spi",
409 .of_match = uniphier_spi_ids,
410 .ops = &uniphier_spi_ops,
411 .ofdata_to_platdata = uniphier_spi_ofdata_to_platdata,
412 .platdata_auto_alloc_size = sizeof(struct uniphier_spi_platdata),
413 .priv_auto_alloc_size = sizeof(struct uniphier_spi_priv),
414 .probe = uniphier_spi_probe,