drivers/spi/ti_qspi.c

   1 /*
   2  * TI QSPI driver
   3  *
   4  * Copyright (C) 2013, Texas Instruments, Incorporated
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/omap.h>
  12 #include <malloc.h>
  13 #include <spi.h>
  14 #include <dm.h>
  15 #include <asm/gpio.h>
  16 #include <asm/omap_gpio.h>
  17 #include <asm/omap_common.h>
  18 #include <asm/ti-common/ti-edma3.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 /* ti qpsi register bit masks */
  23 #define QSPI_TIMEOUT                    2000000
  24 #define QSPI_FCLK                       192000000
  25 /* clock control */
  26 #define QSPI_CLK_EN                     BIT(31)
  27 #define QSPI_CLK_DIV_MAX                0xffff
  28 /* command */
  29 #define QSPI_EN_CS(n)                   (n << 28)
  30 #define QSPI_WLEN(n)                    ((n-1) << 19)
  31 #define QSPI_3_PIN                      BIT(18)
  32 #define QSPI_RD_SNGL                    BIT(16)
  33 #define QSPI_WR_SNGL                    (2 << 16)
  34 #define QSPI_INVAL                      (4 << 16)
  35 #define QSPI_RD_QUAD                    (7 << 16)
  36 /* device control */
  37 #define QSPI_DD(m, n)                   (m << (3 + n*8))
  38 #define QSPI_CKPHA(n)                   (1 << (2 + n*8))
  39 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
  40 #define QSPI_CKPOL(n)                   (1 << (n*8))
  41 /* status */
  42 #define QSPI_WC                         BIT(1)
  43 #define QSPI_BUSY                       BIT(0)
  44 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
  45 #define QSPI_XFER_DONE                  QSPI_WC
  46 #define MM_SWITCH                       0x01
  47 #define MEM_CS(cs)                      ((cs + 1) << 8)
  48 #define MEM_CS_UNSELECT                 0xfffff8ff
  49 #define MMAP_START_ADDR_DRA             0x5c000000
  50 #define MMAP_START_ADDR_AM43x           0x30000000
  51 #define CORE_CTRL_IO                    0x4a002558
  52
  53 #define QSPI_CMD_READ                   (0x3 << 0)
  54 #define QSPI_CMD_READ_DUAL              (0x6b << 0)
  55 #define QSPI_CMD_READ_QUAD              (0x6c << 0)
  56 #define QSPI_CMD_READ_FAST              (0x0b << 0)
  57 #define QSPI_SETUP0_NUM_A_BYTES         (0x3 << 8)
  58 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
  59 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS  (0x1 << 10)
  60 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
  61 #define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
  62 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
  63 #define QSPI_CMD_WRITE                  (0x12 << 16)
  64 #define QSPI_NUM_DUMMY_BITS             (0x0 << 24)
  65
  66 /* ti qspi register set */
  67 struct ti_qspi_regs {
  68         u32 pid;
  69         u32 pad0[3];
  70         u32 sysconfig;
  71         u32 pad1[3];
  72         u32 int_stat_raw;
  73         u32 int_stat_en;
  74         u32 int_en_set;
  75         u32 int_en_ctlr;
  76         u32 intc_eoi;
  77         u32 pad2[3];
  78         u32 clk_ctrl;
  79         u32 dc;
  80         u32 cmd;
  81         u32 status;
  82         u32 data;
  83         u32 setup0;
  84         u32 setup1;
  85         u32 setup2;
  86         u32 setup3;
  87         u32 memswitch;
  88         u32 data1;
  89         u32 data2;
  90         u32 data3;
  91 };
  92
  93 /* ti qspi priv */
  94 struct ti_qspi_priv {
  95 #ifndef CONFIG_DM_SPI
  96         struct spi_slave slave;
  97 #else
  98         void *memory_map;
  99         uint max_hz;
 100         u32 num_cs;
 101 #endif
 102         struct ti_qspi_regs *base;
 103         void *ctrl_mod_mmap;
 104         unsigned int mode;
 105         u32 cmd;
 106         u32 dc;
 107 };
 108
 109 static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
 110 {
 111         uint clk_div;
 112
 113         if (!hz)
 114                 clk_div = 0;
 115         else
 116                 clk_div = (QSPI_FCLK / hz) - 1;
 117
 118         debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 119
 120         /* disable SCLK */
 121         writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
 122                &priv->base->clk_ctrl);
 123
 124         /* assign clk_div values */
 125         if (clk_div < 0)
 126                 clk_div = 0;
 127         else if (clk_div > QSPI_CLK_DIV_MAX)
 128                 clk_div = QSPI_CLK_DIV_MAX;
 129
 130         /* enable SCLK */
 131         writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 132 }
 133
 134 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
 135 {
 136         writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
 137         /* dummy readl to ensure bus sync */
 138         readl(&priv->base->cmd);
 139 }
 140
 141 static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
 142 {
 143         priv->dc = 0;
 144         if (mode & SPI_CPHA)
 145                 priv->dc |= QSPI_CKPHA(0);
 146         if (mode & SPI_CPOL)
 147                 priv->dc |= QSPI_CKPOL(0);
 148         if (mode & SPI_CS_HIGH)
 149                 priv->dc |= QSPI_CSPOL(0);
 150
 151         return 0;
 152 }
 153
 154 static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
 155 {
 156         writel(priv->dc, &priv->base->dc);
 157         writel(0, &priv->base->cmd);
 158         writel(0, &priv->base->data);
 159
 160         priv->dc <<= cs * 8;
 161         writel(priv->dc, &priv->base->dc);
 162
 163         return 0;
 164 }
 165
 166 static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
 167 {
 168         writel(0, &priv->base->dc);
 169         writel(0, &priv->base->cmd);
 170         writel(0, &priv->base->data);
 171 }
 172
 173 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
 174 {
 175         u32 val;
 176
 177         val = readl(ctrl_mod_mmap);
 178         if (enable)
 179                 val |= MEM_CS(cs);
 180         else
 181                 val &= MEM_CS_UNSELECT;
 182         writel(val, ctrl_mod_mmap);
 183 }
 184
 185 static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
 186                         const void *dout, void *din, unsigned long flags,
 187                         u32 cs)
 188 {
 189         uint words = bitlen >> 3; /* fixed 8-bit word length */
 190         const uchar *txp = dout;
 191         uchar *rxp = din;
 192         uint status;
 193         int timeout;
 194
 195         /* Setup mmap flags */
 196         if (flags & SPI_XFER_MMAP) {
 197                 writel(MM_SWITCH, &priv->base->memswitch);
 198                 if (priv->ctrl_mod_mmap)
 199                         ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
 200                 return 0;
 201         } else if (flags & SPI_XFER_MMAP_END) {
 202                 writel(~MM_SWITCH, &priv->base->memswitch);
 203                 if (priv->ctrl_mod_mmap)
 204                         ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
 205                 return 0;
 206         }
 207
 208         if (bitlen == 0)
 209                 return -1;
 210
 211         if (bitlen % 8) {
 212                 debug("spi_xfer: Non byte aligned SPI transfer\n");
 213                 return -1;
 214         }
 215
 216         /* Setup command reg */
 217         priv->cmd = 0;
 218         priv->cmd |= QSPI_WLEN(8);
 219         priv->cmd |= QSPI_EN_CS(cs);
 220         if (priv->mode & SPI_3WIRE)
 221                 priv->cmd |= QSPI_3_PIN;
 222         priv->cmd |= 0xfff;
 223
 224 /* FIXME: This delay is required for successfull
 225  * completion of read/write/erase. Once its root
 226  * caused, it will be remove from the driver.
 227  */
 228 #ifdef CONFIG_AM43XX
 229         udelay(100);
 230 #endif
 231         while (words--) {
 232                 if (txp) {
 233                         debug("tx cmd %08x dc %08x data %02x\n",
 234                               priv->cmd | QSPI_WR_SNGL, priv->dc, *txp);
 235                         writel(*txp++, &priv->base->data);
 236                         writel(priv->cmd | QSPI_WR_SNGL,
 237                                &priv->base->cmd);
 238                         status = readl(&priv->base->status);
 239                         timeout = QSPI_TIMEOUT;
 240                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 241                                 if (--timeout < 0) {
 242                                         printf("spi_xfer: TX timeout!\n");
 243                                         return -1;
 244                                 }
 245                                 status = readl(&priv->base->status);
 246                         }
 247                         debug("tx done, status %08x\n", status);
 248                 }
 249                 if (rxp) {
 250                         debug("rx cmd %08x dc %08x\n",
 251                               ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
 252                         #ifdef CONFIG_DRA7XX
 253                                 udelay(500);
 254                         #endif
 255                         writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
 256                         status = readl(&priv->base->status);
 257                         timeout = QSPI_TIMEOUT;
 258                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 259                                 if (--timeout < 0) {
 260                                         printf("spi_xfer: RX timeout!\n");
 261                                         return -1;
 262                                 }
 263                                 status = readl(&priv->base->status);
 264                         }
 265                         *rxp++ = readl(&priv->base->data);
 266                         debug("rx done, status %08x, read %02x\n",
 267                               status, *(rxp-1));
 268                 }
 269         }
 270
 271         /* Terminate frame */
 272         if (flags & SPI_XFER_END)
 273                 ti_qspi_cs_deactivate(priv);
 274
 275         return 0;
 276 }
 277
 278 /* TODO: control from sf layer to here through dm-spi */
 279 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
 280 void spi_flash_copy_mmap(void *data, void *offset, size_t len)
 281 {
 282         unsigned int                    addr = (unsigned int) (data);
 283         unsigned int                    edma_slot_num = 1;
 284
 285         /* Invalidate the area, so no writeback into the RAM races with DMA */
 286         invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
 287
 288         /* enable edma3 clocks */
 289         enable_edma3_clocks();
 290
 291         /* Call edma3 api to do actual DMA transfer     */
 292         edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
 293
 294         /* disable edma3 clocks */
 295         disable_edma3_clocks();
 296
 297         *((unsigned int *)offset) += len;
 298 }
 299 #endif
 300
 301 #ifndef CONFIG_DM_SPI
 302
 303 static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
 304 {
 305         return container_of(slave, struct ti_qspi_priv, slave);
 306 }
 307
 308 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 309 {
 310         return 1;
 311 }
 312
 313 void spi_cs_activate(struct spi_slave *slave)
 314 {
 315         /* CS handled in xfer */
 316         return;
 317 }
 318
 319 void spi_cs_deactivate(struct spi_slave *slave)
 320 {
 321         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 322         ti_qspi_cs_deactivate(priv);
 323 }
 324
 325 void spi_init(void)
 326 {
 327         /* nothing to do */
 328 }
 329
 330 static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
 331 {
 332         u32 memval = 0;
 333
 334 #ifdef CONFIG_QSPI_QUAD_SUPPORT
 335         struct spi_slave *slave = &priv->slave;
 336         memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
 337                         QSPI_SETUP0_NUM_D_BYTES_8_BITS |
 338                         QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
 339                         QSPI_NUM_DUMMY_BITS);
 340         slave->mode_rx = SPI_RX_QUAD;
 341 #else
 342         memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
 343                         QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
 344                         QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
 345                         QSPI_NUM_DUMMY_BITS;
 346 #endif
 347
 348         writel(memval, &priv->base->setup0);
 349 }
 350
 351 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 352                                   unsigned int max_hz, unsigned int mode)
 353 {
 354         struct ti_qspi_priv *priv;
 355
 356 #ifdef CONFIG_AM43XX
 357         gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
 358         gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
 359 #endif
 360
 361         priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
 362         if (!priv) {
 363                 printf("SPI_error: Fail to allocate ti_qspi_priv\n");
 364                 return NULL;
 365         }
 366
 367         priv->base = (struct ti_qspi_regs *)QSPI_BASE;
 368         priv->mode = mode;
 369 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 370         priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
 371         priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
 372 #else
 373         priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
 374 #endif
 375
 376         ti_spi_set_speed(priv, max_hz);
 377
 378 #ifdef CONFIG_TI_SPI_MMAP
 379         ti_spi_setup_spi_register(priv);
 380 #endif
 381
 382         return &priv->slave;
 383 }
 384
 385 void spi_free_slave(struct spi_slave *slave)
 386 {
 387         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 388         free(priv);
 389 }
 390
 391 int spi_claim_bus(struct spi_slave *slave)
 392 {
 393         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 394
 395         debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
 396         __ti_qspi_set_mode(priv, priv->mode);
 397         return __ti_qspi_claim_bus(priv, priv->slave.cs);
 398 }
 399 void spi_release_bus(struct spi_slave *slave)
 400 {
 401         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 402
 403         debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
 404         __ti_qspi_release_bus(priv);
 405 }
 406
 407 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 408              void *din, unsigned long flags)
 409 {
 410         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 411
 412         debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
 413               priv->slave.bus, priv->slave.cs, bitlen, flags);
 414         return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
 415 }
 416
 417 #else /* CONFIG_DM_SPI */
 418
 419 static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
 420                                       struct spi_slave *slave,
 421                                       bool enable)
 422 {
 423         u32 memval;
 424         u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL);
 425
 426         if (!enable) {
 427                 writel(0, &priv->base->setup0);
 428                 return;
 429         }
 430
 431         memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
 432
 433         switch (mode) {
 434         case SPI_RX_QUAD:
 435                 memval |= QSPI_CMD_READ_QUAD;
 436                 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
 437                 memval |= QSPI_SETUP0_READ_QUAD;
 438                 slave->mode_rx = SPI_RX_QUAD;
 439                 break;
 440         case SPI_RX_DUAL:
 441                 memval |= QSPI_CMD_READ_DUAL;
 442                 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
 443                 memval |= QSPI_SETUP0_READ_DUAL;
 444                 break;
 445         default:
 446                 memval |= QSPI_CMD_READ;
 447                 memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
 448                 memval |= QSPI_SETUP0_READ_NORMAL;
 449                 break;
 450         }
 451
 452         writel(memval, &priv->base->setup0);
 453 }
 454
 455
 456 static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
 457 {
 458         struct ti_qspi_priv *priv = dev_get_priv(bus);
 459
 460         ti_spi_set_speed(priv, max_hz);
 461
 462         return 0;
 463 }
 464
 465 static int ti_qspi_set_mode(struct udevice *bus, uint mode)
 466 {
 467         struct ti_qspi_priv *priv = dev_get_priv(bus);
 468         return __ti_qspi_set_mode(priv, mode);
 469 }
 470
 471 static int ti_qspi_claim_bus(struct udevice *dev)
 472 {
 473         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 474         struct spi_slave *slave = dev_get_parent_priv(dev);
 475         struct ti_qspi_priv *priv;
 476         struct udevice *bus;
 477
 478         bus = dev->parent;
 479         priv = dev_get_priv(bus);
 480
 481         if (slave_plat->cs > priv->num_cs) {
 482                 debug("invalid qspi chip select\n");
 483                 return -EINVAL;
 484         }
 485
 486         __ti_qspi_setup_memorymap(priv, slave, true);
 487
 488         return __ti_qspi_claim_bus(priv, slave_plat->cs);
 489 }
 490
 491 static int ti_qspi_release_bus(struct udevice *dev)
 492 {
 493         struct spi_slave *slave = dev_get_parent_priv(dev);
 494         struct ti_qspi_priv *priv;
 495         struct udevice *bus;
 496
 497         bus = dev->parent;
 498         priv = dev_get_priv(bus);
 499
 500         __ti_qspi_setup_memorymap(priv, slave, false);
 501         __ti_qspi_release_bus(priv);
 502
 503         return 0;
 504 }
 505
 506 static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 507                         const void *dout, void *din, unsigned long flags)
 508 {
 509         struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
 510         struct ti_qspi_priv *priv;
 511         struct udevice *bus;
 512
 513         bus = dev->parent;
 514         priv = dev_get_priv(bus);
 515
 516         if (slave->cs > priv->num_cs) {
 517                 debug("invalid qspi chip select\n");
 518                 return -EINVAL;
 519         }
 520
 521         return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
 522 }
 523
 524 static int ti_qspi_probe(struct udevice *bus)
 525 {
 526         /* Nothing to do in probe */
 527         return 0;
 528 }
 529
 530 static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
 531 {
 532         struct ti_qspi_priv *priv = dev_get_priv(bus);
 533         const void *blob = gd->fdt_blob;
 534         int node = bus->of_offset;
 535         fdt_addr_t addr;
 536         void *mmap;
 537
 538         priv->base = map_physmem(dev_get_addr(bus), sizeof(struct ti_qspi_regs),
 539                                  MAP_NOCACHE);
 540         priv->memory_map = map_physmem(dev_get_addr_index(bus, 1), 0,
 541                                        MAP_NOCACHE);
 542         addr = dev_get_addr_index(bus, 2);
 543         mmap = map_physmem(dev_get_addr_index(bus, 2), 0, MAP_NOCACHE);
 544         priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : mmap;
 545
 546         priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
 547         if (priv->max_hz < 0) {
 548                 debug("Error: Max frequency missing\n");
 549                 return -ENODEV;
 550         }
 551         priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
 552
 553         debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
 554               (int)priv->base, priv->max_hz);
 555
 556         return 0;
 557 }
 558
 559 static int ti_qspi_child_pre_probe(struct udevice *dev)
 560 {
 561         struct spi_slave *slave = dev_get_parent_priv(dev);
 562         struct udevice *bus = dev_get_parent(dev);
 563         struct ti_qspi_priv *priv = dev_get_priv(bus);
 564
 565         slave->memory_map = priv->memory_map;
 566         return 0;
 567 }
 568
 569 static const struct dm_spi_ops ti_qspi_ops = {
 570         .claim_bus      = ti_qspi_claim_bus,
 571         .release_bus    = ti_qspi_release_bus,
 572         .xfer           = ti_qspi_xfer,
 573         .set_speed      = ti_qspi_set_speed,
 574         .set_mode       = ti_qspi_set_mode,
 575 };
 576
 577 static const struct udevice_id ti_qspi_ids[] = {
 578         { .compatible = "ti,dra7xxx-qspi" },
 579         { .compatible = "ti,am4372-qspi" },
 580         { }
 581 };
 582
 583 U_BOOT_DRIVER(ti_qspi) = {
 584         .name   = "ti_qspi",
 585         .id     = UCLASS_SPI,
 586         .of_match = ti_qspi_ids,
 587         .ops    = &ti_qspi_ops,
 588         .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
 589         .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
 590         .probe  = ti_qspi_probe,
 591         .child_pre_probe = ti_qspi_child_pre_probe,
 592 };
 593 #endif /* CONFIG_DM_SPI */